The entirety of U.S. Pat. No. 8,781,008 titled “Highly-Spectrally-Efficient Transmission Using Orthogonal Frequency Division Multiplexing” is hereby incorporated herein by reference.
Limitations and disadvantages of conventional approaches to reception of signals in the presence of nonlinear distortion will become apparent to one of skill in the art, through comparison of such approaches with some aspects of the present method and system set forth in the remainder of this disclosure with reference to the drawings.
Methods and systems are provided for nonlinearity compensation for reception of OFDM signals, substantially as illustrated by and/or described in connection with at least one of the figures, as set forth more completely in the claims.
As utilized herein the terms “circuits” and “circuitry” refer to physical electronic components (i.e. hardware) and any software and/or firmware (“code”) which may configure the hardware, be executed by the hardware, and or otherwise be associated with the hardware. As used herein, for example, a particular processor and memory may comprise a first “circuit” when executing a first one or more lines of code and may comprise a second “circuit” when executing a second one or more lines of code. As utilized herein, “and/or” means any one or more of the items in the list joined by “and/or”. As an example, “x and/or y” means any element of the three-element set {(x), (y), (x, y)}. As another example, “x, y, and/or z” means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. As utilized herein, the terms “e.g.,” and “for example” set off lists of one or more non-limiting examples, instances, or illustrations. As utilized herein, circuitry is “operable” to perform a function whenever the circuitry comprises the necessary hardware and code (if any is necessary) to perform the function, regardless of whether performance of the function is disabled, or not enabled, by some user-configurable setting.
The encoder circuitry 102 receives a vector of bits B′ which are the bits of a particular OFDM symbol. The encoder circuitry 102 converts the bits B′, to a vector of bits B, in accordance with a forward error correction (FEC) algorithm (e.g., Reed-Solomon, Low-Density Parity Check, Turbo, and/or the like).
The mapper circuit 104, is operable to map the vector B to a vector A according to a selected modulation scheme. For example, for a quadrature amplitude modulation (QAM) scheme having an alphabet size of M (M-QAM), the mapper may map each Log2(M) bits of B to a value represented as a complex number and/or as in-phase (I) and quadrature-phase (Q) components. Although M-QAM is used for illustration in this disclosure, aspects of this disclosure are applicable to any modulation scheme (e.g., pulse amplitude modulation (PAM), amplitude shift keying (ASK), phase shift keying (PSK), frequency shift keying (FSK), etc.). Additionally, points of the M-QAM constellation may be regularly spaced (“on-grid”) or irregularly spaced (“off-grid”). Furthermore, the constellation used by the mapper 104 may be optimized for best bit-error rate (BER) performance (or adjusted to achieve a target BER) that is related to log-likelihood ratio (LLR) and to optimizing mean mutual information bit (MMIB) (or achieving a target MMIB).
The ISC generation circuitry 106 is operable to process A to generate a vector C. The elements of A are referred to herein as “virtual subcarrier values” of the particular OFDM symbol and the elements of C are referred to herein as the corresponding “physical subcarrier values” of the particular OFDM symbol, where: the vector A comprises N values, the vector C comprises P values, N and P are positive integers, N≧2, and N≧P. The N elements of A are represented herein as a1:aN, with any particular one of the values represented as an. The P elements of C are represented herein as c1:cP, with any particular one of the values represented as cP. In an example implementation, the processing performed by the circuitry 106 may comprise cyclic filtering and/or decimation such that each of the ISC values of C depends on a plurality (perhaps all) of the elements of A. In an example implementation, the circuitry 106 may be similar to, or the same as, circuits 104 and 106 of the above incorporated Unites States Patent Application Publication US2013/0343473. In an example implementation, Δ (an integer) pilot symbols may be inserted at the IFFT and the total number of physical subcarriers may be P+Δ, where P is thus the quantity of data-carrying subcarriers.
The inverse fast Fourier transform (IFFT) circuit 108 is operable to convert the physical subcarrier value vector C (of length P) to a corresponding vector of P time-domain samples (i.e., the time-domain representation of the particular OFDM symbol).
The analog front end (AFE) 110 is operable to convert the P time-domain values output by IFFT 108 to an analog representation, upconvert the resulting analog signal, and amplify the upconverted signal for transmission onto a channel 112. Thus, the transmitter front-end 118 may comprise, for example, a digital-to-analog converter (DAC), mixer, and/or power amplifier. The front-end 118 may introduce nonlinear distortion and/or phase noise (and/or other non-idealities) to the transmitted signal 117. The nonlinear distortion introduced by the circuit 118 may be represented as NLTx which may be, for example, a polynomial, or an exponential (e.g., Rapp model). The model of the nonlinear distortion may incorporate memory (e.g., Volterra series). The transmitted values C, after being converted to the time domain, experiencing the nonlinear distortion introduced by the AFE 110, and passing through the channel 112 (which may also introduce nonlinear distortion and/or noise), emerge as a signal 113.
The AFE 202 is operable to process the signal 113 corresponding to a particular OFDM signal to a vector of S′ samples of the particular OFDM symbol. Such processing may comprise, amplification, downconversion (to IF or baseband), and analog-to-digital conversion. Thus, the receiver front-end 202 may comprise, for example, a low-noise amplifier, a mixer, and/or an analog-to-digital converter. The AFE 202 may, for example, sample the received signal 113 P times per OFDM symbol period resulting in a S′ of length P (where pilot symbols are used, the AFE 202 may sample P+Δ times per OFDM symbol). Due to non-idealities, the receiver front-end 202 may introduce nonlinear distortion and/or phase noise to the signal S′. The nonlinear distortion introduced by the front end 202 may be represented as NLRx which may be, for example, a polynomial, or an exponential (e.g., Rapp model). The model of the nonlinear distortion may incorporate memory (e.g., Volterra series).
The time domain preprocessing circuitry 204 is operable to perform time-domain processing of the samples S′ to generate received physical subcarrier value vector S. Such processing may include, for example, timing acquisition, phase correction, frequency correction, decimation, DC removal, IQ mismatch correction, filtering, windowing, removal of pilot symbols, cyclic prefix removal, and/or the like.
The FFT 208 is operable to convert the time-domain physical subcarrier value vector S (of length P) to a corresponding vector of P frequency-domain samples (i.e., convert the time-domain representation of S to the frequency-domain representation of S).
The frequency domain preprocessing circuitry 206 is operable to perform frequency domain processing of the output of the FFT 208 to generate a vector Y, which is a vector of N received virtual subcarrier values. Such processing may include, for example, performing the inverse of the ICI generation circuitry 106 (
The RSSE circuitry 212 is operable to perform reduced state sequence estimation on the vector Y to generate a vector  which is the receiver's decision vector (“best guess” as to the transmitted virtual subcarrier value vector A). Details of an example implementation of RSSE circuitry 212 are described below with reference to
The nonlinear distortion model determination circuitry 214 is operable to determine a model, NL, that represents/enables reproduction of (to a desired accuracy) the nonlinear distortion experienced by the signal S′ in the transmitter, the channel, and/or the receiver. In an example implementation, the nonlinear distortion introduced by the AFE 110 of the transmitter may be dominant and NL may be a representation of NLTx. The nonlinear distortion model, NL, may be, for example, a logical and/or mathematical expression, a look-up table, and/or any other suitable representation of the nonlinear distortion. Any one or more of a variety of model types may be used for NL, with each model type being characterized by one or more parameters. The model type and/or parameter values may be communicated directly by the transmitter (e.g., during handshaking) and/or may be learned by the receiver by processing signals received from the transmitter (e.g., selection of the model type and/or training of the parameter values may be based on preambles sent by the transmitter). In an example implementation, NL may comprise an AM/AM parameter whose value is dependent on transmitted signal strength, and an AM/PM parameter whose value is dependent on transmitted signal strength. In such an example implementation, received signal strength may be used as a proxy for transmitted signal strength and the received signal strength may be applied to the look-up table to determine appropriate values of the AM/AM and AM/PM parameters.
The interference estimation circuitry 210 is operable to estimate the interference, F, present in the received virtual subcarrier values Y, based on Y and based on NL. Details of example implementations of 210 are described below with reference to
The buffer circuitry 310 is operable to, upon completion of processing a particular received virtual subcarrier value of the OFDM symbol being processed, latch the selected survivor vectors such that those survivors are available for processing the next received virtual subcarrier value of the OFDM symbol. Thus, in
The successor generation circuitry 312 is operable to extend each of the M survivors from the previous iteration, , to K successors, resulting in successors . Elements of successor vector are represented herein as , where is the element by which survivor was extended to create successor . The number of successors generated thus depends on the number of survivors, M, retained for each received virtual subcarrier value and the number of possible symbol transmitted virtual subcarrier values for which it is desired to search. Higher values of M and K may achieve improved results at the expense of increased size and complexity. In an example implementation, the value of K may be chosen to be the size of the constellation used by mapper 104 (
The nonlinear distortion circuitry 302 is operable to, for each of the M×K successors , generate a candidate vector by introducing nonlinear distortion to the successor Gnm,k. Elements of candidate vector are represented herein as , where is the estimated constellation symbol of the (m,k) candidate for subcarrier index n, is the estimated constellation symbol of the (m,k) candidate for subcarrier index n−1, and so on (where n is less than D, D-n elements may be values from an initialization of the RSSE circuitry).
The nonlinear distortion introduced to each successor is determined based on NL from the nonlinear distortion model determination circuitry 214 (
The metric calculation circuitry 306 is operable to calculate branch a path metric, PMnm,k for each of the candidates , and output the path metrics to the survivor selection circuitry 308. The path metric for candidate may be calculated as PMnm,k=BMnm,k+PMn−1m,k, where BMnm,k is the branch metric for candidate . The branch metric for candidate may be calculated based on F. The manner in which the branch metric is calculated varies for different implementations. Some example branch metric calculations are described below with reference to
The survivor selection circuitry 308 is operable to compare the path metrics for each of the candidates and select the M best candidates (corresponding to the M best path metrics) as the survivors .
The buffer circuitry 314 is operable to buffer samples of signal Y and/or initialization samples and may shift the samples out as signal Yn. For example, the first n elements of Yn may be equal to the first n elements of Y and the remaining (D−n) elements of Yn may be known values used for initialization of the RSSE circuitry.
The notation fnm,k represents an estimate of the aggregate interference present in the received virtual subcarrier value having index n for candidate . The aggregate interference estimate may, for example, be a complex number representing the magnitude and phase of the interference. The notation F represents the vector (of length M×K) of aggregate interference estimates for all of the candidates (i.e., F=fn1,1:fnM,K). In some instances, the estimated aggregate interference may depend only on n (the received virtual subcarrier index) and may be the same for all of the candidates (i.e., each of the estimates fn1,1:fnM,K takes on the same value), but in other instances, the interference estimates may differ among the candidates .
In a first variation, the aggregate interference estimate for candidate may be calculated exhaustively taking into account each of the other N−1 virtual subcarriers. This exhaustive calculation may comprise calculating fnm,kαΣi=0N−1Σj=0N−1zi·zj*·zn−i+j, where: α is a parameter (or vector of parameters) determined by nonlinear model determination block 208, zi=yi for i≧n; zi=gim,k for i<n; zj=yj for j≧n, zj=gjm,k for j<n, yi is a received virtual subcarrier value for subcarrier having index i, yj is the received virtual subcarrier value for subcarrier having index j, gim,k is the decision for the subcarrier having index i for the (m,k) candidate, where gim,k is the decision the subcarrier having index j for the (m,k) candidate.
In a second variation, the aggregate interference estimate for candidate may be calculated taking into account only a selected subset of the other N−1 virtual subcarriers. This may reduce the amount of calculations necessary. This selective calculation may comprise calculating fnm,k=αΣiεQΣjεQzi·zj* ·zn−i∓j, where α is a parameter (or vector of parameters) determined by nonlinear model determination block 208, Q is a subset of the set 1:N; zx=yx for x≧n, zx=gxm,k for x<n, and x is used as a generic for i and j. For example, only indexes of virtual subcarriers having power above a determined threshold may be included in the set Q (based on the assumption that low-energy virtual subcarriers will experience relatively little nonlinear distortion and thus not contribute a lot of interference). The smaller the size of Q relative to the size of N, the more this selective calculation will reduce computational complexity/overhead.
Thus, common to both variations above is that, when calculating the interference present in received virtual subcarrier having index n due to another virtual subcarrier having index x for candidate , if a decision as to a transmitted virtual subcarrier having index x has already been generated by the RSSE circuitry (i.e., x <n), then the decided value of x (i.e., gxm,k) is used in the calculation, but if a decision as to a transmitted virtual subcarrier having index x has not yet been generated by the RSSE circuitry (i.e., x>n), then the received virtual subcarrier value having index x (i.e., yx) is used for the calculation (based on the assumption that the interference in that received signal is relatively small compared to the desired signal and, therefore, error introduced is tolerable).
Once the estimated aggregate interference fnm,k has been determined, the branch metric (represented as BMnm,k) for candidate may be calculated. In an example implementation, the following expression may be used: BMnm,k=|yn−−fnm,k|2.
The clipped subcarrier determination circuit 602 is operable to determine which transmitted virtual subcarriers values were digitally clipped in the transmitter during the transmission that resulted in signal 113. The circuit 602 then outputs the indexes of the clipped subcarriers to the circuit 604 as vector I. In an example implementation, the transmitter may directly send such information (e.g., in a header) and the circuit 602 may simply extract the information. In another example implementation, the circuit 602 may determine which transmitted virtual subcarrier values were digitally clipped based on the magnitude of the received virtual subcarrier values.
With a digital clipping model, the interference F may be determined by NL and I. Thus, once the circuitry 604 has been provided NL and I for a particular OFDM symbol, calculation of F may be straightforward (with much less computational complexity/overhead than for the implementation described with reference to
The nonlinear distortion circuitry 702 is operable to introduce nonlinear distortion to the received virtual subcarrier vector Y to generate Y′. The nonlinear distortion introduced is determined based on NL from the nonlinear distortion model determination circuitry 214 (
The combiner 704 combines Y and Y′ such that the output is the difference between Y and Y′. In this example implementation, the output of combiner 704 is —an initial approximation of the interference introduced by the nonlinear distortion experienced by Y. It is acknowledged that, because there is interference present in Y as a result of the nonlinear distortion that Y experienced en route to the circuitry 210 (at least a portion of which NL is attempting to model), this is not going to be an exact measure of the actual interference present in Y. Nevertheless, if the strength of the interference present in Y is relatively small compared to the desired signal strength, the amount of additional interference contributed by the existing interference during application of NL may be small enough that is a suitable approximation.
Once is calculated as in
As is shown, in
During the second iteration on the particular OFDM symbol, the successors are processed similarly to the first iteration. For each subcarrier n, the sequential processing during the second iteration on the particular OFDM symbol comprises: extending, by successor generation circuitry 312, each of the M selected survivors () from the previous subcarrier to K successors () distorting, by nonlinear distortion circuitry 302, each of the M×K successors to generate candidates ; calculating, by metrics calculation circuitry 306, metrics for each candidate using ; and selecting, by survivor selection circuitry 308, the M best survivors . Thus, the metrics for candidate during the first iteration on the particular OFDM symbol are based on and (as a result of using F). Upon completing processing of all N subcarriers, the M selected survivors are , and the best of these () is selected for output to downstream circuitry such as a FEC decoder. In other implementations, additional iterations may be performed to refine these survivors even further.
In accordance with an example implementation of this disclosure, an electronic receiver (e.g., 200) may comprise nonlinear distortion modeling circuitry (e.g., 214), interference estimation circuitry (e.g., 210), and sequence estimation circuitry (e.g., 212). The receiver may receive an orthogonal frequency division multiplexing (OFDM) symbol in the form of an electromagnetic signal (e.g., 113). The nonlinear distortion modeling circuitry may generate a nonlinear distortion model (e.g., NL) that models nonlinear distortion introduced to the received electromagnetic signal en route to the sequence estimation circuitry. The interference estimation circuitry may estimate inter- subcarrier interference present in the received OFDM symbol based on the generated nonlinear distortion model. The sequence estimation circuitry may sequentially process a plurality of received virtual subcarrier values (e.g., Y) of the OFDM symbol using the estimated inter-subcarrier interference. The processing may result in decisions as to a plurality of transmitted virtual subcarrier values (e.g., ) that correspond to the plurality of received virtual subcarrier values. The estimating of the inter-subcarrier interference may comprise applying the nonlinear distortion model to one or more candidate vectors (e.g., Gnm,k) generated by the sequence estimation circuitry. The estimating of the inter-subcarrier interference may comprise determining which one or more of the transmitted virtual subcarrier values were digitally clipped in a transmitter from which the received electromagnetic signal originated. The estimating of the inter-subcarrier interference may comprise calculating the inter-subcarrier interference based on which one or more of the plurality of transmitted virtual subcarrier values were digitally clipped in the transmitter and based on the generated nonlinear distortion model. The determining which one or more of the plurality of transmitted virtual subcarrier values were digitally clipped in the transmitter may comprise determining magnitude of each of the plurality of received virtual subcarrier values. The estimating of the inter- subcarrier interference may comprise applying the nonlinear distortion model to the received electromagnetic signal to generate an intermediate electromagnetic signal (e.g., Y′). The estimating of the inter-subcarrier interference may comprise subtracting the received electromagnetic signal from the intermediate electromagnetic signal, a result of the subtraction being the estimate of the inter-subcarrier interference. The plurality of received virtual subcarrier values may comprise a first received virtual subcarrier value (e.g., y0) and a second received virtual subcarrier value (e.g., y1). The sequential processing may comprise processing the first received virtual subcarrier value to generate a decision as to a first one of the plurality of transmitted virtual subcarrier values (e.g., ) using an estimate of interference present in the first received virtual subcarrier value (e.g., f0) that is based on the second received virtual subcarrier value. The sequential processing may comprise processing the second received virtual subcarrier value to generate a decision as to a second one of the plurality of transmitted virtual subcarrier values (e.g., ) using an estimate of interference present in the second received virtual subcarrier value (e.g., f1) that is based on the generated decision as to the first one of the plurality of transmitted virtual subcarrier values. The plurality of received virtual subcarrier values may comprise a third received virtual subcarrier value (e.g., y2). The estimate of interference present in the second received virtual subcarrier value may be based on the third received virtual subcarrier value. The sequential processing may comprise processing the third received virtual subcarrier value to generate a decision as to a third one of the plurality of transmitted virtual subcarrier values (e.g., ) using an estimate of interference present in the third received virtual subcarrier value (e.g., f3) that is based on the generated decision as to the first one of the plurality of transmitted virtual subcarrier values and on the generated decision as to the second one of the plurality of transmitted virtual subcarrier values. The sequential processing may comprise generating a plurality of branch metrics (e.g., BM01,1:BMN−1M,K), wherein each of the plurality of branch metrics is based on a corresponding one of the received virtual subcarrier values, a candidate vector generated by the sequence estimation circuitry, and the estimated inter-subcarrier interference. For each of the plurality of received virtual subcarrier values, the estimating of the inter-subcarrier interference may considers all others of the received virtual subcarrier values or only a subset of all others of the plurality of received virtual subcarrier values. The subset of all others of the plurality of received virtual subcarrier values may correspond to those of the plurality of received virtual subcarrier values having a magnitude above a determined threshold.
The present method and/or system may be realized in hardware, software, or a combination of hardware and software. The present methods and/or systems may be realized in a centralized fashion in at least one computing system, or in a distributed fashion where different elements are spread across several interconnected computing systems. Any kind of computing system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software may be a general-purpose computing system with a program or other code that, when being loaded and executed, controls the computing system such that it carries out the methods described herein. Another typical implementation may comprise an application specific integrated circuit or chip. Some implementations may comprise a non-transitory machine-readable (e.g., computer readable) medium (e.g., FLASH drive, optical disk, magnetic storage disk, or the like) having stored thereon one or more lines of code executable by a machine, thereby causing the machine to perform processes as described herein.
While the present method and/or system has been described with reference to certain implementations, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present method and/or system. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present disclosure without departing from its scope. Therefore, it is intended that the present method and/or system not be limited to the particular implementations disclosed, but that the present method and/or system will include all implementations falling within the scope of the appended claims.
This application is a continuation of U.S. patent application Ser. No. 14/298,373, filed Jun. 6, 2014 (now patented as U.S. Pat. No. 8,891,701).
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Number | Date | Country | |
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Number | Date | Country | |
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Parent | 14298373 | Jun 2014 | US |
Child | 14541312 | US |