Patent Application
20160118126
A claim for priority under 35 U.S.C. §119 is made to Korean Patent Application No. 10-2014-0143583 filed Oct. 22, 2014, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.
Semiconductor memory devices may be volatile or nonvolatile. The volatile semiconductor memory devices may perform read and write operations at high speed; contents stored therein may be lost at power-off. The nonvolatile semiconductor memory devices may retain contents stored therein. The nonvolatile semiconductor memory devices may be used to store contents which may be retained regardless of whether or not they are powered.
A flash memory device may be a typical nonvolatile semiconductor memory device. The flash memory device may be widely used as a voice and image data storing medium of information appliances, such as a computer, a cellular phone, a PDA, a digital camera, a camcorder, a voice recorder, an MP3 player, a handheld PC, a game machine, a facsimile, a scanner, a printer, and the like.
As a demand on a mass storage device increases, a multi-level cell (MLC) or multi-bit memory device is widely used which stores multiple bits per cell. However, in a memory device employing multi-level cells, threshold voltages of memory cells may be identified as a plurality of states within a restricted voltage window. Threshold voltages of memory cells vary with a characteristic of the memory device or the lapse of time and a peripheral temperature. Hence, a variety of methods for identifying data states are used to improve data integrity. Among the methods, one is to prevent the drooping and spreading of threshold voltage distributions corresponding to program states. That is, such a method is to reduce the drooping and spreading of threshold voltage distributions corresponding to pieces of different data. However, the method necessitates a program time additionally, thereby lowering performance.
Embodiments of the inventive concepts provide nonvolatile memory devices and programming methods thereof capable of minimizing lowering of performance of the nonvolatile memory devices, thereby making threshold voltage distributions of memory cells better.
One aspect of embodiments of the inventive concept is directed to provide program methods of a nonvolatile memory device which include programming memory cells to a target state using a verification voltage and incremental step pulses, selecting memory cells, each having a threshold voltage lower than a supplementary verification voltage, from among the memory cells programmed to the target state, and applying a supplementary program voltage to the selected memory cells, wherein the supplementary verification voltage is equal to or higher than the verification voltage and the supplementary program voltage is equal to or lower than a program voltage, provided in a program loop where a programming of the memory cells to the target state is completed, from among the incremental step pulses.
Another aspect of embodiments of the inventive concept is directed to provide nonvolatile memory devices which include a cell array, a page buffer, a voltage generator, and control logic. The cell array includes a plurality of memory cells. The page buffer is connected to the cell array through bit lines and transfers data to be written at selected memory cells to the bit lines. The voltage generator provides an incremental program pulse and a verification voltage to a word line connected with the selected memory cells at a normal program operation and provides a supplementary verification voltage and a supplementary program voltage to the word line at a supplementary program operation. The control logic controls the page buffer and the voltage generator to write the data at the selected memory cells depending on the normal program operation and the supplementary program operation. During the normal program operation, the page buffer provides the control logic with pass loop count information corresponding to each of target states to which the plurality of memory cells is programmed. Based on the pass loop count information, the control logic determines a supplementary verification voltage and a supplementary program voltage that are associated with at least one of the target states.
Still another aspect of embodiments of the inventive concept is directed to provide program methods of a nonvolatile memory device which include performing a normal program operation where memory cells are programmed to a target state using incremental step pulses, and performing a supplementary program operation where memory cells, each having a threshold voltage lower than a supplementary verification voltage, from among the memory cells are selected and a supplementary program voltage is applied to the selected memory cells, wherein the supplementary program voltage is higher than or equal to a verification voltage used at the normal program operation, and wherein the supplementary program voltage is lower than or equal to a program voltage that is used in a program loop where the target state is program passed at the normal program operation.
It is noted that aspects of the inventive concept described with respect to one embodiment, may be incorporated in a different embodiment although not specifically described relative thereto. That is, all embodiments and/or features of any embodiment can be combined in any way and/or combination. These and other objects and/or aspects of the present inventive concept are explained in detail in the specification set forth below.
The above and other objects and features will become apparent from the following description with reference to the following figures, wherein like reference numerals refer to like parts throughout the various figures unless otherwise specified, and wherein
FIG, 18 is a diagram schematically illustrating an effect according to embodiments of the inventive concept;
Embodiments will be described in detail with reference to the accompanying drawings. The inventive concept, however, may be embodied in various different forms, and should not be construed as being limited only to the illustrated embodiments. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the concept of the inventive concept to those skilled in the art. Accordingly, known processes, elements, and techniques are not described with respect to some of the embodiments of the inventive concept. Unless otherwise noted, like reference numerals denote like elements throughout the attached drawings and written description, and thus descriptions will not be repeated. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.
It will be understood that, although the terms “first”, “second”, “third”, etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.
Spatially relative terms, such as “beneath”, “below”, “lower”, “under”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the example terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being “on”, “connected to”, “coupled to”, or “adjacent to” another element or layer, it can be directly on, connected, coupled, or adjacent to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to”, “directly coupled to”, or “immediately adjacent to” another element or layer, there are no intervening elements or layers present.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In an embodiment of the present inventive concept, a three dimensional (3D) memory array is provided. The 3D memory array is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate and circuitry associated with the operation of those memory cells, whether such associated circuitry is above or within such substrate. The term “monolithic” means that layers of each level of the array are directly deposited on the layers of each underlying level of the array.
In an embodiment of the present inventive concept, the 3D memory array includes vertical NAND strings that are vertically oriented such that at least one memory cell is located over another memory cell. The at least one memory cell may comprise a charge trap layer. Each vertical NAND string may include at least one select transistor located over memory cells, the at least one select transistor having the same structure with the memory cells and being formed monolithically together with the memory cells.
Although corresponding plan views and/or perspective views of some cross-sectional view(s) may not be shown, the cross-sectional view(s) of device structures illustrated herein provide support for a plurality of device structures that extend along two different directions as would be illustrated in a plan view, and/or in three different directions as would be illustrated in a perspective view. The two different directions may or may not be orthogonal to each other. The three different directions may include a third direction that may be orthogonal to the two different directions. The plurality of device structures may be integrated in a same electronic device. For example, when a device structure (e.g., a memory cell structure or a transistor structure) is illustrated in a cross-sectional view, an electronic device may include a plurality of the device structures (e.g., memory cell structures or transistor structures), as would be illustrated by a plan view of the electronic device. The plurality of devices may be arranged in an array and/or in a two-dimensional pattern.
The following patent documents, which are hereby incorporated by reference, describe suitable configurations for three-dimensional memory arrays, in which the three-dimensional memory array is configured as a plurality of levels, with word lines and/or bit lines shared between levels: U.S. Pat. Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and US Pat. Pub. No. 2011/0233648.
The cell array 110 is connected to the row decoder 120 through word lines WL0 to WLn-1 and selection lines SSL and GSL. The cell array 110 is connected to the page buffer 130 through bit lines BL0 to BLi-1. The cell array 110 includes a plurality of cell strings (e.g., NAND cell strings). The cell strings may constitute a memory block BLK. In some example embodiments, a channel of each cell string may be formed in a vertical or horizontal direction.
At a program operation, memory cells may be selected by a predetermined unit (e.g., 2 KB (page) or 512 B) by controlling the word lines WL0 to WLn-1 and the selection lines SSL and GSL. At a read operation, memory cells may be selected by a predetermined unit (e.g., page or less). Threshold voltage distributions of memory cells may start to vary due to various causes from a point in time the program operation is completed. A threshold voltage variation reduces read margin, thereby lowering integrity of data. Program methods according to some embodiments of the inventive concept make a threshold voltage distribution better, thereby minimizing a decrease in performance and improving integrity of data. This will be more fully described together with describing functions of the page buffer 130 and the control logic 150.
The row decoder 120 selects one of memory blocks of the cell array 110 in response to an address ADD. The row decoder 120 selects one of the word lines WL0 to WLn-1 of the selected memory block. The row decoder 120 transfers a program voltage Vpgm or a verification voltage Vvfy from the voltage generator 126 to the selected word line. During a program operation, the row decoder 120 transfers a program/verification voltage Vpgm/Vvfy to a selected word line and a pass voltage Vpass to unselected word lines. During a read operation, the row decoder 120 transfers a selection read voltage Vrd to a selected word line and a non-selection read voltage Vread to unselected word lines.
The page buffer 130 acts as a write driver at a program operation and as a sense amplifier at a read operation. The page buffer 130 transfers bit line voltages corresponding to pieces of program data to bit lines of the cell array 110 at a program operation. At a read operation, the page buffer 130 senses data stored in a selected memory cell through a bit line. The page buffer 130 latches the sensed data and transfers it to the input/output buffer 140.
Upon programming memory cells, a program voltage is provided to a word line, based on an incremental step pulse programming (ISPP) manner. During the ISPP-based program operation, the applying of a program pulse and the applying of verification pulses are performed in a program loop. Selected memory cells are programmed to target states using a plurality of program loops. Even though the selected memory cells are programmed to the target states, the page buffer 130 according to some embodiments of the inventive concept maintains the program data without initialization. That is, the page buffer 130 stores data corresponding to the target states at an internal latch or a separate storage element. For this purpose, the page buffer 130 contains a state buffer unit 135.
During the program operation, the page buffer 130 provides the control logic 150 with pass loop count information PLCI corresponding to a point in time when the programming of the selected memory cells to the target states is passed. For example, the page buffer 130 provides the control logic 130 with a loop count at which the programming of memory cells, which will be programmed to a target state P1, from among selected memory cells is completed. When a loop count at which the programming of memory cells to be programmed to the target state P1 is completed is L4, the page buffer 130 provides the control logic 150 with the pass loop count information PLCI.
During a normal program operation, selected memory cells are programmed in the ISPP manner under a control of the control logic 150. After the normal program operation is completed, a supplementary program operation is executed according to a control of the control logic 150. For the supplementary program operation, the page buffer 130 uses program data stored at the state buffer unit 135. That is, specific memory cells are selected after the normal program operation ends and then are additionally programmed. The supplementary program operation makes it possible to increase threshold voltages of memory cells which have relatively low threshold voltages at the target states.
In some example embodiments, the state buffer unit 135 may be implemented with a separate storage element formed in the page buffer 130, such as, for example, a latch. In some embodiments, the state buffer unit 135 may be implemented with reserved latches of the page buffer 130 without separate storage elements.
The input/output buffer 140 provides write data received at a program operation to the page buffer 130. At a read operation, the input/output buffer 140 outputs read data provided from the page buffer 130 to an external device. The input/output buffer 140 provides input addresses or commands CMDi to the row decoder 120 and/or the control logic 150.
The control logic 150 controls the page buffer 130 and the row decoder 120 in response to a command CMDi from the external device. The control logic 150 controls the page buffer 130 and the voltage generator 160 in response to a program command such that data loaded on the page buffer 130 is programmed at selected memory cells. The control logic 150 selects a voltage needed for the supplementary program operation in response to the pass loop count information PLCI from the page buffer 130 at the normal program operation. The control logic 150 controls the page buffer 130 and the voltage generator 160 such that the supplementary program operation about selected memory cells is performed using selected supplementary program voltage and supplementary verification voltage. The control logic 150 configures a supplementary program table 155 for selecting the supplementary program voltage and the supplementary verification voltage referring to the pass loop count information PLCI. The supplementary program table 155 may be implemented with a fuse box or a variety of nonvolatile memory media (or, elements).
The voltage generator 160 generates word line voltages to be supplied to word lines and a voltage to be supplied to a bulk (e.g., a well area), at which memory cells are formed, according to a control of the control logic 150. The word line voltages to be applied to the word lines may include the following: a program voltage, a pass voltage Vpgm, a pass voltage Vpass, selection and non-selection read voltages. At a read and a program operation, the voltage generator 160 generates selection line voltages VSSL and VGSL that are supplied to the selection lines SSL and GSL.
Also, the voltage generator 160 generates a supplementary program voltage Vpgm_S1 and a supplementary verification voltage Vvfy_S1 that are provided to a word line of memory cells at the supplementary program operation. It is assumed that pass loop count information PLCI about memory cells to be programmed to a target state P2 corresponds to a loop count L8. For the supplementary program operation about the memory cells to be programmed to the target state P2, the voltage generator 160 generates a level of a supplementary verification voltage Vvfy_S2 that is equal to or higher than that of a verification voltage Vvfy2 corresponding to the target state P2. For the supplementary program operation about the memory cells to be programmed to the target state P2, the voltage generator 160 produces a supplementary program voltage Vpgm_S8 of which the level is equal to or lower than that of a program voltage Vpgm 8 to be provided at a program operation of the loop count L8.
The nonvolatile memory device 100 according to some embodiments of the inventive concept improves a threshold voltage distribution using the supplementary program operation, with a decrease in a program speed minimized. That is, memory cells, having threshold voltages lower than a specific voltage, from among program-completed memory cells are selectively programmed. Threshold voltages of memory cells programmed through the supplementary program operation do not exceed the upper limit of a threshold voltage distribution corresponding to a target state.
In some example embodiments, at least one plate-shaped dummy word line may be formed between the ground selection line GSL and the word lines. Some embodiments provide that at least one plate-shaped dummy word line may be formed between the word lines and the string selection line SSL. Each word line cut, although not shown in
In
The memory block BLK according to some embodiments of the inventive concept may be implemented to have a merged word line structure where two word lines are merged to one.
To erase the CTF cell, a predetermined voltage (e.g., a voltage equal to or greater than 0 V) is applied to the control gate 115, and an erase voltage (e.g., 20 V) is applied to the channel 111. The CTF cell is erased because an electric field is formed in a direction from a bulk to the control gate 115 under to this bias condition.
In
The drooping and spreading of the threshold voltage distribution of CTF cells may occur in various shapes or states with time. The longer a lapse time from a programmed point in time, the more the drooping and spreading of a threshold voltage distribution of CTF cells increases. In some example embodiments, it is possible to solve degradation of a threshold voltage distribution due to a slow charge loss phenomenon as well as the fast charge loss phenomenon.
Threshold voltages of programmed CTF cells may form a threshold voltage distribution S1 immediately after a program operation is carried out. The threshold voltages of the programmed CTF cells form a threshold voltage distribution S1′ after a program operation is performed and then a specific time elapses. In
The drooping and spreading of the distribution may vary with time. As a time elapses, the drooping and spreading may enable threshold voltage distributions to overlap. A supplementary program operation according to some embodiments of the inventive concept makes it possible to supplement threshold voltages of memory cells that are placed at a lower side of a target state due to the drooping and spreading of a threshold voltage distribution or a program speed difference.
In operation 5110, the nonvolatile memory device 100 receives a program command and data from the external device. It is, of course, understood that an address is provided with the program command. The data is loaded on a page buffer 130 shown in
In operation 5120, the nonvolatile memory device 100 performs a normal program operation using an ISPP manner. That is, the nonvolatile memory device 100 applies a program voltage pulse that stepwise increases over the normal program operation. A plurality of verification voltages associated with a plurality of target states may be provided in every program loop to program multi-level cells. Pass loop count information PLCI associated with each target state may be provided to the control logic 150.
In operation 5130, the nonvolatile memory device 100 determines whether programming of the selected memory cells is completed. For example, the nonvolatile memory device 100 performs a verification operation about each target state. When a verification result about all target states indicates program pass, the normal program operation of the nonvolatile memory device 100 is determined as being completed. On this occasion, the method proceeds to operation 5140 to perform a supplementary program operation. In contrast, when memory cells exist which have threshold voltages lower than a verification voltage, the normal program operation of the nonvolatile memory device 100 is determined as being not completed. On this occasion, the method proceeds to operation 5120.
In operation 5140, the nonvolatile memory device 100 selects memory cells that necessitate the supplementary program operation. For example, the nonvolatile memory device 100 selects memory cells, corresponding to a specific target state, from among memory cells selected for programming. Memory cells, having threshold voltages lower than a reference value, from among memory cells corresponding to the selected target state are selected for the supplementary program operation. A supplementary verification voltage Vvfy_S1 is used to select memory cells to which the supplementary program operation is applied.
In operation 5150, the nonvolatile memory device 100 applies a supplementary program voltage to the memory cells selected for the supplementary program operation to perform the supplementary program operation. To program selected memory cells, the nonvolatile memory device 100 provides a program voltage that is equal to or lower than a program voltage corresponding to a pass loop count provided at the normal program operation. Threshold voltages of memory cells increase through the supplementary program operation and are lower than the upper limit defined.
As described above, the nonvolatile memory device 100 according to some embodiments of the inventive concept executes the supplementary program operation after the normal program operation is completed. Thus, it is possible to minimize an increase in a time taken to perform a program operation and to make a threshold voltage distribution of memory cells better.
In
In
Further, memory cells, having threshold voltages lower than a second supplementary verification voltage Vvfy_S2, from among memory cells having the target state P2 as the target state are selected for the supplementary program operation. The selected memory cells that have threshold voltages lower than the second supplementary verification voltage Vvfy_S2 are programmed to have a threshold voltage higher than the second supplementary verification voltage Vvfy_S2 using a supplementary program pulse. Likewise, a level of a second supplementary program voltage Vpgm_S2 is lower than or equal to that of a program voltage that is provided at a pass loop associated with the second program state P2 at the normal program operation. Thus, the supplementary program operation may prevent threshold voltages of the selected memory cells from excessively increasing.
Further, memory cells, having threshold voltages lower than a third supplementary verification voltage Vvfy_S3, from among memory cells having the target state P3 as the target state are selected for the supplementary program operation. The selected memory cells that have threshold voltages lower than the third supplementary verification voltage Vvfy_S3 are programmed to have threshold voltages higher than the third supplementary verification voltage Vvfy_S3 using a supplementary program pulse. Likewise, a level of a third supplementary program voltage Vpgm_S3 is lower than or equal to that of a program voltage that is provided at a pass loop associated with the third program state P3 at the normal program operation. Thus, the supplementary program operation may prevent threshold voltages of the selected memory cells from excessively increasing.
An incremental step pulse programming manner is applied to a normal program operation. That is, program pulses Vpgm1 through VpgmN that stepwise increase are sequentially applied to a word line connected with selected memory cells. After each program pulse is applied, verification voltages Vvfy1, Vvfy2, and Vvfy3 corresponding to the target states P1, P2, and P3 are sequentially applied to the word line connected with the selected memory cells. The normal program operation is executed using a plurality of program loops. A program loop includes the applying of a program pulse and the applying of the verification voltages Vvfy1, Vvfy2, and Vvfy3.
The programming of memory cells, to be programmed to the target state P1, from among the selected memory cells is completed in a program loop corresponding to a loop count L4. The memory cells programmed to have the target state P1 are program inhibited from a program loop corresponding to a loop count L5. The programming of memory cells, to be programmed to the target state P2, from among the selected memory cells is completed in a program loop corresponding to a loop count L8. The memory cells programmed to have the target state P2 are program inhibited from a program loop corresponding to a loop count L9. The programming of memory cells, to be programmed to the target state P3, from among the selected memory cells is completed in a program loop corresponding to a loop count L11. Thus, the normal program operation associated with the target states P1, P2, and P3 is completed in a program loop corresponding to the target count L11.
At the normal program operation, a page buffer 130 (refer to
The supplementary program operation may be executed following the normal program operation. During the supplementary program operation, first, memory cells that necessitate the supplementary program operation are selected. It is assumed that the supplementary program operation is applied to all target states P1, P2, and P3. First, there are selected memory cells, having threshold voltages lower than a first supplementary verification voltage Vvfy_S1, from among memory cells to be programmed to the target state P1. A first supplementary program voltage Vpgm_S1 is applied to the selected memory cells. In some example embodiments, the first supplementary verification voltage Vvfy_S1 is equal to or higher than a first verification voltage Vvfy1, and the first supplementary program voltage Vpgm_S1 is equal to or lower than a program voltage Vpgm4. The program voltage Vpgm4 is a program voltage for a normal program operation that is used at a program loop where the programming of memory cells to the target state S1 is completed.
Next, there are selected memory cells, having threshold voltages lower than a second supplementary verification voltage Vvfy_S2, from among memory cells to be programmed to the target state P2. A second supplementary program voltage Vpgm_S2 is applied to the selected memory cells. In example embodiments, the second supplementary verification voltage Vvfy_S2 is equal to or higher than a second verification voltage Vvfy2, and the second supplementary program voltage Vpgm_S2 is equal to or lower than a program voltage Vpgm8. The program voltage Vpgm8 is a program voltage for a normal program operation that is used at a program loop where the programming of memory cells to the target state S2 is completed.
Then, there are selected memory cells, having threshold voltages lower than a third supplementary verification voltage Vvfy_S3, from among memory cells to be programmed to the target state P3. A third supplementary program voltage Vpgm_S3 is applied to the selected memory cells. In some example embodiments, the third supplementary verification voltage Vvfy_S2 is equal to or higher than a third verification voltage Vvfy3, and the third supplementary program voltage Vpgm_S3 is equal to or lower than a program voltage Vpgm11. The program voltage Vpgm11 is a program voltage for a normal program operation that is used at a program loop where the programming of memory cells to the target state S3 is completed.
In
A difference between a threshold voltage distribution of fast cells and a threshold voltage distribution of slow cells may vary with target states P1, P2, and P3. The supplementary program operation may be applied to a target state where a difference between a threshold voltage distribution of fast cells and a threshold voltage distribution of slow cells is relatively great to minimize a program time.
In
An incremental step pulse programming manner is applied to a normal program operation. That is, program pulses Vpgm1 through VpgmN that stepwise increase are sequentially applied to a word line connected with selected memory cells. After each program pulse is applied, verification voltages Vvfy1, Vvfy2, and Vvfy3 corresponding to the target states P1, P2, and P3 are sequentially applied to the word line connected with the selected memory cells. The normal program operation is executed using a plurality of program loops.
The programming of memory cells, to be programmed to the target state P1, from among the selected memory cells is completed in a program loop corresponding to a loop count L4. The memory cells programmed to have the target state P1 are program inhibited from a program loop corresponding to a loop count L5. The programming of memory cells, to be programmed to the target state P2, from among the selected memory cells is completed in a program loop corresponding to a loop count L8. The memory cells programmed to have the target state P2 are program inhibited from a program loop corresponding to a loop count L9. The programming of memory cells, to be programmed to the target state P3, from among the selected memory cells is completed in a program loop corresponding to a loop count L11. Thus, the normal program operation associated with the target states P1, P2, and P3 is completed in a program loop corresponding to the target count L11.
At the normal program operation, a page buffer 130 (refer to
The supplementary program operation may be executed following the normal program operation. During the supplementary program operation, first, memory cells that necessitate the supplementary program operation are selected. When the supplementary program operation is applied to the target state P3, memory cells, having threshold voltages lower than a third supplementary verification voltage Vvfy_S3, from among memory cells to be programmed to the target state P3 are selected. A third supplementary program voltage Vpgm_S3 is applied to the selected memory cells. In some example embodiments, the third supplementary verification voltage Vvfy_S3 is equal to or higher than a third verification voltage Vvfy3, and the third supplementary program voltage Vpgm_S3 is equal to or lower than a program voltage Vpgm11. The program voltage Vpgm11 is a program voltage for a normal program operation that is used at a program loop where the programming of memory cells to the target state P3 is completed.
In
In
Next, memory cells, having threshold voltages lower than a third supplementary verification voltage Vvfy_S3, from among memory cells to be programmed to the target state P3 are selected for the supplementary program operation. The selected memory cells that have threshold voltages lower than a third supplementary verification voltage Vvfy_S3 are programmed to have a threshold voltage higher than or equal to the third supplementary verification voltage Vvfy_S3 using a supplementary program pulse. However, a level of the third supplementary program voltage Vpgm_S3 is lower than or equal to that of a program voltage that is provided at a pass loop associated with the third program state P3 at a normal program operation.
An incremental step pulse programming manner is applied to a normal program operation. That is, program pulses Vpgm1 through VpgmN that stepwise increase are sequentially applied to a word line connected with selected memory cells. After each program pulse is applied, verification voltages Vvfy1, Vvfy2, and Vvfy3 corresponding to the target states P1, P2, and P3 are sequentially applied to the word line connected with the selected memory cells. The normal program operation is executed using a plurality of program loops.
The programming of memory cells, to be programmed to the target state P1, from among the selected memory cells is completed in a program loop corresponding to a loop count L4. The memory cells programmed to have the target state P1 are program inhibited from a program loop corresponding to a loop count L5. The programming of memory cells, to be programmed to the target state P2, from among the selected memory cells is completed in a program loop corresponding to a loop count L8. The memory cells programmed to have the target state P2 are program inhibited from a program loop corresponding to a loop count L9. The programming of memory cells, to be programmed to the target state P3, from among the selected memory cells is completed in a program loop corresponding to a loop count L11. Thus, the normal program operation associated with the target states P1, P2, and P3 is completed in a program loop corresponding to the target count L11.
At the normal program operation, a page buffer 130 (refer to
The supplementary program operation may be executed following the normal program operation. During the supplementary program operation, first, memory cells that necessitate the supplementary program operation are selected. When the supplementary program operation is applied to the target state P2, memory cells, having threshold voltages lower than a second supplementary verification voltage Vvfy_S2, from among memory cells to be programmed to the target state P2 are selected. A second supplementary program voltage Vpgm_S2 is applied to the selected memory cells. In some example embodiments, the second supplementary verification voltage Vvfy_S2 is equal to or higher than a second verification voltage Vvfy2, and the second supplementary program voltage Vpgm_S2 is equal to or lower than a program voltage Vpgm8. The program voltage Vpgm8 is a program voltage for a normal program operation that is used at a program loop where the programming of memory cells to the target state S2 is completed.
Next, when the supplementary program operation is applied to the target state P3, memory cells, having threshold voltages lower than a third supplementary verification voltage Vvfy_S3, from among memory cells to be programmed to the target state P3 are selected. A third supplementary program voltage Vpgm_S3 is applied to the selected memory cells. In some example embodiments, the third supplementary verification voltage Vvfy_S3 is equal to or higher than a third verification voltage Vvfy3, and the third supplementary program voltage Vpgm_S3 is equal to or lower than a program voltage Vpgm11. The program voltage Vpgm11 is a program voltage for a normal program operation that is used at a program loop where the programming of memory cells to the target state S3 is completed.
When the normal program operation is completed, threshold voltages of memory cells programmed to the target state P3 are formed as illustrated in
However, a third supplementary verification voltage Vvfy_S3 that is higher than the third verification voltage Vvfy3 is applied to selected memory cells for the supplementary program operation. A level of the third supplementary verification voltage Vvfy_S3 may be greater by a (a being a real number more than 0) than that of the third verification voltage Vvfy3. Memory cells selected using the third supplementary verification voltage Vvfy_S3 are programmed to the target state P3, but are memory cells that necessitate the relatively small number of program loops due to relatively fast program speed. Some embodiments provide that memory cells that are placed at a lower side of the target state P3 may be selected by the third supplementary verification voltage Vvfy_S3 because the relatively great number of program loops is applied to the memory cells placed at the lower side of the target state P3 due to excessively slow program speed. However, it is understood that a characteristic of memory cells selected using the third supplementary verification voltage Vvfy_S3 is not limited to the above described.
Memory cells, selected for the supplementary program operation, from among memory cells to be programmed to the target state P3 and a supplementary verification voltage Vvfy_S3 applied thereto are described. However, the scope and spirit of the inventive concept may not be limited thereto. Supplementary verification voltages Vvfy_S2 and Vvfy_S3 may be selected which correspond to target states P1 and P2. However, a supplementary verification voltage associated with a corresponding target state may be higher than a verification voltage corresponding to the target state.
In
When the supplementary program operation is applied to memory cells the threshold voltages of which form threshold voltage distributions illustrated at the top (I) of
Memory cells, having threshold voltages lower than a second supplementary verification voltage Vvfy_S2 (higher than or equal to Vvfy2), from among memory cells to be programmed to the target state P2 are selected for the supplementary program operation. The memory cells thus selected are programmed by a supplementary program pulse to have a threshold voltage higher than the second supplementary verification voltage Vvfy_S2. At this time, a level of the second supplementary program voltage Vpgm_S2 is lower than or equal to that of a program voltage that is provided at a pass loop associated with the second program state P2 at a normal program operation, thereby making it possible to prevent threshold voltages of memory cells from excessively increasing due to the supplementary program voltage.
Memory cells to be programmed to the target states P3 through P7 are selected using supplementary verification voltages Vvfy_S3 through Vvfy_S7. Supplementary program voltages Vpgm_S3 through Vpgm_S7 corresponding to the target states P3 through P7 are applied to a word line connected with the selected word line, respectively. A supplementary verification voltage Vvfy_Sj (j indicating a number of a target state) may be set to be higher than or equal to a verification voltage Vvfyj that is provided at a normal program operation. Each supplementary program voltage may be set to be equal to or lower than a program pulse voltage of a program loop where a corresponding target state is program passed at a normal program operation.
An incremental step pulse programming manner is applied to the normal program operation. That is, program pulses Vpgm1 through VpgmN that stepwise increase are sequentially applied to a word line connected with selected memory cells. After each program pulse is applied, verification voltages Vvfy1, Vvfy2, Vvfy3, Vvfy4, Vvfy5, Vvfy6, and Vvfy7 corresponding to the target states P1, P2, P3, P4, P5, P6, and P7 are sequentially applied to the word line connected with the selected memory cells. The normal program operation is executed using a plurality of program loops.
The programming of memory cells, to be programmed to the target state P1, from among the selected memory cells is completed in a program loop corresponding to a loop count L3. The memory cells programmed to have the target state P1 are program inhibited from a program loop corresponding to a loop count L4. The programming of memory cells, to be programmed to the target state P2, from among the selected memory cells is completed in a program loop corresponding to a loop count L7. The memory cells programmed to have the target state P2 are program inhibited from a program loop corresponding to a loop count L8.
Although not shown in figures, memory cells to be programmed to each of the target states P3, P4, P5, P6, and P7 may be program passed in a program loop corresponding to any loop count as the number program loops increases. At the normal program operation, a page buffer 130 (refer to
Executed is the supplementary program operation following the normal program operation. During the supplementary program operation, first, memory cells that necessitate the supplementary program operation are selected. When the supplementary program operation is applied to the target states P1, P2, P3, P4, P5, P6, and P7, memory cells, having threshold voltages lower than a first supplementary verification voltage Vvfy_S1, from among memory cells to be programmed to the target state P1 are selected. A first supplementary program voltage Vpgm_S1 is applied to the selected memory cells. In some example embodiments, the first supplementary verification voltage Vvfy_S1 is equal to or higher than a first verification voltage Vvfy1, and the first supplementary program voltage Vpgm_S1 is equal to or lower than a program voltage Vpgm3. The program voltage Vpgm3 is a program voltage for a normal program operation that is used at a program loop where the programming of memory cells to the target state P1 is completed.
Memory cells, having threshold voltages lower than a second supplementary verification voltage Vvfy_S2, from among memory cells to be programmed to the target state P2 are selected. A second supplementary program voltage Vpgm_S2 is applied to the selected memory cells. In some example embodiments, the second supplementary verification voltage Vvfy_S2 is equal to or higher than a second verification voltage Vvfy2, and the second supplementary program voltage Vpgm_S2 is equal to or lower than a program voltage Vpgm7. The program voltage Vpgm7 is a program voltage for a normal program operation that is used at a program loop where the programming of memory cells to the target state P2 is completed.
Memory cells, having threshold voltages lower than a third supplementary verification voltage Vvfy_S3, from among memory cells to be programmed to the target state P3 are selected. A third supplementary program voltage Vpgm_S3 is applied to the selected memory cells. In some example embodiments, the third supplementary verification voltage Vvfy_S3 is equal to or higher than a third verification voltage Vvfy3. Although not shown in
The supplementary program operation may be executed with respect to the target states P4, P5, P6, and P7 in the same manner as described above.
Referring to
In
When the supplementary program operation is applied to memory cells the threshold voltages of which form threshold voltage distributions illustrated at the top (I) of
Memory cells, having threshold voltages lower than a seventh supplementary verification voltage Vvfy_S7 (higher than or equal to Vvfy7), from among memory cells to be programmed to the target state P7 are selected for the supplementary program operation. The memory cells thus selected are programmed by a supplementary program pulse to have a threshold voltage higher than the seventh supplementary verification voltage Vvfy_S7. At this time, a level of the seventh supplementary program voltage Vpgm_S7 is lower than or equal to that of a program voltage that is provided at a pass loop associated with the second program state P7 at a normal program operation.
Referring to
An incremental step pulse programming manner is applied to the normal program operation. That is, program pulses Vpgm1 through VpgmN that stepwise increase are sequentially applied to a word line connected with selected memory cells. After each program pulse is applied, verification voltages Vvfy1, Vvfy2, Vvfy3, Vvfy4, Vvfy5, Vvfy6, and Vvfy7 corresponding to the target states P1, P2, P3, P4, P5, P6, and P7 are sequentially applied to the word line connected with the selected memory cells. The normal program operation is executed using a plurality of program loops.
The programming of memory cells, to be programmed to the target state P1, from among the selected memory cells is completed in a program loop corresponding to a loop count L3. The memory cells programmed to have the target state P1 are program inhibited from a program loop corresponding to a loop count L4. The programming of memory cells, to be programmed to the target state P2, from among the selected memory cells is completed in a program loop corresponding to a loop count L7. The memory cells programmed to have the target state P2 are program inhibited from a program loop corresponding to a loop count L8.
Although not shown in figures, memory cells to be programmed to each of the target states P3, P4, P5, P6, and P7 may be program passed in a program loop corresponding to any loop count as the number program loops increases. At the normal program operation, a page buffer 130 (refer to
The supplementary program operation may be executed following the normal program operation. During the supplementary program operation, first, memory cells that necessitate the supplementary program operation are selected. When the supplementary program operation is applied to two target states P6 and P7 of the target states P1, P2, P3, P4, P5, P6, and P7, memory cells, having threshold voltages lower than a sixth supplementary verification voltage Vvfy_S6, from among memory cells to be programmed to the target state P1 are selected. A sixth supplementary program voltage Vpgm_S6 is applied to the selected memory cells. In some example embodiments, the sixth supplementary verification voltage Vvfy S6 is equal to or higher than a sixth verification voltage Vvfy6, and the sixth supplementary program voltage Vpgm_S6 is equal to or lower than a program voltage that is used at a program loop where the programming of memory cells to the target state P6 is completed.
Memory cells, having threshold voltages lower than a seventh supplementary verification voltage Vvfy_S7, from among memory cells to be programmed to the target state P7 are selected. A seventh supplementary program voltage Vpgm_S7 is applied to the selected memory cells. In some example embodiments, the seventh supplementary verification voltage Vvfy_S7 is equal to or higher than a seventh verification voltage Vvfy7, and the seventh supplementary program voltage Vpgm_S7 is a program voltage for a normal program operation that is used at a program loop where the programming of memory cells to the target state P7 is completed.
Referring to
In
When the supplementary program operation is applied to memory cells the threshold voltages of which form threshold voltage distributions illustrated at the top (I) of
Memory cells, having threshold voltages lower than a fifth supplementary verification voltage Vvfy_S5 (higher than or equal to Vvfy5), from among memory cells to be programmed to the target state P5 are selected for the supplementary program operation. The memory cells thus selected are programmed by a supplementary program pulse to have a threshold voltage higher than the fifth supplementary verification voltage Vvfy_S5. At this time, a level of the fifth supplementary program voltage Vpgm_S5 is lower than or equal to that of a program voltage that is provided at a pass loop associated with the target state P5 at a normal program operation.
A supplementary program method of programming memory cells to the target states P6 and P7 is substantially the same as that described with reference to
There are described supplementary program methods for programming memory cells to at least one of a plurality of target states. The supplementary program methods for one target state, two target states, or four target states is described with reference to accompanying drawings. However, the scope and spirit of the inventive concept may not be limited thereto. For example, it is understood that the supplementary program methods according to an embodiment of the inventive concept is applied to at least one any target state.
At a normal program operation, the programming of memory cells to a target state P1 is completed in a program loop corresponding to a loop count L3. On this occasion, control logic 150 selects a supplementary verification voltage (Vvfy1−α1) and a supplementary program voltage (Vpgm4−β1), based on the supplementary program table 155. In some embodiments, at the normal program operation, the programming of memory cells to a target state P2 is completed in a program loop corresponding to a loop count L5. On this occasion, the control logic 150 selects a supplementary verification voltage (Vvfy2−α2) and a supplementary program voltage (Vpgm5−β2), based on the supplementary program table 155.
The supplementary verification voltage Vvfy_S that is defined in the supplementary program table 155 is higher than a verification voltage that is used at the normal program operation. The supplementary program voltage Vpgm_S may be set to be lower than a program voltage that is used in a pass loop of a corresponding target state.
In operation 1610, the nonvolatile memory device 100 receives a program command and data from the external device. The received data is loaded on a page buffer 130 shown in
In operation 1620, the nonvolatile memory device 100 performs the normal program operation using an ISPP manner. In particular, the nonvolatile memory device 100 sets a loop count to an initialization value L1. Afterwards, a value of a loop count is gradually increased.
In operation 1630, the nonvolatile memory device 100 applies a program voltage Vpgmi (i indicating a loop count) to selected memory cells. Verification voltages Vvfy corresponding to plural target states are provided every program loop to program multi-level cells. Pass loop count information PLCI associated with a pass loop of each target state is sent to the control logic 150.
In operation 1640, the nonvolatile memory device 100 determines whether memory cells are programmed to have target states. For example, whether memory cells are programmed to have a selected target state P1 is determined based on a first verification voltage Vvfy1. Whether memory cells are programmed to have a selected target state P2 is determined based on a second verification voltage Vvfy2. Whether memory cells are programmed to have a selected target state P3 is determined based on a third verification voltage Vvfy3. Whether all target states are passed, that is, whether the normal program operation is passed may be determined in the above-described manner. As a consequence of determining that at least one of the target states is not passed, the methods proceed to operation 1650 to apply an increase program voltage. As a consequence of determining that all target states are passed, the methods proceed to operation 1660.
In step S250, the nonvolatile memory device 100 increases a value of a loop count and then returns to operation 1630 to execute a program operation using an increased program voltage.
In operation 1660, the nonvolatile memory device 100 stores all program data at internal latches of the page buffer 130 or at a state buffer unit 135 even after all program data is stored through the normal program operation. Pass loop count information indicating values of pass loops corresponding to target states is transferred from the page buffer 130 to the control logic 150.
In operation 1670, memory cells to which a supplementary program operation will be applied are selected. For example, the nonvolatile memory device 100 selects memory cells, corresponding to a specific target state, from among memory cells selected for programming. Memory cells, having threshold voltages lower than a supplementary verification voltage, from among the memory cells programmed to the specific target state are selected.
In operation 1680, the nonvolatile memory device 100 applies a supplementary program voltage to memory cells selected for the supplementary program operation. The nonvolatile memory device 100 provides a program voltage with respect to the selected/specific target state at the supplementary program operation. A level of the provided program voltage is lower than that of a final program pulse provided at a normal program operation. Even though memory cells are programmed using the supplementary program operation, an increase in threshold voltages of the memory cells may be set to be lower than the upper limit defined.
As described above, the nonvolatile memory device 100 performs a supplementary program operation after a normal program operation is completed. Thus, it is possible to minimize an increase in a time taken to perform a program operation and to prevent threshold voltage distributions of memory cells from deteriorating due to various factors. Some embodiments of the inventive concept are exemplified as a supplementary program operation is performed once with respect to each target state. However, the scope and spirit of the inventive concept may not be limited thereto. If needed, the number of supplementary program operations associated with each target state may increase.
In
The nonvolatile memory devices 1100 are provided with an external high voltage VPPx optionally. Each of the nonvolatile memory devices 1100 may be implemented with a nonvolatile memory device described with reference to
The SSD controller 1200 includes one or more processors 1210, a buffer memory 1220, an ECC block 1230, a host interface 1250, and a nonvolatile memory interface 1260.
The buffer memory 1220 temporarily stores data needed to drive the SSD controller 1200. In some example embodiments, the buffer memory 1220 may include a plurality of memory lines each of which stores data or a command. The memory lines may be mapped onto cache lines in various manners. The buffer memory 1220 may store page bitmap information and read count information. The page bitmap information and read count information may be read from the nonvolatile memory device 1100 and may be updated according to an internal operation. The updated page bitmap information and read count information may be stored at the nonvolatile memory device 1100 periodically or randomly.
The ECC block 1230 calculates an ECC value of data to be programmed at a write operation, corrects an error of read data according to an ECC value at a read operation, and corrects an error of data restored from the nonvolatile memory device 1100 at a data restoration operation. Although not shown in
The host interface 1250 provides an interface with an external device. The host interface 1250 may be a NAND flash interface. Besides, the host interface 1250 may be implemented with various interfaces or with a plurality of interfaces. The nonvolatile memory interface 1260 provides an interface with the nonvolatile memory devices 1100.
The SSD 1000 according to some embodiments of the inventive concept includes the nonvolatile memory devices 1100 to which a supplementary program operation is applied, thereby making integrity of data high.
The inventive concept is applicable to an eMMC (e.g., an embedded multimedia card, moviNAND, iNAND, etc.).
The controller 2200 includes one or more controller cores 2210, a host interface 2250, and a NAND interface 2260. The controller core 2210 may control an overall operation of the eMMC 2000. The host interface 2250 performs an interface between the controller 2200 and a host. The NAND interface 2260 provides an interface between the NAND flash memory device 2100 and the controller 2200. In some example embodiments, the host interface 2250 may be a parallel interface (e.g., MMC interface). In some example embodiments, the host interface 2250 of the eMMC 2000 may be a serial interface (e.g., UHS-II, UFS interface, etc.). In some example embodiments, the host interface 2250 may be a NAND interface.
The eMMC 2000 receives power supply voltages Vcc and Vccq from the host. Herein, the power supply voltage Vcc (e.g., about 3.3 V) may be supplied to the NAND flash memory device 2100 and the NAND interface 2260, and the power supply voltage Vccq (e.g., about 1.8 V/3.3 V) may be supplied to the controller 2200. In some example embodiments, the eMMC 2000 may be optionally supplied with an external high voltage.
The eMMC 2000 according to some embodiments of the inventive concept includes the NAND flash memory device 2100 that minimizes a decrease in performance and provides high integrity of data, thereby obtaining high performance and integrity of data.
The inventive concept is applicable to Universal Flash Storage UFS.
The host 3100 includes a bridge that enables the removable UFS card 3300 to communicate using the protocol different from the UFS protocol. The UFS host 3100 and the removable UFS card 3300 may communicate through various card protocols (e.g., UFDs, MMC, SD (secure digital), mini SD, Micro SD, etc.).
The network adaptor 4100 provides an interface between the computing system 4000 and external networks 5000. The CPU 4200 controls an overall operation for driving an operating system and an application program which are resident on the RAM 4400. The data storage device 4300 may store data needed for the computing system 4000. For example, the data storage device 4300 may store an operating system for driving the computing system 3000, an application program, various program modules, program data, user data, and so on.
The RAM 4400 may be used as a working memory of the computing system 4000. Upon booting, the operating system, the application program, the various program modules, and program data needed to drive programs and various program modules read out from the data storage device 4300 may be loaded onto the RAM 4400. The ROM 4500 may store a basic input/output system (BIOS) which is activated before the operating system is driven upon booting. Information exchange between the computing system 4000 and a user may be made via the user interface 4600.
In some example embodiments, the computing system 4000 may further include a battery, a modem, and so on. Although not shown, also, the computing system 4000 may further include an application chipset, a camera image processor (CIS), a mobile DRAM, and so on.
The mass storage device 4300 may be implemented with a solid state drive, a multimedia card (MMC), a secure digital (SD) card, a micro SD card, a memory stick, an ID card, a PCMCIA card, a chip card, an USB card, a smart card, a compact flash (CF) card, and so on. The mass storage device 4300 may include a nonvolatile memory device 100 shown in
A semiconductor device according to the inventive concept may be packaged according to any of a variety of different packaging technologies. Examples of such packaging technologies may include the following: PoP (Package on Package), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), and/or Wafer-Level Processed Stack Package (WSP).
In some embodiments of the inventive concept, a nonvolatile memory device is provided which minimizes a program time taken to better threshold voltage distributions and minimizes the drooping and spreading of threshold voltage distributions of memory cells. Thus, it is possible to implement a nonvolatile memory device that has high reliability without lowering performance.
While the inventive concept has been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above embodiments are not limiting, but illustrative.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2014-0143583 | Oct 2014 | KR | national |
