Nonvolatile semiconductor memory device and programming or erasing method therefor

Abstract

In a nonvolatile memory cell having a trap layer, by executing first charge injection with a given wait time being secured and second charge injection after the first charge injection in a programming or erasing sequence, surrounding charge that may deteriorate the data retention characteristic is reduced utilizing an initial variation (charge loss phenomenon caused by binding of injected charge with the surrounding charge in an extremely short time) occurring immediately after programming. Thereafter, the charge loss in the initial variation is compensated, so that the subsequent data retention characteristic is improved. The second charge injection is executed only when a predetermined determination level has been reached.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view showing a programming or erasing method for a nonvolatile semiconductor memory device in Embodiment 1.

FIGS. 2A through 2H are views showing the behavior of trapped charge in the nonvolatile semiconductor memory device in Embodiment 1.

FIGS. 3A and 3B are views showing changes in the memory cell threshold voltage of the nonvolatile semiconductor memory device in Embodiment 1.

FIG. 4 is a view of memory cell threshold voltage distributions of multi-valued memory, used for description of Embodiment 1.

FIG. 5 is a view showing a circuit configuration of the nonvolatile semiconductor memory device in Embodiment 1.

FIG. 6 is a view showing a programming or erasing method for a nonvolatile semiconductor memory device in Embodiment 2.

FIGS. 7A through 7F are views showing the behavior of trapped charge in the nonvolatile semiconductor memory device in Embodiment 2.

FIG. 8 is a view showing a programming or erasing method for a nonvolatile semiconductor memory device in Embodiment 3.

FIG. 9 is a view showing a programming or erasing method for a nonvolatile semiconductor memory device in Embodiment 4.

FIG. 10 is a view showing a programming or erasing method for a nonvolatile semiconductor memory device in Embodiment 5.

FIG. 11 is a view showing an alternative method in Embodiment 5.

FIG. 12 is a view showing another alternative method in Embodiment 5.

FIG. 13 is a view showing a circuit configuration of the nonvolatile semiconductor memory device in Embodiment 5.

FIG. 14 is a view showing a programming or erasing method for a nonvolatile semiconductor memory device in Embodiment 6.

FIG. 15 is a view showing a programming or erasing method for a nonvolatile semiconductor memory device in Embodiment 7.

FIG. 16 is a view showing a circuit configuration of the nonvolatile semiconductor memory device in Embodiment 7.

FIG. 17 is a view showing a circuit configuration of electronic equipment using the nonvolatile semiconductor memory device in Embodiment 7.

FIG. 18 is a view showing a programming or erasing method for a nonvolatile semiconductor memory device in Embodiment 8.

FIG. 19 is a view of memory cell threshold voltage distributions of multi-valued memory, used for description of Embodiment 9.

FIG. 20 is a view showing a programming or erasing method for a nonvolatile semiconductor memory device in Embodiment 9.

FIG. 21 is a view showing an alternative method in Embodiment 9.

FIG. 22 is a view showing a programming or erasing method for a nonvolatile semiconductor memory device in Embodiment 10.

FIG. 23 is a view showing a memory cell structure of a conventional nonvolatile semiconductor memory device.

FIGS. 24A through 24E are views showing the behavior of trapped charge in the conventional nonvolatile semiconductor memory device.

Claims

1. A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step, wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage, andin the second charge injection step, charge injection is executed up to a given threshold voltage only when a given determination level has been reached.

2. The method of claim 1, wherein the second charge injection step is repeated a given number of times.

3. A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in pre-erase programming, a first charge injection step and a second charge injection step executed after the first charge injection step, wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage, andin the second charge injection step, charge injection is executed up to a given threshold voltage.

4. The method of claim 3, wherein, in data programming, the first charge injection and the second charge injection are executed under conditions changed from conditions for the pre-erase programming.

5. The method of claim 4, wherein only the first charge injection step is executed in the pre-erase programming.

6. The method of claim 3, wherein, in the first charge injection step in the pre-erase programming, the charge injection is executed up to a programming level above a level adopted in the data programming.

7. A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step, wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,in the second charge injection step, charge injection is executed up to a given threshold voltage, andconditions of the first charge injection and the second charge injection are changed with a production unit.

8. A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step, wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,in the second charge injection step, charge injection is executed up to a given threshold voltage, andconditions of the first charge injection and the second charge injection are changed with a programming or erasing unit.

9. A programming or erasing method For a nonvolatile semiconductor memory vice having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step, wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,in the second charge injection step, charge injection is executed up to a given threshold voltage, andconditions of the first charge injection and the second charge injection are set for each production unit in a testing process.

10. A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step, wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,in the second charge injection step, charge injection is executed up to a given threshold voltage, andconditions of the first charge injection and the second charge injection are set for each programming or erasing unit in a testing process.

11. A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,in the second charge injection step, charge injection is executed up to a given threshold voltage, andconditions of the first charge injection and the second charge injection are set for each programming or erasing unit according to a characteristic in preceding programming or erasing.

12. A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step, wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,in the second charge injection step, charge injection is executed up to a given threshold voltage, andthe wait time changes with the length of a left-to-stand time from last data programming until the programming or erasing.

13. A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step, wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,in the second charge injection step, charge injection is executed up to a given threshold voltage, andonly the first charge injection step may be executed depending on the length of a left-to-stand time from last data programming until the programming or erasing.

14. A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step, wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,in the second charge injection step, charge injection is executed up to a given threshold voltage, andcharge injection conditions in the second charge injection step changes with the length of a left-to-stand time from last data programming until the programming or erasing.

15. A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step, wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,in the second charge injection step, charge injection is executed up to a given threshold voltage, andwait time changes with the degree of the ambient temperature during data programming.

16. A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step, wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,in the second charge injection step, charge injection is executed up to a given threshold voltage, andonly the first charge injection step may be executed depending on the degree of the ambient temperature during data programming.

17. A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step, wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,in the second charge injection step, charge injection is executed up to a given threshold voltage, andcharge injection conditions in the second charge injection step changes with the degree of the ambient temperature in data programming.

18. A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step, wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,in the second charge injection step, charge injection is executed up to a given threshold voltage, andthe wait time changes with the number of times of data programming or erasing.

19. A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step, wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,in the second charge injection step, charge injection is executed up to a given threshold voltage, andonly the first charge injection step may be executed depending on the number of times of programming or erasing.

20. A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step, wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,in the second charge injection step, charge injection is executed up to a given threshold voltage, andcharge injection conditions in the second charge injection step changes with the number of times of data programming or erasing.

21. A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step, wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,in the second charge injection step, charge injection is executed up to a given threshold voltage, andthe wait time changes with a data value immediately before the programming or erasing.

22. A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step, wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,in the second charge injection step, charge injection is executed up to a given threshold voltage, andonly the first charge injection step may be executed depending on a data value immediately before the programming or erasing.

23. A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step, wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,in the second charge injection step, charge injection is executed up to a given threshold voltage, andcharge injection conditions in the second charge injection step changes with a data value immediately before the programming or erasing.

24. A programming or erasing method for a nonvolatile semiconductor memory device having a top layer and three or more memory cell threshold voltage values, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step, wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,in the second charge injection step, charge injection is executed up to a given threshold voltage, andcharge injection is first executed for memory cells for which a low threshold voltage is set, then charge injection is executed for memory cells for which a higher threshold voltage is set while a wait time after the first charge injection for the memory cells for which a low threshold voltage is set is secured, and thereafter the second charge injection is executed for the memory cells for which a low threshold voltage is set.

25. A programming or erasing method for a nonvolatile semiconductor memory device having a top layer and three or more memory cell threshold voltage values, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step, wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,in the second charge injection step, charge injection is executed up to a given threshold voltage, andcharge injection is first executed for memory cells for which a high threshold voltage is set, then charge injection is executed for memory cells for which a lower threshold voltage is set while a wait time after the first charge injection for the memory cells for which a high threshold voltage is set is secured, and thereafter the second charge injection is executed for the memory cells for which a high threshold voltage is set.

26. A programming or erasing method for a nonvolatile semiconductor memory device having a top layer and three or more memory cell threshold voltage values, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step, wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,in the second charge injection step, charge injection is executed up to a given threshold voltage, andwhether or not the first charge injection and the second charge injection should be executed in data programming, or both the first charge injection and the second charge injection or only the first charge injection should be executed in pre-erase programming is determined according to the memory cell threshold voltage level.

27. The method of claim 26, wherein in programming or erasing, in particular, the first charge injection is executed in the pre-erase programming for memory cells for which a low threshold voltage is set before the programming or erasing, and in the data programming after erasing, first, the first charge injection and the second charge injection are executed for memory cells for which a high threshold voltage is set, the wait time after the first charge injection is secured using a programming time for memory cells for which a lower threshold voltage is set, and thereafter the second charge injection is executed for the memory cells for which a high threshold voltage is set.

28. A nonvolatile semiconductor memory device comprising: a nonvolatile memory array having a trap layer;a programming or erasing sequence control circuit for controlling a given wait time after execution of charge injection up to a given memory cell threshold voltage in first charge injection and then controlling second charge injection after the given wait time so that the first charge injection and the second charge injection are executed in programming or erasing; anda time management area, provided for each erase unit area of the nonvolatile memory array, for storing a time at which the first charge injection was executed.

29. A nonvolatile semiconductor memory device comprising: a nonvolatile memory array having a trap layer;a programming or erasing sequence control circuit for controlling a given wait time after execution of charge injection up to a given memory cell threshold voltage in first charge injection and then controlling second charge injection after the given wait time so that the first charge injection and the second charge injection are executed in programming or erasing; anda status management area, provided for each erase unit area of the nonvolatile memory array, for storing a status of being after the first charge injection or after the second charge injection.

30. Electronic equipment comprising: a nonvolatile semiconductor memory device having a trap layer, comprising a programming or erasing sequence control circuit for controlling a given wait time after execution of charge injection up to a given memory cell threshold voltage in first charge injection and then controlling second charge injection after the given wait time so that the first charge injection and the second charge injection are executed in programming or erasing; anda programming or erasing operation selection circuit capable of switching between the first charge injection and the second charge injection after termination of the control of the given wait time in the first charge injection.