V. Kynett et al., "An In-System Reprogrammable 32K.times.8 CMOS Flash Memory", IEEE Journal of Solid State Circuits, vol. 23, Non. 5, pp. 1157-1163, Oct. 1988. |
S. Haddad et al., "Degradations Due to Hole Trapping in Flash Memory Cells", IEEE Eletron Device Letters, vol. 10, No. 3, pp. 117-119, Mar. 1989. |
S. Haddad et al., "An Investigation of Erase-Mode Dependent Hole Trapping in Flash EEPROM Memory Cell", IEEE Electron Device Letters, vol. 11, No. 11, pp. 514-516, Nov. 1990. |
Electronics Magazine, Nov. 1990, pp. 44-53, "Look Out EPROMs, Here Comes Flash", by Samuel Weber. |
Gill et al., "A Novel Sublithographic Tunnel Diode Based 5V-Only Flash Memory", IEEE-IEDM, Dec. 1990, pp. 119-122. |
Gill et al., "Process Technology for 5-Volt Only 4 MB Flash EEPROM with 8.6 UM2 Cell", IEEE Symposium on VLSI Technology, Jun. 1990, pp. 125-126. |
Gill et al., "A Five-Volt Contactless Array 256K Bit Flash EEPROM Technology," IEEE Int. Electron Devices Meeting, Dec. 1988, pp. 428-431. |
Chang et al., "Corner-Field Induced Drain Leakage in Thin Oxide MOSFETs", IEEE Intl. Electron Devices Meeting, Dec. 1987, pp. 714-717. |
Chang et al., Drain-Avalanche and Whole-Trapping Induced Gate Leakage in Thin-Oxide MOS Devices, IEEE Electron Devices Letters, vol. 9, No. 11, Nov. 1988, pp. 588-590. |
S. Mukherjee et al., "A Single Transistor EEPROM Cell and its Implementation in a 512K CMOS EEPROM", IEEE Intl. Electron Devices Meeting, 1985, pp. 616-619. |
G. Samachisa et al., "A 128K Flash EEPROM Using Double-Polysilicon Technology", IEEE Journal of Solid State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 676-683. |
Cernea et al., "A 1Mb Flash EEPROM", IEEE Intl. Solid State Circuits Conference, Feb. 1989, pp. 138-139, 316. |
S. Tam et al., "A High Density CMOS 1-T Electrically Erasable Non-Volatile (Flash) Memory Technology", IEEE Electron Devices Society, 1988 Symposium of VLSI Technology Digest of Technical Papers, May 1988, pp. 31-32. |
S. D'Arrigo et al., "A 5V-Only 256K Bit CMOS Flash EEPROM", IEEE Solid State Circuits Conference, Feb. 1989, pp. 132-133, 313. |
V. Kynett et al., "A 90ns 100K Erase/Program Cycle Megabit Flash Memory", 1989 IEEE Intl. Solid State Circuits Conference, Feb. 1989, pp. 140-141, 317. |
K. Komori et al., "A High Performance Memory Cell Technology For Mega Bit EPROMs", pp. 627-630, IEEE-IEDM 1985. |
K. Seki et al., "An 80-n5 1-Mb Flash Memory Unit With On-Chip Erase/Erase-Verify Controller", IEEE Journal SSC, vol. 25, No. 5, Oct. 1990, pp. 1147-1152. |
Johnson et al., "A 16Kb Electrically Erasable Non-Volatile Memory", IEEE Intl. Solid-State Circuits Conf., pp. 152-153, 271, Feb. 1980. |
Samachisa et al., "A 128K Flash EEPROM Using Double Polysilicon Technology", IEEE Intl. Solid-State Circuits Conf., pp. 76-77, 345, Feb. 1987. |
Electronic Technology, pp. 122-127, and English translation, Jun. 1988. |
Kume et al., "A Flash Erase EEPROM Cell With An Asymmetric Source and Drain Structure", pp. 560-563, IEEE-IEDM 1987. |