Claims
- 1. A semiconductor integrated circuit device comprising:
- a plurality of nonvolatile memory cells each having a programmed or erased state, the programmed state thereof being changed into the erased state thereof by an application of an erase voltage thereto;
- nodes to which first address signals are supplied in a read operation mode for reading out data in nonvolatile memory cells;
- an erase voltage providing circuit which is operated in an erase operation mode to provide the erase voltage to nonvolatile memory cells to be erased;
- an address providing circuit which is operated in the erase operation mode to generate second address signals;
- a detecting circuit which detects whether each of the nonvolatile memory cells designated by the second address signals is placed in the erased state;
- a control circuit which operates the erase voltage providing circuit and the detecting circuit thereafter, if the detecting circuit detects that a nonvolatile memory cell that is out of the erased state is still included in the nonvolatile memory cells designated by the second address signals, wherein the control circuit controls the address providing circuit to provide new second address signals different from the previous ones and to operate the detecting circuit, if the detecting circuit detects that each nonvolatile memory cell designated by the second address signals is in the erased state; and
- an output circuit which outputs a condition of the nonvolatile memory cells in the erase operation mode.
- 2. A semiconductor integrated circuit device according to claim 1,
- wherein the plurality of nonvolatile memory cells are coupled to a plurality of word lines, wherein a word line from the plurality of word lines is indicated according to the first address signals and the indicated word line is supplied with a read voltage in the read operation mode, and
- wherein the detecting circuit includes a verify voltage providing circuit which generates a verify voltage being different from the read voltage and which provides the verify voltage to a word line designated by the second address signals.
- 3. A semiconductor integrated circuit device according to claim 2,
- wherein a word line among the plurality of word lines is indicated by decoding ones of the first address signals in the read operation mode, and by decoding the second address signals instead of the ones of the first address signals in the erase operation mode.
- 4. A semiconductor integrated circuit device according to claim 3, further comprising:
- a node which is used to output the stored data in the read operation mode and is used to output the condition.
- 5. A semiconductor integrated circuit device according to claim 4,
- wherein the condition includes failure in the erase operation mode.
- 6. A semiconductor integrated circuit device according to claim 1, further comprising:
- a node which is used to output the stored data in the read operation mode and is used to output the condition.
- 7. A semiconductor integrated circuit device according to claim 6,
- wherein the condition includes failure in the erase operation mode.
- 8. A semiconductor integrated circuit device according to claim 1,
- wherein the condition includes failure in the erase operation mode.
Priority Claims (5)
Number |
Date |
Country |
Kind |
1-27271 |
Jun 1989 |
JPX |
|
1-317477 |
Aug 1989 |
JPX |
|
1-210262 |
Aug 1989 |
JPX |
|
1-243603 |
Sep 1989 |
JPX |
|
2-13614 |
Jan 1990 |
JPX |
|
Parent Case Info
This application is a continuation of application Ser. No. 08/456,797, filed Jun. 1, 1995, now U.S. Pat. No. 5,781,476; which is a continuation of application Ser. No. 08/249,899, filed May 26, 1994, now U.S. Pat. No. 5,844,842, the latter, in turn, being (1) a continuation-in-part application of application Ser. No. 08/144,500, now abandoned, filed Nov. 2, 1993, which is a continuation application of application Ser. No. 07/474,994, filed Feb. 5, 1990, now abandoned, and being (2) a continuation-in-part application of application Ser. No. 07/888,447, filed May 28, 1992, now abandoned, which is a continuation application of application Ser. No. 07/567,391, filed Aug. 14, 1990, now abandoned; and the contents of all of which are incorporated herein by reference in their entirety.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
5602987 |
Harari et al. |
Feb 1997 |
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Continuations (4)
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Number |
Date |
Country |
Parent |
456797 |
Jun 1995 |
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Parent |
249899 |
May 1994 |
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Parent |
474994 |
Feb 1990 |
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Parent |
567391 |
Aug 1990 |
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