Patent Application
20060214009
The present application claims priority from Japanese patent application No. 2005-091034 filed on Mar. 28, 2005, the content of which is hereby incorporated by reference into this application.
The present invention relates to a memory card and a nonvolatile storage apparatus such as a multiple function card which is a memory card having a microcomputer for IC card formed thereon. It relates to technology effectively applicable to nonvolatile memory cards such as a memory card operated at low voltage, for example, using an operating supply voltage of 1.8 V or a dual voltage memory card compatible with operating supply voltages of, for example, 1.8 V and 3.3 V.
A nonvolatile memory card which can be removably inserted in a card slot of a host device is, when it is inserted in the card slot, supplied with operating power supply from a host system. The nonvolatile memory card has a card controller and a flash memory. The card controller has, for example, a microcomputer as a data processing section to execute instructions. When the card controller is powered on, the microcomputer is reset by a power-on reset. When, for example, the operating power supply that has been turned on reaches or exceeds a minimum operating voltage, a reset terminal of the microcomputer is set at a low level and, as a result, internal initialization of the microcomputer starts. When an initialization command is given by the host system, the reset terminal of the microcomputer is set at a high level and, as a result, the microcomputer starts reset exception processing. As part of the reset exception processing, the microcomputer accesses the flash memory and reads information such as a memory card ID. The flash memory and the card controller differ in manufacturing process. This is because the flash memory requires high voltage when rewriting information stored therein. Hence, they also differ in minimum voltage at which they are operational (minimum operating voltage). Generally, the card controller is lower in minimum operating voltage than the flash memory. There are, therefore, cases in which, when the supply voltage reaches the minimum operating voltage of the card controller and the microcomputer starts power-on reset processing, the minimum operating voltage of the flash memory has not been reached. In such a state, reading, by the microcomputer, of ID information from the flash memory may result in a read error or a data error.
Technology disclosed in the patent document 1 includes an arrangement for the following procedure: unique data is written on a flash memory beforehand; when the unique data is correctly read out at a power-on reset, normal processing is performed; if the unique data is not correctly read out, the microcomputer is put in a sleep state; subsequently, with the microcomputer in a sleep state, when an initialization command is received again, the inside of the microcomputer is initialized and reset exception processing is performed again.
Technology in which a watchdog timer is used to detect running out of control of a program in a microcomputer and then cause resetting operation to be performed is described in the patent document 2.
[Patent document 1] Japanese Unexamined Patent Publication No. 2003-85508
[Patent document 2] Japanese Unexamined Patent Publication No. Sho 60 (1985)-27038
The measure disclosed in the patent document 2 is aimed at, when program execution in a microcomputer in normal operating condition gets out of control, detecting and recovering from such an out-of-control state. The measure disclosed in the patent document 1 is based on the assumption that a microcomputer is operated at a normal operating voltage. Therefore, when the microcomputer is not supplied with a normal operating voltage and, as a result, a reset signal is set at a low level causing the microcomputer to be instructed to perform reset exception processing, the microcomputer itself gets out of control. In such a state, the microcomputer cannot even be put in a sleep state. Moreover, a flag to indicate a state in which, in response to an initialization command, the microcomputer has been instructed to perform power-on reset processing is provided in a card controller. This is to prevent undesired reset exception processing from being performed if an initialization command is inputted while a memory card is operating normally. In such an arrangement, however, unless the flag is reset, even responding to an initialization command issued by a host device is impossible. When the microcomputer gets out of control, no matter how many times the host device issues the initialization command to the memory card, the memory card being unable to return a response to the host device remains in a busy state. In such a state, the memory card will have to be re-inserted in the card slot before it is operational again.
The above state occurs particularly when a low operating supply voltage is used. Take a case where the operating supply voltage is 3.3 V nominal, for example. The minimum operating voltage of the flash memory is 2.5 V and that of the microcomputer is 2.0 V, so that the difference between the two minimum operating voltages is relatively large. Assume that, in this case, the minimum operating voltage of the memory card is 2.5 V. Even if it is taken into account that the accuracy (2.50±0.10 V) of the voltage detection circuit has been affected by factors in the manufacturing process, there is practically no possibility of the operating supply voltage being lower than the minimum operating voltage of the microcomputer when reset exception processing is performed. If the operating supply voltage is 1.8 V nominal, the minimum operating voltage of the flash memory is 1.6 V and that of the microcomputer is 1.5 V, so that the difference between the two minimum operating voltages is extremely small. In such a case, the minimum operating voltage of the memory card is usually 1.5 V. If, in such a case, the accuracy (1.50±0.10 V) of the voltage detection circuit has been largely changed by being affected by factors in the manufacturing process, the microcomputer may be instructed to perform reset exception processing while the operating supply voltage is lower than the minimum operating voltage of the microcomputer.
The above possibility also exists when using, with a low-potential power supply of 1.8 V, a dual voltage memory card compatible with both of the operating supply voltages of 3.3 V and 1.8 V.
An object of the present invention is to provide a nonvolatile storage apparatus and a semiconductor device which are not deadlocked even if their data processing section gets out of control during a power-on reset processing.
The above and other objects, and novel features of the present invention will become apparent from the description in the present specification and the attached drawings. Representative ones of the inventions disclosed in the present application are briefly described in the following.
1
A nonvolatile storage apparatus according to the present invention includes a first semiconductor device (3) having a data processing section (8) capable of executing instructions and an external interface section (7), and a second semiconductor device (4) controlled by the first semiconductor device. The external interface section, upon detecting that an operating supply voltage supplied from outside the nonvolatile storage apparatus has reached or exceeded a prescribed voltage, responds to an initialization command supplied from outside the nonvolatile storage apparatus and makes the data processing section start reset exception processing. After the reset exception processing is completed, the external interface section does not respond to the initialization command. When a prescribed state is reached during the reset exception processing, the external interface section again responds to the initialization command and makes the data processing section start the reset exception processing. The prescribed state is a state in which, during the reset exception processing, the data processing section has become or is anticipated to become out of control.
With the above arrangement made, even if the data processing section gets out of control when starting the reset exception processing in response to the initialization command, the external interface section can again respond to the initialization command to have the reset exception processing started. The data processing section is not deadlocked even if it gets out of control during a power-on reset processing. Even if the initialization command is issued after the reset exception processing is normally terminated, undesired resetting of the nonvolatile storage apparatus is prevented.
In an embodiment of the present invention, the external interface section has a timer circuit (21). The timer circuit starts counting in synchronization with starting of the reset exception processing and detects an elapse of a time-out period longer than a time required to complete the reset exception processing. When an elapse of the time-out period is detected by the timer circuit, the external interface section again responds to the initialization command and causes the reset exception processing to be started. With this arrangement made, when the data processing section gets out of control, the timer circuit is timed out, so that the external interface section can again responds to the initialization command to have the reset exception processing started. Stopping the timer circuit operation when the reset exception processing is completed can prevent undesired giving of a response to the initialization command if issued after completion of the reset exception processing.
In another embodiment of the present invention, the nonvolatile storage apparatus has a specified circuit (24) which includes programmed information for specifying a time-out period of the timer circuit. The specified circuit may be composed of, for example, a fuse program circuit or an aluminum master slice. The timer circuit may be composed of a counter circuit including flip-flop circuits connected in series.
In still another embodiment of the present invention, the data processing section has a data processor (10), a ROM (32), and a decision circuit (31). The ROM holds a program for the reset exception processing. The decision circuit can detect, at least within a time required to complete the reset exception processing, disagreement between information read out from a prescribed address of the ROM and an anticipated value. When the disagreement is detected, the external interface section again responds to the initialization command and causes the reset exception processing to be started. With this arrangement made, when the operating supply voltage for the data processing section has not reached the minimum operation guaranteed voltage of the data processing section at instructing of execution of the reset exception processing, a read access to the ROM results in a data error causing the disagreement to be detected. Hence, the external interface section can again respond to the initialization command to have the reset exception processing to be started. The prescribed address of the ROM may be, for example, the starting address of the program for the reset exception processing.
In a still another embodiment of the present example, time-up control by the timer circuit and decision control for data read from the ROM may both be used.
In a still another embodiment of the present invention, the external interface section further includes a first flag and a second flag. The first flag is changed from a first state to a second state when the initialization command supplied from outside the nonvolatile storage apparatus is received for the first time after the operating supply voltage supplied from outside the nonvolatile storage apparatus has reached or exceeded a prescribed voltage. The second flag is changed from a first state to a second state when the prescribed state is reached during the reset exception processing. It is changed from the second state to the first state when the reset exception processing is subsequently completed. When both the first flag and the second flag are in the first state or when both the first flag and the second flag are in the second state, the external interface section responds to the initialization command and makes the data processing section start the reset exception processing. When the first flag is in the second state and the second flag is in the first state, the external interface section does not allow the data processing section to start the reset exception processing even if the initialization command is given.
In a still another embodiment of the present invention, the second semiconductor device is a flash memory and the first semiconductor device is a memory card controller which performs access control and external interface control for the flash memory. Furthermore, the nonvolatile storage apparatus includes a microcomputer for IC card connected to the memory card controller.
2
The nonvolatile storage apparatus seen from another standpoint includes a first semiconductor device and a second semiconductor device controlled by the first semiconductor device. The first semiconductor device, upon detecting that an operating supply voltage supplied from outside has reached or exceeded a prescribed voltage, responds to an initialization command supplied from outside and starts reset exception processing. After the reset exception processing is completed, the first semiconductor device does not respond to the initialization command. When a prescribed amount of time has elapsed after the reset exception processing was started, the first semiconductor device again responds to the initialization command and starts the reset exception processing.
The nonvolatile storage apparatus seen from still another standpoint includes a first semiconductor device and a second semiconductor device controlled by the first semiconductor device. The first semiconductor device, upon detecting that an operating supply voltage supplied from outside has reached or exceeded a prescribed voltage, responds to an initialization command supplied from outside and starts reset exception processing. After the reset exception processing is completed, the first semiconductor device does not respond to the initialization command. When, before the reset exception processing is completed, a read access error is detected in making a read access to a memory storing a program for the reset exception processing, the first semiconductor device again responds to the initialization command and starts the reset exception processing.
In an embodiment of the present embodiment, the second semiconductor device is a flash memory, and the first semiconductor device is a memory card controller which performs access control and external interface control for the flash memory.
The nonvolatile storage apparatus seen from still another standpoint includes a first semiconductor device having a data processing section and a second semiconductor device controlled by the first semiconductor device. The first semiconductor device, upon detecting that an operating supply voltage supplied from outside has reached or exceeded a prescribed voltage, responds to an initialization command supplied from outside and starts reset exception processing by the data processing section. After the reset exception processing is completed, the first semiconductor device does not respond to the initialization command. When a state in which the data processing section has become or is anticipated to become out of control is reached during the reset exception processing, the first semiconductor device again responds to the initialization command and starts the reset exception processing by the data processing section.
3
A semiconductor device according to the present invention includes a data processing section capable of executing instructions and an external interface section. It is formed on a semiconductor substrate. It, upon detecting that an operating supply voltage supplied from outside has reached or exceeded a prescribed voltage, responds to an initialization command supplied from outside and starts reset exception processing by the data processing section. After the reset exception processing is completed, the semiconductor device does not respond to the initialization command. When a prescribed amount of time has elapsed after the reset exception processing was started, the semiconductor device again responds to the initialization command and starts the reset exception processing by the data processing section.
Another semiconductor device according to the present invention includes a data processing section capable of executing instructions and an external interface section. It is formed on a semiconductor substrate. It, upon detecting that an operating supply voltage supplied from outside has reached or exceeded a prescribed voltage, responds to an initialization command supplied from outside and starts reset exception processing by the data processing section. After the reset exception processing is completed, the semiconductor device does not respond to the initialization command. When a state in which the data processing section has become or is anticipated to become out of control is reached during the reset exception processing, the semiconductor device again responds to the initialization command and starts the reset exception processing by the data processing section.
Effects of representative ones of the inventions disclosed in the present application are briefly described in the following.
A nonvolatile storage apparatus such as a memory card or a semiconductor device such as a memory card controller can be prevented from being deadlocked even if its data processing section gets out of control during a power-on reset.
The host device 2 is, for example, a mobile phone, personal digital assistance (PDA), personal computer, audio playback (and recording) device, still camera, video camera, automatic teller machine, street-corner terminal, or settlement terminal.
The memory card 1 includes an internal memory card controller (MCCNT) 3 and an internal flash memory (FLASH) 4, each being composed in a discrete semiconductor integrated circuit chip, formed on a memory card substrate. Plural external connection terminals of the memory card 1 are exposed on the memory card substrate. The flash memory 4 is a memory chip using a semiconductor memory as a memory medium. Data can be read and written from and to the flash memory 4 using flash memory commands. The configuration of the flash memory 4 will not be described in detail here, but it includes, for example, many nonvolatile memory cells having floating gates as charge storage areas and nonvolatile memory cells having insulating charge storage areas made of silicon nitride. The threshold voltage of a nonvolatile memory cell increases when electrons are selectively injected into its charge storage area, and the threshold voltage decreases when electrons are discharged from the charge storage area. Increasing the threshold voltage is referred to, for example, as writing, and decreasing the threshold voltage is referred to, for example, as erasing. Writing and erasing requires high voltage. The flash memory 4, for example, has a charge pump type booster circuit. It uses the booster circuit to boosts a supply voltage so as to generate the high voltage needed to perform writing or erasing.
Though not shown in the figure, the MMC has seven external terminals including a power supply terminal, a clock input terminal, a command input/output terminal, a data input/output terminal, a ground terminal, and a chip selection terminal. The MMC specification specifies two operation modes, that is, MMC mode and SPI mode, for MMC1. The external terminals are used differently between the two operation modes.
The memory card controller 3 has an external interface section 7 interfaced to the host device 2, a data processing section 8, a buffer memory section 9, and a flash memory interface circuit (FIF) 15 connected to the flash memory 4, all of which are connected to a bus 6.
The data processing section 8 has a microprocessor (MPU) 10, a ROM 11, a RAM 12, and a processor interface (MIF) 13. The MPU 10 has an instruction control section which controls instruction execution sequences and decodes instructions and an instruction execution section which executes decoded instructions by accessing operands and performing operations according to the instructions. The ROM 11 holds instructions to be executed by the MPU 10. The RAM 12 is used as a work area for the MPU 10. The MIF 13 connects the bus 6 to the MPU 10. When accessing the FLASH 4, the MPU 10 issues an access command to the FLASH 4 via the FIF 15.
The buffer memory section 9 has a buffer interface circuit (BIF) 16 and a buffer memory (BMRY) 17. The MPU 10 temporarily stores write data transferred from the HOST 2 in the BMRY 17. When issuing a write command to the FLASH 4, the MPU 10 supplies the write data stored in the BMRY 17 to the FLASH 4. When supplying data stored in the FLASH 4 to the HOST 2, the MPU 10 temporarily stores the data read out from the FLASH 4 in the BMRY 17. The MPU 10 sequentially transfers the data stored in the BMRY 17 to the HOST 2.
The external interface section 7 has a host interface circuit (HIF) 14, a host interface control circuit (CONT) 18, a clock pulse generation circuit (CPG) 19, a voltage detection circuit (VDTC) 20, a timer circuit (TMR) 21, and a program circuit (PGM) 24. When the CONT 28 accepts a memory card command given by the host device 2, it returns an acknowledgment to the host device 2. The CONT 28 interprets the memory card command it has accepted and issues an interrupt determined according to the content of the command to the MPU 10. The MPU 10 performs processing in accordance with the interrupt. The CPG 19 generates an internal clock signal CLK of the memory card controller 3.
The operating supply voltage for the memory card 1 is, as shown in
The host interface control circuit 18 gives, in response to a command from the host device 2, a corresponding interrupt signal (including an exception processing request signal) to the MPU 10. A reset signal φrst is an interrupt signal outputted by the host interface control circuit 18. When the operating power supply is turned on and the reset signal φrst goes low, the inside of the MPU 10 is initialized in terms of hardware. When the reset signal φrst subsequently goes low, so-called resetting is canceled and the MPU 10 executes the power-on reset exception processing.
The timer 21 is composed of a counter circuit made of plural flip-flop circuits connected in series. It detects elapse of a time-out period which is longer than the time required to execute the power-on reset exception processing. When a timer control signal φtmr outputted from the host interface control circuit 18 is asserted, the timer circuit 21 starts counting operation. When a count corresponding to an elapse of the time-out period is reached, the timer circuit 21 outputs a time-out signal stout to the host interface control circuit 18. If the timer control signal φtmr is negated in the course of the counting operation, the timer circuit 21 stops counting and it is then initialized. The program circuit 24 is a circuit where information specifying the time-out period of the timer circuit is programmed. It is composed of, for example, an aluminum master slice or a fuse program circuit. The timer circuit 21 is arranged such that the number of flip-flop circuits connected in series up to an output node for outputting the time-out signal φtout can be changed based on the information programmed in the program circuit 24. The time-out period is longer when the number of flip-flop circuits connected in series as described above is larger. The time-out period may be determined, in cases where an aluminum master slice is used, by changing the photomask depending on the manufacturing process or, in cases where a fuse program circuit is used, by determining the state of the fuse program depending on characteristic data obtained as a result of device testing. If it is not necessary to strictly determine the time-out period, the program circuit 24 is not required.
When the memory card 1 is inserted in the host device 2, the supply voltage Vdd starts being supplied to the memory card 1. When the voltage detection circuit 20 detects that the supply voltage vdd has reached or exceeded the minimum voltage VLmcc, it asserts a detection signal φdtc to the host interface control circuit 18. When the detection signal φdtc is asserted, the host interface control circuit 18 asserts a clock control signal φck causing the CPG 19 to output the clock signal CLK. The clock signal CLK is supplied to the MPU 10 and other clock synchronous circuits. The host interface control circuit 18 has an initialization command reception flag (a first flag) ICMDR and an initialization failure flag (a second flag) IFAIL. The initialization command reception flag ICMDR is changed from a reset state to a set state when the initialization command is received from the host device 2 for the first time after the detection signal φdtc is asserted. The initialization failure flag IFAIL is changed from a reset state to a set state when the time-out signal φtout is asserted. It is returned from the set state to the reset state when the reset exception processing is completed. Processing for returning the initialization failure flag IFAIL to the reset state may be performed, for example, at the same time as when the MPU 10, upon receiving the initialization command, returns a response to the host device 2. When the initialization command φcmd is received from the host device 2, the host interface control circuit 18 refers to the initialization command reception flag ICMDR and the initialization failure flag IFAIL. At this time, if the initialization command reception flag ICMDR and the initialization failure flag IFAIL are both in the reset state or both in the set state, the host interface control circuit 18 instructs, in response to the initialization command, the MPU 10 to perform the reset exception processing. Even if the MPU 10 is given, the host interface control circuit 18 does not allow the MPU 10 to start the reset exception processing if the initialization command reception flag ICMDR is in the set state whereas the initialization failure flag IFAIL is in the reset state.
When the detection signal φdtc is asserted, the host interface control circuit 18 sets the reset signal φrst low, thereby instructing the MPU 10 to initialize itself. The host interface control circuit 18 referring to the flags ICMDR and IFAIL detects when the initialization command φcmd is received from the host device 2 for the first time after the detection signal φdtc has been asserted. It then sets, after elapse of at least a delay time required to initialize the MPU 10 in terms of hardware, the reset signal φrst high, thereby instructing the MPU 10 to perform the reset exception processing. At the same time, it asserts the timer control signal φtmr. When the reset exception processing is completed, the MPU 10 negates the timer control signal φtmr and resets the flag IFAIL. Subsequently, the MPU 10, after confirming that the flash memory 4 can be accessed normally, reads ID information from the flash memory 4 and makes initialization based on the ID information read out from the flash memory 4. The MPU 10 then returns a response for the initialization command to the host device 2 and returns to the main routine. This enables the memory card 1 to perform memory operation in response to a command subsequently received from the host device 2. When, on the other hand, the time-out signal φtout is asserted, the flag IFAIL is reset. When this occurs, obviously, the reset exception processing has not been terminated normally. No response for the initialization command is therefore returned to the host device 2. The host device 2 then gives the initialization command φcmd to the MPU 10 again. In this state, with the flag IFAIL having been reset, the host interface control circuit 18 sets the reset signal φrst low thereby instructing the MPU 10 to make initialization. The host interface control circuit 18 can make the MPU 10 perform the reset exception processing again by, after elapse of at least the delay time required to initialize the MPU 10 in terms of hardware, asserting the reset signal φrst and the timer control signal φtmr. This process can be repeated until the supply voltage Vdd reaches a required voltage value, so that occurrence of a state where the MPU 10 is deadlocked during power-on reset processing causing the memory card to become nonoperational at all can be prevented.
A dual voltage memory card 1 is compatible with two operating voltages, that is, 1.8 V nominal (low potential power supply) as indicated in
Based on the assumption that the memory card is compatible with a supply voltage of 3.3 V nominal, reference numeral 40A in
An actual configuration of the dual voltage memory card 1 may be one in which, when using a high potential power supply, the supply voltage is lowered using a voltage regulator so as to make the card controller operate in the same voltage range as when using a low potential power supply, or it may be one in which the withstand voltage of the card controller is high enough to allow the card controller to operate using whichever of the low potential and high potential power supplies. In the former case, circuit portions to operate while being directly subjected to the supply voltage Vdd, for example, the input circuit for the supply voltage Vdd and the voltage detection circuits 20 and 30 are required to withstand a high voltage. No matter which of the low potential and high potential power supplies is used, the flash memory 4 requires a voltage boosting operation to obtain a high voltage required for write and erase operations, so that the supply voltage Vdd supplied from outside is supplied, as it is, to the flash memory. Therefore, the flash memory is provided with functions for being compatible with dual voltage power supply. It can, for example, determine whether the supply voltage is of a low potential or of a high potential and change the voltage boosting ratio as required. The voltage detection circuit 30 checks whether or not the supply voltage Vdd has exceeded the voltage VLfsh. When the voltage VLfsh has been exceeded, the voltage detection circuit 30 asserts the detection signal φdtc2 and supplies it to the external interface control circuit 18. When the detection signal φdtc2 is asserted, the external interface control circuit 18 enables a level conversion function of the FIF 15 so that the flash memory 4 is allowed to operate using the high potential power supply.
The supply voltage Vdd for the dual voltage memory card 1 ranges as shown in
The power-on reset processing performed in the dual voltage memory card 1 is the same as described in the foregoing. When the configuration shown in
The present invention has been concretely described with respect to preferred embodiments. The present invention, however, is not limited to the above embodiments. Various changes and modifications may be made without departing from the spirit and scope of the invention.
For example, the conditions for responding again to the initialization command from the host device and having the reset exception processing started are not limited to a time-out detected by the timer circuit 21 and a data disagreement detected by the decision circuit 31. An occurrence, for example, of a state in which the data processing section has become or is anticipated to become out of control during the reset exception processing may also be used as one of such conditions.
The memory to be employed as a memory card is not limited to a flash memory. It may be, for example, an EEPROM or a mask ROM. The application of the present invention is not limited to a combination of a memory card controller and memory. It can also be applied, for example, to a nonvolatile storage apparatus incorporating a controller which has a data processing section capable of executing instructions and an external interface section, and a device to be controlled by the controller. The present invention can also be applied to a semiconductor device such as a controller having a data processing section capable of executing instructions and an external interface section.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2005-091034 | Mar 2005 | JP | national |
