NONVOLATITLE MEMORY ARRAY AND METHOD FOR OPERATING THEREOF

Abstract

A mixed nonvolatile memory array. In the mixed nonvolatile memory array, each nonvolatile memory cell has at least one depletion mode memory cell. The depletion mode region is composed of a gate structure and a doped region. Since the thickness of the doped region is relatively thin, a voltage is applied on the gate structure to invert the conductive type of the doped region under the gate structure. Meanwhile, a bias is applied at both terminals of the doped region so as to control the operation of the depletion mode memory cell. In addition, each nonvolatile memory cell of the mixed nonvolatile memory array further comprises an enhanced mode memory cell. Therefore, each nonvolatile memory cell provides at least four carrier storage spaces so that the numbers of bits storing in a unit memory device is increased.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a top view showing a mixed nonvolatile memory array according to one embodiment of the present invention.

FIG. 2 is a cross-sectional view along a line 2-2 of a mixed nonvolatile memory array according to one embodiment of the present invention.

FIG. 3 is a cross-sectional view along a line 3-3 of a mixed nonvolatile memory array according to one embodiment of the present invention.

FIG. 4A is a cross-sectional view a depletion mode memory cell of a mixed nonvolatile memory array during a programming process is performed on the depletion mode memory cell according to one embodiment of the present invention.

FIG. 4B is a cross-sectional view a depletion mode memory cell of a mixed nonvolatile memory array during a reading process is performed on the depletion mode memory cell according to one embodiment of the present invention.

FIG. 4C is a cross-sectional view a depletion mode memory cell of a mixed nonvolatile memory array during an erasing process is performed on the depletion mode memory cell according to one embodiment of the present invention.

FIG. 5A is a cross-sectional view an enhanced mode memory cell of a mixed nonvolatile memory array during a programming process is performed on the enhanced mode memory cell according to one embodiment of the present invention.

FIG. 5B is a cross-sectional view an enhanced mode memory cell of a mixed nonvolatile memory array during a reading process is performed on the enhanced mode memory cell according to one embodiment of the present invention.

FIG. 5C is a cross-sectional view an enhanced mode memory cell of a mixed nonvolatile memory array during an erasing process is performed on the enhanced mode memory cell according to one embodiment of the present invention.

FIG. 6 is top view showing a mixed nonvolatile memory array according to another embodiment of the present invention.

FIG. 7 is top view showing a mixed nonvolatile memory array according to the other embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a top view showing a mixed nonvolatile memory array according to one embodiment of the present invention. FIG. 2 is a cross-sectional view along a line 2-2 of a mixed nonvolatile memory array according to one embodiment of the present invention. FIG. 3 is a cross-sectional view along a line 3-3 of a mixed nonvolatile memory array according to one embodiment of the present invention. As shown in FIGS. 1, 2 and 3, at least two parallel doped regions 102 are positioned in a substrate 100. The doped regions 102 include a first doped region 102a and a second doped region 102b. The substrate 100 can be a substrate having a first conductive type or a silicon-on-insulator substrate.

In addition, the doped regions 102 including the first doped region 102a and the second doped region 102b have a second conductive type. The doped regions 102 extend from a top surface of the substrate 100 toward to a bottom of the substrate 100. The thickness of the doped regions 102 can be about 200 angstroms, for example. Furthermore, the doped regions 102 are separated from each other. Moreover, the doped regions 102 can be, for example, buried bit lines. Further, when the first conductive type is P type, the second conductive type is N type; when the first conductive type is N type, the second conductive type is P type.

As shown in FIGS. 1, 2 and 3, at least one gate structure 104 comprising a first gate structure 104a and a second gate structure 104b is positioned on the substrate 100 and across the doped regions 102. The first gate structure 104a and the second gate structure 104b are parallel to each other and each gate structure 104 includes a multi-carrier storage element 108 located on the substrate 100 and a gate 110 located on the multi-carrier storage element 108. Moreover, the multi-carrier storage element 108 can be, for example, an oxide/nitride/oxide layer which is a stacked layer formed by stacking an oxide layer 112, a nitride layer 114 and an oxide layer 116on the substrate 100 sequentially. Further, the nitride layer 114 is used as an electron or hole trapping element in the operations of the nonvolatile memory array.

As shown in FIG. 1, a two-feature-size square (4F²) region 106 is circled by bold-dotted line, wherein the feature size is half of a smallest device pitch. In the nonvolatile memory array of the present embodiment of the invention, the gate pitch of the gate structure is smaller than or equal to double feature size. Furthermore, the mixed type nonvolatile memory array of the present embodiment possesses a plurality of 4F² regions 106 and each 4F² region 106 includes at least one nonvolatile memory cell.

In addition, each nonvolatile memory cell includes at least one depletion mode memory cell. As shown in FIG. 2, taking a nonvolatile memory cell in the 4F² region 106 as an example, the depletion mode memory cell is composed of the first doped region 102a and the first gate structure 104a. Also, as shown in FIG. 1, the depletion mode memory cell composed of the first doped region 102a and the first gate structure 104 comprises at least a third carrier storage space 114a and a fourth carrier storage space 114b located at both sides of the multi-carrier storage element 108 and adjacent to the first doped region 102a respectively.

Moreover, every nonvolatile memory cell further comprises an enhanced mode memory cell. As shown in FIG. 3, taking a nonvolatile memory cell in the 4F² region 106 as an example, the enhanced mode memory cell is composed of the first gate structure 104a, a portion of the first doped region 102a covered by the first gate structure 104a and a portion of the second doped region 102b covered by the first gate structure 104a.

Therefore, when a nonvolatile memory cell comprises both an enhanced mode memory cell and a depletion mode memory cell, the nonvolatile memory cell is a mixed type nonvolatile memory cell. By comparing with the conventional nitride read-only memory, the aforementioned mixed nonvolatile memory array does not need a buried diffusion oxide layer structure, and the oxide/nitride/oxide layer under the gate is remained. That is, there is no conventional buried diffusion oxide layer structure above the substrate 100 and the gate structure 104 possesses a complete multi-carrier storage element 108.

FIG. 4A is a cross-sectional view a depletion mode memory cell of a mixed nonvolatile memory array during a programming process is performed on the depletion mode memory cell according to one embodiment of the present invention. As shown in FIGS. 1 and 2, when there is no operation is performed on the depletion mode memory cell of a nonvolatile memory cell in the 4F² region 106, the channel region in the substrate 100 under the first gate structure 104a is in a turn on situation normally. Referring to FIG. 1 together with FIG. 4A, during the depletion mode memory cell of the nonvolatile memory cell is programmed, a voltage is applied on the first gate structure 104a to invert a portion of the first doped region 102a having the second conductive type and covered by the first gate structure 104a into a doped region 118a, which is the inversion region 118a, with the first conductive type. That is, the channel region in the substrate 100 under the first gate structure 104a is turned off. Simultaneously, a bias is applied on the first doped region 102a to program the depletion mode memory cell.

Preferably, when the first doped region 102a is an N type doped region, a second voltage is applied on the first gate structure 104a to invert the portion of the doped region 102a under the first gate structure 104a into the doped region 118a with P conductive type, wherein the second voltage is of about −7 volt. Meanwhile, a second bias is applied on an A terminal and a B terminal of the first doped region 102a. The second bias applied on the A terminal and the B terminal of the first doped region 102a can be accomplished by applying a 5 volt on the A terminal and grounding the B terminal. By applying the second bias on the first doped region 102a, a programming process in a way of band-to-band tunneling hot carrier, such as the band-to-band tunneling hot hole process, is triggered so as to inject holes from the first doped region 102a into a third carrier storage space 114a in a portion of the multi-carrier storage element 108 in the first gate structure 104a near to the A terminal. Hence, the threshold voltage at the third carrier storage space 114a is decreased from −2 volt to −5 volt. On the other hand, when the second voltage applied on the first gate structure 104a is fixed, the A terminal is grounded and a 5 volt is applied on the B terminal, the programming process in a way of band-to-band tunneling hot hole is triggered to inject holes from the first doped region 102a into a fourth carrier storage space 114b in a portion of the multi-carrier storage element 108 in the first gate structure 104a near to the B terminal. Therefore, the threshold voltage at the fourth carrier storage space 114b is decreased from −2 volt to −5 volt. Although the programming process in a way of band-to-band tunneling hot hole is recited above, the other programming process can be also applied to program the depletion mode memory cell by applying proper voltages on the first gate structure 104a and the first doped region 102a.

FIG. 4B is a cross-sectional view a depletion mode memory cell of a mixed nonvolatile memory array during a reading process is performed on the depletion mode memory cell according to one embodiment of the present invention. Referring to FIG. 1 together with FIG. 4B, during a reading process is performed on the depletion mode memory cell having the third carrier storage space 114a storing holes 114a′, a voltage is applied on the first gate structure 104a. Therefore, a portion of the first doped region 102a directly under the third carrier storage space 114a and a portion of the first doped region 102a exposed by the first gate structure 104a still possess the second conductive type but the rest portion of the first doped region 102a is converted into a doped region 118b, which is an inversion region, with the first conductive type. In other words, when this depletion mode memory cell is at a carrier storage state, the so-called on state, the conductive type of the portion of the first doped region 102a right under the first gate structure 104a is inverted from the second conductive type into the first conductive type. That is, an inversion region is formed in the first doped region right under a portion of the first gate structure. On the other words, the channel region in the substrate 100 under the first gate structure 104a is partially turned off. Simultaneously, a bias is applied on the first doped region 102a to read the depletion mode memory cell.

Preferably, when the first doped region 102a is an N type doped region, a third voltage is applied on the first gate structure 104a to invert the portion of the doped region 102a under the first gate structure 104a into the doped region 118a with P conductive type, wherein the third voltage can be in a range from −2 volt to −5 volt and the preferred value of the third voltage is of about −3 volt. Meanwhile, a bias is applied on the A terminal and the B terminal of the first doped region 102a. The bias applied on the A terminal and the B terminal of the first doped region 102a can be accomplished by applying a 2 volt on the B terminal and grounding the A terminal. By applying the bias on the first doped region 102a, a reading process in a way of reverse read is triggered to read the third carrier storage space 114a′ of this depletion mode memory cell. Although the reading process in a way of reverse read is recited above, the other reading process such as forward reading process can be also applied to read the depletion mode memory cell by applying proper voltages on the first gate structure 104a and the first doped region 102a.

Alternatively, under the circumstance that there is no carrier stored in the multi-carrier storage element, during a reading process is performed on the depletion mode memory cell, by applying a voltage on the gate structure, the conductive type of the portion of the doped region covered by the gate structure is converted from the second conductive type into the first conductive type. That is, an inversion region is formed in the first doped region 102a right under the first gate structure. On the other words, under the situation that the depletion mode memory cell is at a non-carrier storage state, the so-called off state, the channel region in the substrate under the first gate structure is totally turned off during the reading process is performed on the depletion mode memory cell.

FIG. 4C is a cross-sectional view a depletion mode memory cell of a mixed nonvolatile memory array during an erasing process is performed on the depletion mode memory cell according to one embodiment of the present invention. Referring to FIG. 1 together with FIG. 4C, during an erasing process is performed on the depletion mode memory cell, a voltage is applied on the first gate structure 104a and both the A terminal and the B terminal of the first doped region 102a are grounded.

Preferably, when the first doped region 102a is an N type doped region, a fourth voltage is applied on the first gate structure 104a and both the A terminal and the B terminal of the doped region 102a are grounded, wherein the fourth voltage can be −20. By applying the fourth voltage on the first gate structure 104a and grounding the first doped region 102a, an erasing process in a way of Fowler-Nordheim tunneling effect is triggered. Hence, the threshold voltage of the depletion mode memory cell is increased from −5 volt to −2 volt. Notably, the conductive type of the portion of the first doped region 102 covered by the first gate structure 104a is inverted from the second conductive type into the first conductive type by applying the fourth voltage on the first gate structure 104a. Although the erasing process in a way of Fowler-Nordheim tunneling effect is recited above, the other erasing process can be also applied on the depletion mode memory cell by applying proper voltages on the first gate structure 104a and the first doped region 102a.

FIG. 5A is a cross-sectional view a enhanced mode memory cell of a mixed nonvolatile memory array during a programming process is performed on the enhanced mode memory cell according to one embodiment of the present invention. As shown in FIGS. 1 and 3, when there is no operation is performed on the enhanced mode memory cell of a nonvolatile memory cell in the 4F² region 106, the channel region in the substrate 100 under the first gate structure 104a between the first doped region 102a and the second doped region 102b is in a turn off situation normally. That is, the conductive type of the channel region is the first conductive type. Referring to FIG. 1 together with FIG. 5A, during the enhanced mode memory cell of the nonvolatile memory cell is programmed, a voltage is applied on the first gate structure 104a to invert the channel region having the first conductive type into a channel region 120 with the second conductive type. That is, the channel region in the substrate 100 under the first gate structure 104a between the first doped region 102a and the second doped region 102b is turned on. Simultaneously, a bias is applied between the first doped region 102a and the second doped region 102b to program the enhanced mode memory cell.

Preferably, when the first doped region 102a and the second doped region 102a are both the N type doped regions, a first voltage of about 12 volt is applied on the first gate structure 104a, a fifth voltage of about 5 volt is applied on the first doped region 102a and a sixth voltage of about 0 volt is applied on the second doped region 102b. Therefore, a programming process in a way of channel hot carrier, such as a channel hot electron process, is triggered so as to inject electrons from the second doped region 102b (i.e. source region) into a second carrier storage space 114d in a portion of the multi-carrier storage element 108 in the first gate structure 104a between the first doped region 102a and the second doped region 102b and near the first doped region 102a (i.e. drain region). Hence, the threshold voltage at the second carrier storage space 114d is increased from 6 volt to 9 volt. On the other hand, when the first voltage applied on the first gate structure 104a is fixed, the fifth voltage is of about 0 volt and the sixth voltage is of about 5 volt, the programming process in a way of channel hot electron is triggered to inject electrons from the first doped region 102a (i.e. source region) into a first carrier storage space 114c in a portion of the multi-carrier storage element 108 in the first gate structure 104a between the first doped region 102a and the second doped region 102b and near the second doped region 102b (i.e. drain region). Therefore, the threshold voltage at the first carrier storage space 114c is increased from 6 volt to 9 volt. Although the programming process in a way of channel hot electron is recited above, the other programming process can be also applied to program the enhanced mode memory cell by applying proper voltages on the first gate structure 104a, the first doped region 102a and the second doped region 102b.

FIG. 5B is a cross-sectional view a enhanced mode memory cell of a mixed nonvolatile memory array during a reading process is performed on the enhanced mode memory cell according to one embodiment of the present invention. Referring to FIG. 1 together with FIG. 5B, during a reading process is performed on the enhanced mode memory cell having the first carrier storage space 114c storing electrons 114c′, a voltage is applied on the first gate structure 104a to turn on a channel region 122 with the second conductive type in the substrate 100 covered by the first gate structure 104a between the first doped region 102a and the second doped region 102b, wherein the channel region 122 is near the top surface of the substrate 100. Simultaneously, a bias is applied between the first doped region 102a and the second region 102b to read the enhanced mode memory cell.

Preferably, when the first doped region 102a and the second doped region 102a are both the N type doped regions, a seventh voltage, a eight voltage and a ninth voltage are applied on the first gate structure 104a, the first doped region 102a and the second doped region 102b respectively. Therefore, a reading process in a way of reverse read is triggered to read the first carrier storage space 114c′ of this enhanced mode memory cell. Notably, the seventh voltage can be in a range from 6 volt to 9 volt and the preferred value of the seventh voltage is of about 8 volt. Furthermore, the eighth voltage is of about 2 volt and the ninth voltage is about of 0 volt. Although the reading process in a way of reverse read is recited above, the other reading process such as forward reading process can be also applied to read the enhanced mode memory cell by applying proper voltages on the first gate structure 104a, the first doped region 102a and the second doped region 102b.

FIG. 5C is a cross-sectional view a enhanced mode memory cell of a mixed nonvolatile memory array during an erasing process is performed on the enhanced mode memory cell according to one embodiment of the present invention. Referring to FIG. 1 together with FIG. 5C, during an erasing process is performed on the enhanced mode memory cell, a voltage is applied on the first gate structure 104a and both the first doped region 102a and the second doped region 102b are grounded.

Preferably, when the first doped region 102a and the second doped region 102a are both the N type doped regions, a tenth voltage of about −20 volt is applied on the first gate structure 104a and both the first doped region 102a and the second doped region 102b are grounded. By applying the tenth voltage on the first gate structure 104a and grounding the first doped region 102a and the second doped region 102b, an erasing process in a way of Fowler-Nordheim tunneling effect is triggered. Hence, the threshold voltage of the enhanced mode memory cell is decreased from 9 volt to 6 volt. Although the erasing process in a way of Fowler-Nordheim tunneling effect is recited above, the other erasing process can be also applied on the depletion mode memory cell by applying proper voltages on the first gate structure 104a, the first doped region 102a and the second doped region 102b.

In the embodiment described above, in every 4F² region 106, there is at least one nonvolatile memory cell. As for each nonvolatile memory cell, there are at least one pair memory cell including a depletion mode memory cell and an enhanced mode memory cell. In addition, each of the depletion mode memory cell and the enhanced mode memory cell possesses two carrier storage spaces. In other words, for each 4F² region 106, at least four bits can be stored therein.

FIG. 6 is top view showing a mixed nonvolatile memory array according to another embodiment of the present invention. As shown in FIG. 6, a similar gate structures are inserted in the gate space between each two gate structures 104 in the above embodiment so that the gate pitch of the gate structure 604 is smaller than or equal to one feature size F. Therefore, for each 4F² region 606, there are at least two nonvolatile memory cells. That is, there are eight carrier storage spaces including space 614a, space 614b, space 614c, space 614d , space 614e, space 614f, space 614g and space 614h in a 4F² region 606. More specifically, each 4F² region 606 can store at most 8 bits.

FIG. 7 is top view showing a mixed nonvolatile memory array according to the other embodiment of the present invention. As shown in FIG. 7, when there are n (where n is not less than 3) gate structures within a 4F² region 706, there are 4n carrier storage spaces within the 4F² region 706. That is, at most 4n bits can be stored in a single 4F² region 706.

Altogether, in the present invention, the oxide/nitride/oxide layer is used as a carrier trapping element and the doped region with the relatively small thickness is used as the source/drain regions and the channel region of both the depletion mode memory cell and the enhanced mode memory cell. By applying the voltages on the gate structures and the doped regions, the conductive type of a portion of the doped region under the gate structure is exchanged to either turn on or turn off the channel between the source/drain regions. Therefore, there is no need to perform additional ion implantation process and gate patterning process so that the manufacturing cost is decreased. Furthermore, for each memory cell of the present invention, there are a depletion mode memory cell and an enhanced mode memory cell. Hence, the density of the carrier storage space is increased. That is, for each 4F² region, there are at least four carrier storage spaces. Moreover, when there are n gate structures within a 4F² region, the number of the carrier storage spaces is greatly increased.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing descriptions, it is intended that the present invention covers modifications and variations of this invention if they fall within the scope of the following claims and their equivalents.

Claims

1. A nonvolatile memory cell comprising: a substrate;a doped region located in the substrate, wherein the doped region has a conductive type and the doped region extends from a top surface of the substrate toward to a bottom of the substrate; anda gate structure located on the substrate and across the doped region, wherein the gate structure comprises a multi-carrier storage element on the doped region and a gate on the multi-carrier storage element and the multi-carrier storage element comprises at least two carrier storage spaces including a first carrier storage space and a second carrier storage space, wherein the first carrier storage space and the second carrier storage space are located adjacent to the multi-carrier storage element at both side of the doped region respectively and there is no buried diffusion oxide layer structure over the substrate and the gate structure has complete the multi-carrier storage element.

2. The nonvolatile memory cell of claim 1, wherein, during a programming process is performed on the nonvolatile memory cell, the doped region further comprises a first inversion region in a portion of the doped region covered by the gate structure.

3. The nonvolatile memory cell of claim 2, wherein the conductive type of the first inversion region is different from that of the doped region.

4. The nonvolatile memory cell of claim 1, wherein, during a reading process is performed on the nonvolatile memory cell: when the first storage space of the multi-carrier storage element stores at least one carrier, the doped region further comprises a second inversion region located in a portion of the doped region covered by a portion of the gate structure other than the first carrier storage space; andwhen there is no carrier stored in the multi-carrier storage element, the doped region has a third inversion region located in a portion of the doped region covered by the gate structure.

5. The nonvolatile memory cell of claim 4, wherein the second inversion region and the third inversion region possess the same conductive type and the conductive types of the second inversion region and the third inversion region are different from the conductive type of the doped region.

6. The nonvolatile memory cell of claim 1, wherein, during an erasing process is performed on the nonvolatile memory cell, the doped region has a fourth inversion region in a portion of the doped region covered by the gate structure.

7. The nonvolatile memory cell of claim 6, wherein the conductive type of the fourth inversion region is different from that of the doped region.

8. The nonvolatile memory cell of claim 1, wherein a thickness of the doped region is of about 200 angstroms.

9. The nonvolatile memory cell of claim 1, wherein the multi-carrier storage element comprises an oxide/nitride/oxide layer.

10. The nonvolatile memory cell of claim 1, wherein there is at least one nonvolatile memory cell in a two-feature-size square region.

11. The nonvolatile memory cell of claim 1, wherein a gate pitch size of the gate structure is smaller than a feature size.

12. A mixed nonvolatile memory array having a plurality of mixed type memory cell, comprising: a substrate having a first conductive type, wherein the substrate possesses at least two doped regions including a first doped region and a second doped region, the first doped region and the second doped region extend from a top surface of the substrate toward to a bottom of the substrate, the first doped region and the second doped region are parallel to each other and the first doped region and the second doped region possesses a second conductive type; andat least a gate structure located on the substrate and across the doped regions and possessing a plurality of carrier storage spaces, wherein the gate structure, the first doped region and the second doped region together form a mixed type memory cell and the mixed type memory cell comprises: an enhanced mode memory cell composed of the gate structure, a portion of the first doped region covered by the gate structure and a portion of the second doped region covered by the gate structure; anda depletion mode memory cell composed of the first doped region and the gate structure.

13. The mixed nonvolatile memory array of claim 12, wherein, during a programming process is performed on the depletion mode memory cell, the first doped region has a first inversion region located in a portion of the first doped region covered by the gate structure and the conductive type of the first inversion region is different from that of the first doped region.

14. The mixed nonvolatile memory array of claim 12, wherein, during a reading process is performed on the depletion mode memory cell: when the depletion mode memory cell is at a carrier storage state, the first doped region possesses a second inversion region covered by a portion of the gate structure other than the carrier storage spaces, which store at least one carrier, and the conductive type of the second inversion region is different from that of the first doped region; andwhen the depletion mode memory cell is at a non-carrier storage state, the first doped region has a third inversion region covered by the gate structure and the conductive type of the third inversion region is different from that of the first doped region.

15. The mixed nonvolatile memory array of claim 12, wherein, during an erasing process is performed on the depletion mode memory cell, the first doped region has a fourth inversion region covered by the gate structure and the conductive type of the fourth inversion region is different from that of the first doped region.

16. The mixed nonvolatile memory array of claim 12, wherein a thickness of each of the doped regions is of about 200 angstroms.

17. The mixed nonvolatile memory array of claim 12, wherein when the first conductive type is P type, the second conductive type is N type; when the first conductive type is N type, the second conductive type is P type.

18. The mixed nonvolatile memory array of claim 12, wherein the gate structure comprises a multi-carrier storage element located on the substrate and a gate located on the multi-carrier storage element.

19. The mixed nonvolatile memory array of claim 18, wherein the multi-carrier storage element includes an oxide/nitride/oxide layer.

20. The mixed nonvolatile memory array of claim 12, wherein the enhanced mode memory cell comprises a first carrier storage space and a second carrier storage space located at a portion of the gate structure between the first doped region and the second doped region, the first carrier storage space is adjacent to the first doped region and the second carrier storage space is adjacent to the second doped region.

21. The mixed nonvolatile memory array of claim 12, wherein the depletion mode memory cell comprises a third carrier storage space and a fourth carrier storage space located in both sides of the gate structure covering the first doped region and adjacent to the first doped region respectively.

22. The mixed nonvolatile memory array of claim 12, wherein there is at least one mixed type memory cell in a two-feature-size square region.

23. The mixed nonvolatile memory array of claim 12, wherein a gate pitch size of the gate structure is smaller than a feature size.

24. The mixed nonvolatile memory array of claim 12, wherein the gate structure further comprises a complete multi-carrier storage element having the carrier storage spaces.

25. A method for programming a nonvolatile memory array having a plurality of memory cells, wherein each memory cell includes a first doped region of a second conductive type and a second doped region of the second conductive type located in a substrate of a first conductive type and parallel to and adjacent to each other, each memory cell further includes a gate structure located on the substrate and across the first doped region and the second doped region, the first doped region and the gate structure together form a depletion mode memory cell and the first doped region, the second doped region and the first gate structure together form an enhanced mode memory cell, and method comprising: during the enhanced mode memory cell is programmed, applying a first voltage on the gate structure to turn on a channel region having the second conductive type in the substrate under the gate structure between the first doped region and the second doped region and applying a first bias between the first doped region and the second doped region to inject a plurality of electrons into the gate structures in a way of channel hot carrier; andduring the depletion mode memory cell is programmed, applying a second voltage on the gate structure to invert a conductive type of a portion of the first doped region under the gate structure from the second conductive type into the first conductive type and applying a second bias on the first doped region to inject a plurality of holes into the gate structures in a way of band-to-band tunneling hot carrier.

26. The method of claim 25, wherein a thickness of the first doped region is of about 200 angstroms and a thickness of the second doped region is of about 200 angstroms.

27. The method of claim 25, wherein when the first conductive type is P type and the second conductive type is N type, the channel hot carrier includes a channel hot electron process and the band-to-band tunneling hot carrier includes a band-to-band tunneling hot hole process.

28. The method of claim 25, wherein the gate structure comprises a multi-carrier storage element located on the substrate and a gate located on the multi-carrier storage element.

29. The method of claim 28, wherein the multi-carrier storage element includes an oxide/nitride/oxide layer.

30. A method for reading a nonvolatile memory array having a plurality of memory cells, wherein each memory cell includes a first doped region of a second conductive type and a second doped region of the second conductive type located in a substrate of a first conductive type and parallel to and adjacent to each other, each memory cell further includes a gate structure located on the substrate and across the first doped region and the second doped region, the first doped region and the gate structure together form a depletion mode memory cell and the first doped region, the second doped region and the first gate structure together form an enhanced mode memory cell, and method comprising: during the enhanced mode memory cell is read, applying a first voltage on the gate structure to turn on a channel region having the second conductive type in the substrate under the gate structure between the first doped region and the second doped region and applying a first bias between the first doped region and the second doped region to read the enhanced mode memory cell in a way of reverse read; andduring the depletion mode memory cell is read, applying a second voltage on the gate structure to invert a conductive type of a portion of the first doped region under the gate structure from the second conductive type into the first conductive type and applying a second bias on the first doped region to read the depletion mode in the way of reverse read.

31. The method of claim 30, wherein a thickness of the first doped region is of about 200 angstroms and a thickness of the second doped region is of about 200 angstroms.

32. The method of claim 30, wherein the gate structure comprises a multi-carrier storage element located on the substrate and a gate located on the multi-carrier storage element.

33. The method of claim 32, wherein the multi-carrier storage element includes an oxide/nitride/oxide layer.

34. A method for erasing a nonvolatile memory array having a plurality of memory cells, wherein each memory cell includes a first doped region of a second conductive type and a second doped region of the second conductive type located in a substrate of a first conductive type and parallel to and adjacent to each other, each memory cell further includes a gate structure located on the substrate and across the first doped region and the second doped region, the first doped region and the gate structure together form a depletion mode memory cell and the first doped region, the second doped region and the first gate structure together form an enhanced mode memory cell, and method comprising: during the enhanced mode memory cell is erased, applying a first voltage on the gate structure and grounding the first doped region and the second doped region to erase the enhanced mode memory cell in a way of Flowler-Nordheim tunneling effect; andduring the depletion mode memory cell is erased, applying a second voltage on the gate structure and grounding the first doped region to erase the depletion mode in the way of Flowler-Nordheim tunneling effect.

35. The method of claim 34, wherein a thickness of the first doped region is of about 200 angstroms and a thickness of the second doped region is of about 200 angstroms.

36. The method of claim 34, wherein the gate structure comprises a multi-carrier storage element located on the substrate and a gate located on the multi-carrier storage element.

37. The method of claim 36, wherein the multi-carrier storage element includes an oxide/nitride/oxide layer.

38. The method of claim 34, wherein, when the enhanced mode memory cell and the depletion mode memory cell are erased at the same time, the first voltage is equal to the second voltage.