Patent Application
20250202437
Embodiments of this application relate to the field of differential amplifier technologies, and in particular, to a novel differential amplifier with a feedforward bias correction circuit, and a device.
A differential amplifier, as a circuit capable of amplifying a difference between two input voltages, is a directly coupled amplifier with a quite small zero drift and is usually used for direct-current amplification. The differential amplifier may provide balanced (the term “balanced” means differential) input and output, or may provide single-terminal (unbalanced) input and output. In addition, the differential amplifier is usually configured to implement mutual conversion between a balanced circuit and an unbalanced circuit and serves as a basic unit of various integrated circuits.
During design of a fully differential amplifier, it is found that an effective bias voltage for the amplifier is related to common-mode voltage output. For a quite small input signal, the common-mode voltage output produces an unacceptably large offset, leading to low accuracy of the differential amplifier.
In view of this, embodiments of this application provide a novel differential amplifier with a feedforward bias correction circuit, and a device, so as to resolve the prior-art technical problem that common-mode voltage output produces an unacceptably large offset due to a quite small input signal, leading to low accuracy of a differential amplifier.
To achieve the foregoing objective, the following technical solutions are provided in the embodiments of this application.
According to a first aspect of the embodiments of this application, an embodiment of this application provides a differential amplifier with a feedforward bias correction circuit. The differential amplifier includes a differential amplifier and a bias correction circuit, where
In a preferred embodiment of this application, the differential amplifier further includes a first resistor, a second resistor, a first feedback circuit, and a second feedback circuit, where
In a preferred embodiment of this application, the bias correction circuit includes a clamping voltage setting circuit and a common-mode voltage regulation circuit, where
In a preferred embodiment of this application, the clamping voltage setting circuit includes a buffer amplifier and a third resistor, where a first input terminal of the buffer amplifier is connected to the reference voltage setting circuit, a second input terminal of the buffer amplifier is connected to a common terminal between an output terminal of the buffer amplifier and a first terminal of the third resistor, and a second terminal of the third resistor is connected to a high-level input terminal of the common-mode voltage regulation circuit.
In a preferred embodiment of this application, the common-mode voltage regulation circuit includes a fourth resistor, a fifth resistor, and a differential amplifier, where
In a preferred embodiment of this application, the differential amplifier is an instrumentation amplifier.
In a preferred embodiment of this application, the common-mode voltage regulation circuit further includes a second feedback circuit, where a first terminal of the second feedback circuit is connected to a common terminal between the second terminal of the fifth resistor and the second input terminal of the differential amplifier.
Compared with the prior art, the embodiments of this application provide a novel differential amplifier with a feedforward bias correction circuit, and a device. Common-mode voltage output of a differential amplifier is dynamically adjusted based on an input voltage by using a bias correction circuit. This can greatly reduce an input voltage error of the differential amplifier caused by an offset of the common-mode voltage output, so that a quite small input signal can be detected at high precision, assisting a common-mode regulation channel in tracking the common-mode voltage output, thereby reducing the offset of the common-mode voltage output and improving accuracy of the differential amplifier.
According to a second aspect, an embodiment of this application further provides a device including the differential amplifier according to the first aspect.
Compared with the prior art, the beneficial effects of the device provided in this embodiment of this application are the same as that of the differential amplifier provided in the first aspect. Details are not described herein again.
To describe the technical solutions of the embodiments of this application or in the prior art more clearly, the following briefly describes the accompanying drawings required for describing the embodiments or the prior art. Apparently, the accompanying drawings in the following descriptions are merely examples, and persons of ordinary skill may still derive other implementation drawings from the provided accompanying drawings without creative efforts.
A structure, a proportion, a size, and the like shown in this specification are merely intended to match content disclosed in this specification to facilitate understanding and reading by persons skilled in the art, but not intended to limit a limiting condition under which this application can be implemented, and therefore have no technical significance. Any structural modification, proportional relationship change, or size adjustment shall still fall within the scope covered by technical content disclosed in this application without affecting effect that can be produced by this application or objectives that can be achieved by this application.
Embodiments of this application are described below by using specific embodiments. Persons skilled in the art can easily understand other advantages and effects of this application from content disclosed in this specification. Apparently, the described embodiments are some but not all of the embodiments of this application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments of this application without creative efforts shall fall within the protection scope of this application.
A first terminal of the first resistor 101 is connected to a high-level input terminal Vin+ of the differential amplifier. A second terminal of the first resistor 101 is connected to a first input terminal a1 of the operational amplifier 105. A first terminal of the second resistor 102 is connected to a low-level input terminal Vin− of the differential amplifier. A second terminal of the second resistor 102 is connected to a second input terminal a2 of the operational amplifier 105. A first terminal of the first feedback circuit 103 is connected to the first input terminal a1 of the operational amplifier 105. A first terminal of the second feedback circuit 104 is connected to the second input terminal a2 of the operational amplifier 105. A second terminal of the first feedback circuit 103 and a second terminal of the second feedback circuit 104 are separately connected to an output terminal b of the operational amplifier 105.
The existing differential amplifier has common-mode voltage input Vcmi, common-mode voltage output Vcmo, the high-level input terminal Vin+, the low-level input terminal Vin−, a high-level output terminal Vout+, and a low-level output terminal Vout−. If an open-loop gain of the differential amplifier tends to be infinite, an output voltage of the differential amplifier (Vout+−Vout−) is calculated according to the following formula:
R1 indicates resistances of the first resistor 101 and the second resistor 102, and the resistances of the first resistor 101 and the second resistor 102 are the same. R2 indicates resistances of the first feedback circuit 103 and the second feedback circuit 104, and the resistances of the first feedback circuit 103 and the second feedback circuit 104 are the same. In a circuit of the differential amplifier, the first resistor (R1) 101, the second resistor (R1) 102, the first feedback circuit (R2) 103, and the second feedback circuit (R2) 104 are configured to set a gain of the differential amplifier. A value of R2/R1 is used to set a closed-loop gain ratio of the differential amplifier. The gain ratio may range from 20 times to 100 times, and the gain may alternatively be larger. This is not limited in this embodiment of this application.
It is assumed that an open-loop gain of the differential amplifier tends to be infinite and an offset of common-mode voltage output may be ignored. An output error Vout,ε,cm of the differential amplifier caused by a mismatch between independent resistors R2 is calculated according to the following formula:
Vcmo is the common-mode voltage output. R1 indicates resistances of the first resistor 101 and the second resistor 102, and the resistances of the first resistor 101 and the second resistor 102 are the same. R2 indicates resistances of the first feedback circuit 103 and the second feedback circuit 104, and the resistances of the first feedback circuit 103 and the second feedback circuit 104 are the same. In practical application of an integrated circuit, two devices are not exactly the same due to a subtle change during manufacturing. Therefore, two resistors R2 are represented by a value of R2 and a value of (1+σ)×R2, where σ is an error change between two R2. Similar analysis may also be performed for R1, but results are quite similar. The output error Vout,ε,cm of the differential amplifier is obtained by multiplying the common-mode voltage output Vcmo by the gain of the differential amplifier.
It can be learned from the formula (II) that the output error Vout,ε,cm of the differential amplifier is mainly determined by the first resistor (R1) 101, the second resistor (R1) 102, the first feedback circuit (R2) 103, the second feedback circuit (R2) 104, and the common-mode voltage output Vcmo.
It can be learned from the prior art that, to reduce the output error Vout,ε,cm of the differential amplifier so as to improve accuracy of the differential amplifier, the common-mode voltage output Vcmo needs to be reduced. The embodiments of this application provide the following technical solutions.
As shown in
The differential amplifier 21 includes an operational amplifier 205.
An input terminal c and an input terminal d of the bias correction circuit 22 are connected to a high-level input terminal Vin+ and a low-level input terminal Vin− of the differential amplifier respectively. An output terminal m of the bias correction circuit 22 is connected to the operational amplifier 205. The bias correction circuit 22 dynamically adjusts common-mode voltage output of the differential amplifier based on an input voltage of the differential amplifier 21.
The differential amplifier 21 further includes a first resistor (R1) 201, a second resistor (R1) 202, a first feedback circuit (R2) 203, and a second feedback circuit (R2) 204.
A first terminal of the first resistor (R1) 201 is connected to the high-level input terminal Vin+ of the differential amplifier. A second terminal of the first resistor (R1) 201 is connected to a first input terminal e of the operational amplifier 205. A first terminal of the second resistor (R1) 202 is connected to the low-level input terminal Vin− of the differential amplifier. A second terminal of the second resistor (R1) 202 is connected to a second input terminal f of the operational amplifier 205. A first terminal of the first feedback circuit (R2) 203 is connected to the first input terminal e of the operational amplifier 205. A first terminal of the second feedback circuit (R2) 204 is connected to the second input terminal f of the operational amplifier 205. A second terminal of the first feedback circuit (R2) 203 and a second terminal of the second feedback circuit (R2) 204 are separately connected to an output terminal n of the operational amplifier 205.
The bias correction circuit 22 includes a clamping voltage setting circuit 22-1 and a common-mode voltage regulation circuit 22-2. A first terminal of the clamping voltage setting circuit 22-1 is connected to a reference voltage setting circuit 212. A second terminal of the clamping voltage setting circuit 22-1 is connected to a first input terminal k of the common-mode voltage regulation circuit 22-2. The first input terminal k of the common-mode voltage regulation circuit 22-2 is connected to the high-level input terminal Vin+ of the differential amplifier. A second input terminal 1 of the common-mode voltage regulation circuit 22-2 is connected to the low-level input terminal Vin− of the differential amplifier. An output terminal m of the common-mode voltage regulation circuit 22-2 is connected to the operational amplifier 205. The clamping voltage setting circuit 22-1 is configured to set a clamping voltage of the common-mode voltage regulation circuit 22-2.
The clamping voltage setting circuit 22-1 includes a buffer amplifier 206 and a third resistor (r2) 207. A first input terminal h of the buffer amplifier 206 is connected to the reference voltage setting circuit 212. A second input terminal i of the buffer amplifier 206 is connected to a common terminal between an output terminal j of the buffer amplifier 206 and a first terminal of the third resistor (r2) 207. A second terminal of the third resistor (r2) 207 is connected to a common terminal between a second terminal of a fourth resistor (r1) 208 and a first input terminal k of a differential amplifier 210.
The buffer amplifier 206 is configured to prevent overloading of the reference voltage setting circuit 212. The reference voltage setting circuit 212 is usually overloaded in a band gap circuit. The reference voltage setting circuit 212 also has quite high impedance in the case of overloading. Any overloading affects a reference voltage (VREF) of the reference voltage setting circuit 212. The buffer amplifier 206 can retain accuracy of the reference voltage (VREF) of the reference voltage setting circuit 212. The third resistor (r2) 207 can reduce a clamping voltage of the bias correction circuit 22.
The common-mode voltage regulation circuit 22-2 includes the fourth resistor (r1) 208, a fifth resistor (r1) 209, and the differential amplifier 210. A first terminal of the fourth resistor (r1) 208 is connected to the high-level input terminal Vin+ of the differential amplifier, and a second terminal of the fourth resistor (r1) 208 is connected to the first input terminal k of the differential amplifier 210. A first terminal of the fifth resistor (r1) 209 is connected to the low-level input terminal Vin− of the differential amplifier, and a second terminal of the fifth resistor (r1) 209 is connected to a second input terminal i of the differential amplifier 210. An output terminal m of the differential amplifier 210 is connected to the operational amplifier 205. The differential amplifier 210 is an instrumentation amplifier. The differential amplifier 210 calculates a difference between the high-level input terminal Vin+ and the low-level input terminal Vin− of the differential amplifier, and then calculates a sum of the difference and the reference voltage (VREF) of the reference voltage setting circuit 212. A reference common-mode voltage VREF_VCM output by the differential amplifier 210 is calculated according to the following formula (III):
The reference common-mode voltage VREF_VCM is set by using the instrumentation amplifier 210. The reference common-mode voltage VREF_VCM set by the common-mode voltage setting circuit is used to adjust common-mode voltage output of the differential amplifier. The reference common-mode voltage VREF_VCM is also another input terminal of the differential amplifier, to facilitate adjustment of the common-mode voltage output of the differential amplifier. To reduce the influence of the common-mode voltage output on the differential amplifier, the reference common-mode voltage VREF_VCM is set based on an input voltage Vin(Vin+−Vin−) by using the instrumentation amplifier 210.
The common-mode voltage regulation circuit 22-2 further includes a second feedback circuit (r2) 211, where a first terminal of the second feedback circuit (r2) 211 is connected to a common terminal between the second terminal of the fifth resistor (r1) 209 and the second input terminal i of the differential amplifier 210.
Each differential amplifier has common-mode voltage input and output. When a mismatch occurs between the first feedback circuit (R2) 203 and the second feedback circuit (R2) 204, the common-mode voltage output causes degradation of accuracy of the differential amplifier. In this embodiment of this application, the bias correction circuit 22 in the differential amplifier adjusts the common-mode voltage output based on an input voltage to reduce a common-mode error.
As shown in
In a specific battery charger, a negative electrode of a battery 215 is connected to a fixed voltage node through an inductive resistor RSNS, so that a battery current can be measured more accurately. An output terminal n of an operational amplifier 205 is connected to an analog-to-digital converter ADC 212. The analog-to-digital converter ADC 212 is a type of device for converting a continuous analog signal into a discrete digital signal. The analog-to-digital converter ADC 212 is connected to a digital controller 213. The digital controller 213 usually has a program for converting an input signal into an output signal. The digital controller 213 completes a specific control algorithm through programming by using computer software. The digital controller 213 is connected to a positive electrode of the battery 215 through a DC/DC converter 214. The DC/DC converter 214 is configured to convert an input voltage into a fixed effective output voltage. The battery charger adjusts a current of the battery by using the differential amplifier provided in this embodiment of this application, preventing damage to the battery.
In battery charging application, because the inductive resistor RSNS is directly connected in a current path, the inductive resistor RSNS is configured to produce a voltage drop for retaining low impedance and reducing power loss. Therefore, a high-fidelity amplifier needs to be used to detect a low voltage that passes through the inductive resistor RSNS, and amplify the voltage to enable the analog-to-digital converter ADC 212 to correctly perform reading. A gain of the differential amplifier 21 may range from 20 times to 100 times. A specific gain multiple depends on a current requirement of the battery, an input requirement of the analog-to-digital converter ADC 212, and selection of the inductive resistor RSNS. The instrumentation amplifier 210 is configured to sample an input voltage and adjust the common-mode voltage output of the differential amplifier 21 to improve accuracy of the differential amplifier.
As shown in
In this embodiment of this application, the differential amplifier 1 and the differential amplifier 2 each have a bias correction circuit 22 to enhance regulation control of a direct current/direct current converter loop. Regulation accuracy of an average current mode loop can be improved through more accurate detection of an inductor current. In this embodiment of this application, a current may be detected at quite high precision and adjusted, allowing for extended battery life, thereby implementing charging at higher precision, preventing damage to the battery, and reducing a risk of a fire.
According to a second aspect, an embodiment of this application further provides a device including the differential amplifier according to the first aspect.
Compared with the prior art, the beneficial effects of the device provided in this embodiment of this application are the same as that of the differential amplifier provided in the first aspect. Details are not described herein again.
Although this application is described above in detail by using general descriptions and specific embodiments, it is apparent to persons skilled in the art that some modifications or improvements may be made based on this application. Therefore, these modifications or improvements made without departing from the spirit of this application fall within the protection scope of this application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202210903044.X | Jul 2022 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2022/114638 | 8/24/2022 | WO |
