1. Field
The present disclosure relates generally to wireless communication and, more particularly, to wireless communication using Orthogonal Frequency Division Multiplexing (OFDM).
2. Background
Channel Estimation (CE) is used in conventional multi-carrier systems such as DVB-H or ISDB-T to obtain an estimate of the channel frequency response for each OFDM sub-carrier and each OFDM symbol for demodulation of OFDM data symbols. Additionally, the CE provides an estimate of the channel impulse response for a time tracking algorithm. Detailed descriptions of various CE algorithms are provided in aforementioned U.S. application Ser. No. 11/777,251.
CE algorithms are based on pilot sub-carriers embedded in the transmitted signal. In order to improve CE performance, pilot information is interpolated over several consecutive symbols. During data demodulation the time tracking algorithm occasionally advances or retards the position of the FFT window in order to keep track with the transmitted signal timing. If these time adjustments are not taken into consideration by the CE algorithm, the CE performance is degraded due to the different time bases of the OFDM symbols used for pilot information interpolation.
To avoid degrading the CE performance, the OFDM symbols (or only the pilot sub-carriers) are translated to the same time basis before interpolating the pilot information. This operation is referred to as timing correction. The time-corrected pilots are interpolated to obtain the channel estimate. The time basis of this channel estimate (which is the identical time basis of all the OFDM symbols used to obtain it) may be different from the time basis of the corresponding OFDM symbol to be demodulated with the channel estimate. If this is the case, the channel estimate has to be translated to the time basis of the corresponding OFDM symbol prior to the demodulation of this OFDM symbol. This operation is referred to as matching the time basis of the channel estimate with the time basis of the OFDM symbol to be demodulated by it.
In U.S. Ser. No. 11/777,251, frequency domain pilot interpolation and time domain pilot interpolation are described. Methods for changing OFDM symbol time basis (for timing correction) and changing channel estimate time basis (for matching the channel estimate time basis to the corresponding OFDM symbol) are described. These methods involve phase operations which have to be performed by hardware or by firmware.
In the CE algorithms described in U.S. Ser. No. 11/777,251, at time n, the consecutive OFDM symbols from time m to time n (m<n) are interpolated to obtain a channel estimate for demodulating the OFDM symbol at time p (m<p<n). All the algorithms assume that when the OFDM symbol at time n (also referred to herein as “OFDM symbol n”) arrives, time-corrected versions of the pilots of OFDM symbol m to OFDM symbol n−1 are stored in memory, with their time basis matching the time basis of OFDM symbol p for which the channel estimate has to be obtained at time n. All the algorithms have the same structure, performing the following steps when OFDM symbol n arrives:
The steps above are repeated for OFDM symbol n+1 and so on.
As can be seen, existing algorithms require many phase operations. Special hardware and special firmware code are required to implement these operations. These operations complicate the design and the verification, increase power consumption and require computation time.
It is desirable in view of the foregoing to provide for simplifying the processes of timing correction among received OFDM symbols, and matching the channel estimate time basis to the time basis of the OFDM symbol to be demodulated.
A pre-FFT cyclic shift is used to achieve time basis matching in OFDM communication. Time basis matching among symbols, and/or between symbols and their corresponding channel estimates may be achieved.
Various aspects of a wireless communications system are illustrated by way of example, and not by way of limitation, in the accompanying drawings, wherein:
a-2f are timing diagrams that illustrate how FFT window cyclic shifting affects a channel impulse response estimate at the receiver;
a-3b are timing diagrams that illustrate the result of a known zero padding process when applied to a channel impulse response estimate that has been affected by FFT window cyclic shifting;
c-3d are timing diagrams that illustrate the desired result of the zero padding process of
The detailed description set forth below in connection with the appended drawings is intended as a description of various embodiments of the present work and is not intended to represent the only embodiments in which the present work may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the present work. However, it will be apparent to those skilled in the art that the present work may be practiced without these specific details. In some instances, well known structures and components are shown in block diagram form in order to avoid obscuring the concepts of the present work.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.
Exemplary embodiments of the present work implement a time domain cyclic shift of the FFT window prior to performing the FFT. The cyclic shift is readily implemented. Some embodiments utilize a simple hardware cyclic addressing implementation. Phase operations such as described above are not required, so the design is simplified, requiring less hardware, firmware code, computation power and design verification time.
In some embodiments, the required cyclic shift is calculated by summing all the FFT window timing updates from the beginning of data demodulation to the current OFDM symbol (for which the cyclic shift is to be calculated). The FFT window of the current symbol is then cyclically shifted by the calculated shift. This operation results in translating each OFDM symbol in the received sequence to the time basis of the first OFDM symbol, so all the OFDM symbols have the same time basis. Because the cyclic shift simultaneously changes the time basis of both the pilot sub-carriers and the data sub-carriers, there is no need to match the channel estimate to the corresponding OFDM symbol to be demodulated using the channel estimate, so the cyclic shift achieves both (1) the desired timing correction among the received OFDM symbols, and (2) the desired matching of the channel estimate time basis to the time basis of the corresponding OFDM symbol to be demodulated.
Note that the cyclic shift operation is distinct from the FFT window positioning update provided by the time tracking algorithm. First, the FFT window position is advanced or retarded according to the output of the time tracking algorithm. Then, after the FFT window position is used to extract the FFT window for the current OFDM symbol, the extracted FFT window is cyclically shifted in order to change the time basis of the current OFDM symbol to the time basis of the first OFDM symbol.
For the next successive OFDM symbol of the received sequence, OFDM symbol 2, the corresponding FFT window position is provided by the time tracking algorithm as an offset (+2 samples in the example of
For the next successive OFDM symbol, OFDM symbol 3, the corresponding FFT window position is provided by the time tracking algorithm as an offset (−3 samples in the example of
The foregoing process may be repeated for every OFDM symbol in the received sequence. Because cyclic shifts that differ by a multiple of the FFT window length are equivalent, some embodiments maintain the accumulated time update value modulo L, where L is the FFT window length.
As mentioned, the cyclic shift simultaneously changes the time bases of both the pilot sub-carriers (used for channel estimation) and data sub-carriers (used for demodulation). The requirement for proper demodulation—equal time basis for the channel estimate and the corresponding OFDM symbol, no mater what that equal time basis may be—is therefore met, the equal time basis being the time basis of OFDM symbol 1. Accordingly, the time basis of the channel estimate matches that of the corresponding OFDM symbol to be demodulated using that channel estimate.
In some OFDM communication systems, the pilots are interpolated in the frequency domain to obtain an estimate of the channel frequency response in the pilot sub-carriers. An estimate of the channel impulse response is obtained from this channel frequency response via inverse FFT (IFFT). The above-described cyclic shifting of samples within the FFT window affects related algorithms implemented by the system. More specifically, the time tracking algorithm, which uses the channel impulse response, is affected, as is the algorithm that interpolates between pilots to obtain the channel frequency response for OFDM symbol demodulation. These affected algorithms may be modified to remove the effects of the cyclic shift. Examples of suitable modifications are described below, wherein the following notation is used:
Examples include
For demodulation, a frequency response resolution of FBin is required. The corresponding period of the impulse response in the time domain is NTchipx1. However, the receiver only has a decimated measurement of the channel frequency response in the pilot tones, which are 3FBin apart. This decimation by 3 in the frequency domain folds the 3 thirds of the impulse response onto each other and reduces the time-domain period to
When a proper OFDM mode is used by the network, the non-zero range of the original impulse response (channel delay spread) is assumed to be shorter than the maximal guard interval whose duration is typically
(e.g. for ISDB-T and DVB-H). Therefore, the decimation above causes no aliasing. However, the
time-domain period of the channel impulse response available to the receiver is affected by the introduction of the FFT window cyclic shift (whose duration is up to NTchipx1). This effect may be taken into account in the manner described below with reference to
a-2c illustrate the case without the cyclic shift.
d-2f show plots respectively corresponding to
One known receiver design, also referred to as receiver A, performs the following steps:
interpolated pilots are zero padded to length of NIFFT, obtaining a frequency sampling interval of 3FBin and a frequency period of 3FBinNIFFT. The zero padded pilots are converted to time domain by an NIFFT-point IFFT, yielding an NIFFT-samples estimate of the channel impulse response. This impulse response estimate has a sampling interval of
and a period of
This is the impulse response in
and increasing its time period to NTchipx1. This results in the desired impulse response in
The interpolation in step A4 above requires a 3NIFFT-point FFT. For pure hardware implementation reasons, it is performed in a mathematically equivalent way which requires three NIFFT-point FFTs as follows. Given an NIFFT-samples impulse response {h(n)}n=0N
The multiplication by the linear phase term prior to FFT, referred to as “phase ramping”, is implemented by hardware in receiver A.
Introducing a cyclic shift to the FFT window leads to a corresponding cyclic shift in the channel impulse response, as shown in
so “shift” in
Accordingly, the cyclic shift introduced to the channel impulse response of step A1 above (shown in
impresp_shift_mod=mod(impresp_shift, NIFFT).
The time tracking algorithm in receiver A may be modified as follows to compensate for the effect of the cyclic shift in the FFT window. First, a counter-cyclic shift of impresp_shift_mod samples to the left is applied to the impulse response of step A1 (
The cyclic shift introduced to the impulse response {h(n)}n=0N
If step A4 above is replaced by the following steps, the desired zero padding according to
This converts fftwin_shift which is sampled at Tchipx1 to the impulse response sampling interval which is
(The rounding quantization error does not affect the interpolation.)
y
m(mod(n+impresp_shift_mod, NIFFT))=h(mod(n+impresp_shift_mod, NIFFT))pm(n)
{H(3k+m)}k=0N
The modifications according to steps MA1-MA5 may be characterized as the addition of a non-zero initial phase to the phase ramping, and the addition of a cyclic addressing mode for reading the impulse response and for writing the input to the FFT. The cyclic addressing mode uses a cyclic addressing offset which can be seen in that, for use in pm and ym above, an address corresponding to “sample n+sample offset amount” (where the sample offset amount is related to the cyclic shift, impresp_shift) is involved, instead of simply the address corresponding to sample n. The same cyclic addressing mechanism may be used to control both addresses.
As indicated above, there is a zero interval between the two non-zero parts of the shifted impulse response (see
Ideally, for steps MA1-MA6 above, the cyclic shift value applied to the current OFDM symbol would not be used for the value of fftwin_shift. Rather, a value equal to the cyclic shift that was applied to the OFDM symbol to be demodulated by the channel estimate would be used. This latter value is equal to the accumulated time update up to the OFDM symbol to be demodulated. However, the difference between the cyclic shift value that was applied to the OFDM symbol to be demodulated, and the cyclic shift value applied to the current OFDM symbol is small (sum of time updates between the OFDM symbol to be demodulated and the current OFDM symbol), so use of the current OFDM cyclic shift value is a good approximation. This is another advantage of the cyclic shift approach over known algorithms such as described in U.S. application Ser. No. 11/777,251: it need not account for the channel estimate delay (number of symbols between the current OFDM symbol and the OFDM symbol to be demodulated by the channel estimate).
Steps MA4 and MA5 suggest using continuous phase terms and cyclic indexing of the impulse response and the FFT input. This is not the only possible implementation. Any mathematically equivalent implementation could be used. Possible examples include:
Another known receiver design, referred to herein as receiver B, performs the following steps:
interpolated pilots are zero padded to length of N. The zeros are inserted between the pilots (two zeros between every two consecutive pilots) such that the pilots are located in their true positions. The sampling interval in the frequency domain is FBin and the period in the frequency domain is NFBin. The zero-padded pilots are converted to time domain by an N-point IFFT, yielding an N-samples estimate of the channel impulse response. This impulse response has time sampling interval of Tchipx1 and a period of NTchipx1. Due to the zero values between the pilots, the effective sampling interval in the frequency domain is 3FBin so the effective period of the impulse response is
This results in an NTchipx1-long impulse response having 3 identical replicas, each
long. This is exactly
Introducing a cyclic shift to the FFT window leads to a corresponding cyclic shift in the channel impulse response, as shown in
The time tracking algorithm in receiver B may be modified as follows to compensate for the effect of the cyclic shift in the FFT window. First, a counter-cyclic shift of fftwin_shift to the left is applied to the one-replica impulse response (produced by the aforementioned zeroing in
The frequency response interpolation in receiver B may be modified to compensate for the effect of the cyclic shift in the FFT window by simply converting the one-replica impulse response (produced by zeroing in
An FFT window extractor 52 uses FFT window position information 500 (produced according to a time tracking algorithm implemented in a timing control unit 59) to extract, for each OFDM symbol in the received sequence, an initial FFT window for the samples of that OFDM symbol. These initial FFT windows are designated generally at 506. A cyclic shifter 53 then cyclically shifts the samples within each of the initial FFT windows 506 as may be required by cyclic shift information 501 provided by the timing control unit 59. As described above, this cyclic shifting translates the time basis of the corresponding OFDM symbol to the time basis of the reference OFDM symbol. An FFT unit 54 performs conventional FFT processing operations with respect to the samples in the FFT windows produced at 507 by the cyclic shifter 53. For each FFT result produced at 504 by the FFT unit 54, a demodulation unit 55 uses corresponding channel estimate information 503, produced by a channel estimator 57, to demodulate the corresponding OFDM symbol according to conventional techniques. The demodulation results 505 are provided to a decoding unit 56 that uses conventional techniques to produce information bits 502 from the demodulation results.
The channel estimate information 503 is also provided to the time tracking algorithm that the timing control unit 59 implements to produce the FFT window position information 500.
In embodiments that modify the channel estimation in the manners described above relative to receivers A and B, the channel estimator 57 receives the cyclic shift information 501, as shown by broken line in
Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present work.
The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use products that embody principles of the present work. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present work is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The present Application for Patent claims priority to Provisional Application No. 61/145,536 filed Jan. 17, 2009, and assigned to the assignee hereof and hereby expressly incorporated by reference herein. The present application is related to the following U.S. patent application Ser. No. 11/777,251 and Ser. No. 11/777,263, both of which are expressly incorporated by reference herein.
Number | Date | Country | |
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61145536 | Jan 2009 | US |