Patent Application
20130083577
The present disclosure relates to offline integrated circuits, more particularly, the present disclosure relates to offline AC-low voltage full-wave rectified DC output integrated bridge circuits.
Sometimes in low power offline applications, rectified output voltage is needed which may be used to power small logic signal, boot/wake-up startup circuits, transponders, sensor circuits, small relays, etc.
However, such circuit 50 needs a transformer to step down the input AC voltage, which highly increases the system volume, weight and cost.
So there is a need to provide a simpler and cost effective integrated circuit (semiconductor approach) of offline AC-low voltage DC rectification.
It is an object of the present disclosure to provide a circuit and a method for constant current regulation of power supplies.
In accomplishing the above and other objects, there has been provided, in accordance with an embodiment of the present disclosure, an offline low voltage DC output circuit, comprising: a first input port and a second input port configured to receive an input AC voltage; an output port configured to provide an output voltage; a first depletion high voltage pass transistor coupled to the first input port to receive the input AC voltage, and based on the input AC voltage, the first depletion high voltage pass transistor provides a first voltage; a second depletion high voltage pass transistor coupled to the second input port to receive the input AC voltage, and based on the input AC voltage, the second depletion high voltage pass transistor provides a second voltage; and a bridge rectifier having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the first depletion high voltage pass transistor to receive the first voltage, the second input terminal is coupled to the second depletion high voltage pass transistor to receive the second voltage, and wherein the output terminal is coupled to the output port.
In addition, there has been provided, in accordance with an embodiment of the present disclosure, an offline low voltage DC output integrated circuit die comprising: a plurality of minority generating devices; a plurality of mergeable NWell; a plurality of unmergeable devices: a first site, and a second site, wherein the first site and the second site are placed on opposite sides of the integrated circuit die; an N-well tub between the first site and the second site; and a die seal; wherein the minority generating devices are placed at the first site and the second site; the devices with mergeable NWell are group together and placed in the N-well tub; and the unmergeable devices are placed next to the die seal or close to an edge of the integrated circuit die.
Furthermore, there has been provided, in accordance with an embodiment of the present disclosure, a method for providing a low voltage DC output from an AC offline source, comprising: receiving an AC input voltage; generating a first voltage in response to the AC input voltage; generating a second voltage in response to the AC input voltage; and generating a low voltage DC output by rectifying the first voltage and the second voltage.
These and other features of the present disclosure will be readily apparent to persons of ordinary skill in the art upon reading the entirety of this disclosure, which includes the accompanying drawings and claims.
a and 9b schematically show a die 400 for an offline low voltage DC output circuit in accordance with an embodiment of the present disclosure.
The use of the same reference label in different drawings indicates the same or like components.
Embodiments of circuits for integrated full bridge rectifiers for offline low voltage DC output are described in detail herein. In the following description, some specific details, such as example circuits for these circuit components, are included to provide a thorough understanding of embodiments of the disclosure. One skilled in relevant art will recognize, however, that the disclosure can be practiced without one or more specific details, or with other methods, components, materials, etc.
The following embodiments and aspects are illustrated in conjunction with circuits and methods that are meant to be exemplary and illustrative. In various embodiments, the above problem has been reduced or eliminated, while other embodiments are directed to other improvements.
The present disclosure relates to integrated circuits and methods of offline AC-low voltage DC rectification. These integrated circuits usually comprise of two depletion high voltage pass transistors and bridge rectifiers, wherein most of the voltage is dropped across the pass transistor devices, so that other components in the circuit could be low voltage devices.
In one embodiment, the first depletion high voltage pass transistor 103 comprises a first depletion high voltage JFET; and the second depletion high voltage pass transistor 104 comprises a second depletion high voltage JFET.
In one embodiment, the bridge rectifier 105 further comprises a fourth terminal 105D coupled to ground.
In one embodiment, the first depletion high voltage pass transistor 103 and the second depletion high voltage pass transistor 104 each has a gate coupled to ground.
In one embodiment, the bridge rectifier comprises four diodes. The diodes may be Schottky diodes, regular PN diodes or base-collector connected bipolar transistors, which is known to one skilled in the art.
Because the first depletion high voltage pass transistor 103 and the second depletion high voltage pass transistor 104 have conductive channels when their gates are connected to ground, when the absolute value of the input AC voltage is lower than the pinch off voltage (VT) of the depletion high voltage pass transistors, the output voltage (VO) follows the input AC voltage; when the absolute value of the input AC voltage is higher than the pinch off voltage (VT) of the depletion high voltage pass transistors, the voltage at the conjunction of the depletion high voltage pass transistor and the bridge rectifier 105 stays at the pinch off voltage (VT) level of the depletion high voltage pass transistors. As a result, the output voltage (VO) stays at the pinch off voltage (VT) of the depletion high voltage pass transistors minus the diode voltage drop (VD), i.e., VO=VT−Vd.
As illustrated herein before in various embodiments of the present disclosure, the gates of the first depletion high voltage pass transistor 103 and the second depletion high voltage pass transistor 104 are connected to ground, i.e., the substrates of the first depletion high voltage pass transistor 103 and the second depletion high voltage pass transistor 104 are connected to ground. In typical applications, the pass transistor gate comprises a P type substrate (P-sub) as bottom gate and a separate P type implant/diffusion as top gate, while the pass transistor channel is an N type well (N-well), which form a PN junction, as illustrated in
The offline AC-low voltage rectified DC output circuit 200 is similar to the offline AC-low voltage rectified DC output circuit 100. Different to the offline AC-low voltage rectified DC output circuit 100 in
The operation of the offline AC-low voltage rectified DC output circuit 200 is described by referring to
The operation of other parts in the offline AC-low voltage rectified DC output circuit 200 is similar to that of the offline AC-low voltage rectified DC output circuit 100.
In one embodiment, the ballast resistor may be a parasitic resistor or a defined resistor, e.g. implant resistor, diffusion resistor, poly silicon resistor, etc. . . . .
In one embodiment, the ballast resistor may be replaced by active circuits such as a charge pump circuit.
In one embodiment, all other circuits are placed in an N-well tub so that the substrate is fully the pass transistor body and not sharing with other devices of other circuits. The negative voltage charge pump applies a reverse bias at the pass transistor p body and N-well channel so that no current flows through.
The operation of other parts in the offline AC-low voltage rectified DC output circuit 300 is similar to that of the offline AC-low voltage rectified DC output circuit 100.
As illustrated hereinbefore, there are two high voltage structures in the offline low voltage DC output circuit 100/200/300, which may be integrated into a chip in one embodiment. As a result, the die area of the offline low voltage DC output circuit 100/200/300 is highly reduced, which further reduces the cost.
The effect of any generated minority carriers may also be alleviated by layout techniques.
In one embodiment, the N-well tub 403 serves as a minority collector. In one embodiment, the minority collector is coupled to a potential reference.
In one embodiment, the minority generating devices comprise a first depletion high voltage pass transistor and a second depletion high voltage pass transistor.
In one embodiment, the potential reference is ground.
In one embodiment, the N-well tub 403 comprises one opening next to the die seal (and/or close to die edge) to surround unmergeable devices, as shown in
In other embodiments, the N-well tub 403 may comprise more than one opening, e.g. 2 openings to surround unmergeable devices if there are too many unmergeable devices, as shown in
As illustrated above, devices with mergeable NWell are placed in the N type well 403, and unmergeable devices are placed next to the die seal 404 (and/or close to die edge 405) surrounded with the minority collector, so the die seal and/or the die edge 405 may take some of the wandering minority carriers and minimize the number of carriers from reaching the sensitive devices.
Step 501, placing minority generating devices at a first site and a second site; wherein the first site and the second site are placed on opposite sides of the integrated circuit die;
Step 502, placing devices with mergeable NWell into an N-Well tub, wherein the N-well tub serves as a minority collector;
Step 503, placing unmergeable devices next to a die seal and/or close to a die edge;
Step 504, placing sensitive devices as far as possible from the first site and the second site; and
Step 505, surrounding unmergeable devices with the minority collector.
In one embodiment, the minority generating devices comprise a first depletion high voltage pass transistor and a second depletion high voltage pass transistor.
In one embodiment, the minority collector comprises NWell tubs. An optional N-type buried layer (NBL) on this NWell tub further enhances the collection area.
In one embodiment, sensitive devices comprise diffusion devices which may be affected by minority carriers.
Step 601, receiving an AC input voltage;
Step 602, generating a first voltage in response to the AC input voltage;
Step 603, generating a second voltage in response to the AC input voltage; and
Step 604, generating a low voltage DC output by rectifying the first voltage and the second voltage.
In one embodiment, in step 602, the first voltage is generated by a first depletion pass transistor; and in step 603, the second voltage is generated by a second depletion pass transistor.
In one embodiment, in step 604, the rectifying is executed by a bridge rectifier.
In one embodiment, both the first depletion pass transistor and the second depletion pass transistor have a gate connected to ground, respectively.
In one embodiment, both the first depletion pass transistor and the second depletion pass transistor have a substrate connected to ground via a ballast resistor, respectively.
In one embodiment, both the first depletion pass transistor and the second depletion pass transistor have a substrate connected to ground via an active circuit.
In one embodiment, the active Circuit comprises a charge pump.
This written description uses examples to disclose the disclosure, including the best mode, and also to enable a person skilled in the art to make and use the disclosure. The patentable scope of the disclosure may include other examples that occur to those skilled in the art.
