FIELD OF THE INVENTION
The present invention is related generally to a switching DC-DC power supply and, more particularly, to a control circuit and method of a switching DC-DC power supply.
BACKGROUND OF THE INVENTION
As shown in FIG. 1, a constant on time switching DC-DC power supply employs a control circuit 10 to provide a control signal Sd to control an output stage 11 to generate a regulated output voltage Vout. The output stage 11 includes a pair of power switches M1 and M2 connected in series, an inductor L and a capacitor C in the manner that the inductor L is connected between the switching node between the power switches M1 and M2 and the capacitor C. In the control circuit 10, a feedback circuit 16 detects the output voltage Vout to generate a feedback signal Vfb, an error comparator 14 compares the feedback signal Vfb with a reference voltage Vref to generate a comparison signal EC, and a control logic circuit 12 triggers the on time of the control signal Sd according to the comparison signal EC. The control logic circuit 12 includes a flip-flop 20 to trigger a signal Vc in response to the comparison signal EC, an on time one shot circuit 18 to trigger a signal Sr according to the signal Vc to reset the flip-flop 20, and a driver 22 to generate the control signal Sd in response to the signal Vc. In the control logic circuit 12, the on time one shot circuit 18 and the flip-flop 20 establish a constant on time trigger for generating the signal Vc that has a constant pulse width for the on time of the control signal Sd. For constant off time switching DC-DC power supply, the constant on time trigger is replaced by a constant off time trigger for generating a constant pulse width for the off time of the control signal for the output stage.
FIG. 2 is a waveform diagram of the switching DC-DC power supply shown in FIG. 1. Referring to FIGS. 1 and 2, when the feedback signal Vfb goes down beyond the reference voltage Vref, as shown at time t1, the comparison signal EC turns to high from low, thereby triggering the signal Vc to turn on the high side power switch M1 to charge the inductor L, and the output voltage Vout acquires energy through the filter composed of the inductor L and the capacitor C. After triggered by the signal Vc, the signal Sr lasts for a constant pulse width time and then terminates to reset the flip-flop 20 to turn off the signal Vc, as shown at time t2, thereby turning on the low side power switch M2 to release the energy of the inductor L. This energy release continues until the feedback signal Vfb goes down beyond the reference voltage Vref again, and then the process enters the next cycle. This is a complete cycle of a constant on time control system.
As compared with the other pulse width modulation (PWM) control circuits, the constant on time control circuit 10 uses the error comparator 14 instead of an error amplifier, thereby advantageously having simpler circuit, requiring no compensation circuit and allowing fast response. Yet, its defect is that the real output voltage Vout may depart from the design value of the output voltage. As shown in FIG. 3, the real output voltage Vout has the waveform 24 and the average Vout(dc) 26 that departs from its design value Vout(set) 28 due to the combined influence of the output ripple Vripple, the offset Voff of the error comparator 14 itself, the response delay Td and the output voltage, output inductance and capacitance of the applied circuit. To solve this problem, conventionally, the offset Voff of the error comparator 14 is adjusted, for example, by adding or subtracting a fixed value to or from the offset Voff of the error comparator 14. However, the output ripple Vripple, the offset Voff and the response delay Td usually vary with the input voltage, output voltage, output inductance, output capacitance, and the slew rate of the input terminal of the applied circuit, causing it difficult to provide adjustment adaptable to all conditions.
Therefore, it is desired a control circuit and method to dynamically adjust the offset of an error comparator of a switching DC-DC power supply depending on real application environments.
SUMMARY OF THE INVENTION
An objective of the present invention is to provide a switching DC-DC power supply.
Another objective of the present invention is to provide a control circuit and method of a switching DC-DC power supply.
A further objective of the present invention is to provide an offset and delay cancellation circuit for dynamically adjusting the offset of an error comparator of a switching DC-DC power supply.
According to the present invention, a control circuit of a switching DC-DC power supply includes a feedback circuit to detect the output voltage of the power supply to generate a feedback signal, an error comparator to compare the feedback signal with a first reference voltage to generate a comparison signal to trigger a control signal for the power supply to regulate the output voltage, and an offset and delay cancellation circuit to generate an offset adjust signal according to the feedback signal and a second reference voltage for adjusting the offset of the error comparator.
According to the present invention, a control method of a switching DC-DC power supply detects the output voltage of the power supply to generate a feedback signal, compares the feedback signal with a first reference voltage by an error comparator to generate a comparison signal for generating a control signal for the power supply to regulate the output voltage, generates an offset adjust signal according to the feedback signal and a second reference voltage, and adjusts the offset of the error comparator according to the offset adjust signal.
According to the present invention, a switching DC-DC power supply includes an output stage to provide an output voltage, a feedback circuit to detect the output voltage to generate a feedback signal, an error comparator to compare the feedback signal with a first reference voltage to generate a comparison signal to generate a control signal to control the output stage, and an offset and delay cancellation circuit to determine an offset adjust signal according to the feedback signal and a second reference voltage for adjusting the offset of the error comparator.
The offset adjust signal is adjusted according to the feedback signal and the second reference voltage, and thus dynamically adjusts the offset of the error comparator depending on the real conditions, thereby pulling the average of the real output voltage toward the design value thereof. Preferably, the offset adjust signal is stored according to the offset calibration signal at appropriate time points to provide appropriate offset adjust signal.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other objectives, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a circuit diagram of a conventional constant on time switching DC-DC power supply;
FIG. 2 is a waveform diagram of the switching DC-DC power supply shown in FIG. 1;
FIG. 3 is a waveform diagram showing the real output voltage of the switching DC-DC power supply shown in FIG. 1 departing from its design value;
FIG. 4 is a circuit diagram of an embodiment according to the present invention;
FIG. 5 is a circuit diagram of a first embodiment for the offset and delay cancellation circuit shown in FIG. 4;
FIG. 6 is a circuit diagram of a second embodiment for the offset and delay cancellation circuit shown in FIG. 4; and
FIG. 7 is a circuit diagram of a third embodiment for the offset and delay cancellation circuit shown in FIG. 4.
DETAILED DESCRIPTION OF THE INVENTION
FIG. 4 is a circuit diagram of an embodiment according to the present invention designed on the basis of the circuit shown in FIG. 1, in which an offset and delay cancellation (ODC) circuit 30 generates an offset adjust signal Voa according to the feedback signal Vfb and a reference voltage Voref to dynamically adjust the offset of the error comparator 14, thereby pulling the average of the output voltage Vout toward its design value. In addition, as is well known, when the power supply enters its sleep mode, the level of the output voltage Vout will depart from its design value because the power switches M1 and M2 are both kept off. In this case, if the ODC circuit 30 still dynamically adjusts the offset of the error comparator 14, the offset of the error comparator 14 will be adjusted upward or downward excessively. Consequently, when the power supply returns to its normal operation from the sleep mode, the error comparator 14 will generate incorrect output voltage Vout due to the excessive adjustment of the offset of the error comparator 14. For preventing this, an offset calibration signal Voc is set to control the ODC circuit 30, thereby make it to calibrate and store an offset adjust signal Voa at appropriate time points.
FIG. 5 is a circuit diagram of a first embodiment for the ODC circuit 30 shown in FIG. 4, which includes an error transconductor 32 and a sample-and-hold circuit 34. The error transconductor 32 generates an error current Igm that may be positive or negative according to the difference between the feedback signal Vfb and the reference voltage Voref. The sample-and-hold circuit 34 samples and holds the error current Igm according to the offset calibration signal Voc to generate the offset adjust signal Voa. The sample-and-hold circuit 34 includes a capacitor Cs and a switch SW connected between the capacitor Cs and the error transconductor 32. When the offset calibration signal Voc turns on the switch SW, the voltage Voa of the capacitor Cs varies with the error current Igm. When the offset calibration signal Voc turns off the switch SW, the capacitor Cs transfers the offset adjust signal Voa it stores to the error comparator 14 for adjusting the offset of the error comparator 14, thereby making the feedback signal Vfb close to the reference voltage Voref. The reference voltage Voref represents the design value of the output voltage Vout, and thus the ODC circuit 30 is capable of pulling the average of the real output voltage Vout toward the design value.
FIG. 6 is a circuit diagram of a second embodiment for the ODC circuit 30 shown in FIG. 4, which includes a digital-to-analog converter (DAC) 36, an up/down counter 38, an AND gate 40 and a comparator 42. The comparator 42 compares the feedback signal Vfb with the reference voltage Voref to generate a comparison signal UD for the up/down counter 38, and the AND gate 40 generates an enable signal EN according to a clock CLK and the offset calibration signal Voc to enable the up/down counter 38. The clock CLK may be an oscillation signal generated inside the power supply. After enabled, the up/down counter 38 determines a count value Scou according to the comparison signal UD. It also stores the count value Scou and transmits the same to the DAC 36 where the count value Scou is converted into the offset adjust signal Voa for the error comparator 14 to adjust its offset, thereby making the feedback signal Vfb close to the reference voltage Voref. The reference voltage Voref represents the design value of the output voltage Vout, and thus the ODC circuit 30 is capable of pulling the average of the real output voltage Vout toward the design value.
FIG. 7 is a circuit diagram of a third embodiment for the ODC circuit 30 shown in FIG. 4, which is similar to the circuit of FIG. 5, but with an error amplifier 44 replacing the error transconductor 32. The error amplifier 44 amplifies the difference between the feedback signal Vfb and the reference voltage Voref to generate an error voltage VEA, and the sample-and-hold circuit 34 samples and holds the error voltage VEA according to the offset calibration signal Voc to generate the offset adjust signal Voa.
While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.
Patent Grant
8791678
