Claims
- 1. A direct current offset correction system for use in an analog signal processing system, said offset correction system comprising:comparator means for comparing polarity of signals from an analog signal channel and producing a binary output signal; digital accumulator means coupled to said comparator output signal and to a first clock signal for providing an accumulated average signal over a predetermined period of time; threshold corrective signal means for determining whether said accumulated signal is within a defined threshold window of acceptable values; and correction means coupled to said threshold corrective signal means for applying a corrective current to said analog signal channel.
- 2. The offset correction system as claimed in claim 1, wherein said threshold corrective signal means is coupled to a second clock signal.
- 3. The offset correction system as claimed in claim 2, wherein said second clock signal is relatively slow compared to said first clock signal.
- 4. The offset correction system as claimed in claim 3, wherein said correction system further includes a divider for receiving said first clock signal and providing said second clock signal.
- 5. The offset correction system as claimed in claim 1, wherein said threshold corrective signal means includes a defined high threshold input digital value and a defined low threshold input digital value.
- 6. The offset correction system as claimed in claim 1, wherein said threshold corrective signal means provides a digital to analog converter output signal.
- 7. A direct current offset correction system for use in an analog signal processing system, said offset correction system comprising:comparator means for comparing polarity of signals from an analog signal channel and producing a comparator binary output signal; accumulator means coupled to said comparator output signal and to a first clock signal for providing an accumulated avenge signal over a predetermined period of time; reset means for resetting the accumulator means; and correction means coupled to said accumulator means for applying a corrective signal to said analog signal channel.
- 8. The offset correction system as claimed in claim 7, wherein said offset correction system further includes threshold corrective signal means for determining whether said accumulated signal is within a defined window of acceptable values.
- 9. The offset correction system as claimed in claim 8, wherein said correction means is coupled to said accumulator means via said threshold corrective signal means.
- 10. The offset correction system as claimed in claim 8, wherein said threshold corrective signal means receives a second clock signal that is relatively stow compared to said first clock signal.
- 11. A direct current offset correction system for use in an analog signal processing system, said offset correction system comprising;comparator means for comparing polarity of signals from an analog signal channel and producing a comparator output signal; accumulator means coupled to said comparator output signal for providing an accumulated average signal over a predetermined period of time responsive to a clock signal from a first clock; threshold corrective signal means coupled to a second clock signal that is relatively slow compared to said fast clock signal, said threshold corrective signal means for determining whether said accumulated signal is within a defined threshold window of acceptable values; and correction means coupled to said threshold corrective signal means for applying a corrective signal to said analog signal channel.
- 12. The offset correction system as claimed in claim 11, wherein said accumulator means is reset responsive to said second clock signal.
- 13. The offset correction system as claimed in claim 11, wherein said first clock signal has a frequency of at least twice a maximum signal bandwidth of the analog channel.
- 14. A method of correcting for direct current offset in an analog signal processing system, said method comprising the steps of:a) receiving analog signals in an analog signal channel b) comparing each of said analog signals with a reference to determine whether a direct current offset exists and producing a comparator output signal; c) providing a first clock signal at a first frequency; d) accumulating a sum of comparator output signals over a predetermined period of time to determine an accumulated value; and e) applying a correction signal to the analog signal channel responsive to whether said accumulated value is outside of a window threshold.
- 15. The method of correcting for direct current offset as claimed in claim 14, wherein said method further includes the step of providing a second clock signal at a second frequency that is lower tan said first frequency.
- 16. The method of correcting for direct current offset as claimed in claim 14, wherein said method further includes the step of resetting an accumulator.
- 17. The method of correcting for direct current offset as claimed in claim 15, wherein said method further includes the step of dividing said first clock signal to provide said second clock signal.
- 18. The method of correcting for direct current offset as claimed in claim 15, wherein said first frequency is at least twice a maximum signal bandwidth of the analog channel.
- 19. The method of correcting for direct current offset as claimed in claim 15, wherein said first frequency is about 10 MHz and said second frequency is about 100 Hz.
- 20. The method of correcting for direct current offset as claimed in claim 15, wherein said method further includes the step of determining whether an average comparator signal is outside of the window threshold responsive to said second clock signal.
- 21. The offset correction system as claimed in claim 1, wherein said correction means includes a plurality of mixer load resistors that are coupled to a power supply and to said analog signal channel.
- 22. The offset correction system as claimed in claim 7, wherein said correction means includes a plurality of mixer load resistors that are coupled to a power supply and to said analog signal channel.
- 23. The offset correction system as claimed in claim 7, wherein said reset means is coupled to a second clock signal.
- 24. The offset correction system as claimed in claim 8, wherein said threshold corrective signal means includes a digital comparator.
- 25. The offset correction system as claimed in claim 8, wherein said threshold corrective signal means includes a digital to analog converter.
- 26. The offset correction system as claimed in claim 11, wherein said threshold corrective signal means includes a digital comparator.
- 27. The offset correction system as claimed in claim 11, wherein said threshold corrective signal means includes a digital to analog converter.
- 28. The offset correction system as claimed in claim 11, wherein said correction means includes a plurality of mixer load resistors that are coupled to a power supply and to said analog signal channel.
Parent Case Info
This application claims priority to U.S. Provisional Patent Application Ser. No. 60/342,223 filed Dec. 20, 2001.
US Referenced Citations (9)
Provisional Applications (1)
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Number |
Date |
Country |
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60/342223 |
Dec 2001 |
US |