Offset correction circuit of encoder

Abstract

An encoder sampling a first phase (A) signal and second phase (B) signal with phases differing from each other by about 90 degrees at the same timing, converting them from an analog to digital format, and detecting an angle signal based on the obtained digital signals, provided with offset detection circuits using a second phase A/D converted value (BD) of when a first phase A/D converted value (AD) is near a first value (XA) to find a second phase (B) offset value (Bofs), using a first phase A/D converted value (AD)of when a second phase A/D converted value (BD) is near a second value (XB) to find a first phase (A) offset value (Aofs), and using the currently found first offset value (Aofs) for the first value (XA) and the currently found second offset value (Bofs) for the second value (XB)when calculating the next first offset value (Aofs) and second offset value (Bofs) and a subtraction circuits using a first offset value (Aofs) and second offset value (Bofs) to correct offsets of the first phase signal and second phase signal, whereby correct offset amounts can be obtained with regard as to the length of the sampling periods or the magnitudes of the offsets.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects and features of the present invention will become clearer from the following description of the preferred embodiments given with reference to the attached drawings, wherein:

FIG. 1 is a schematic block diagram of an offset correction circuit of an encoder described in the applicant's Japanese Patent No. 3026949;

FIG. 2 is a view for explaining an example of an operation for detection of an offset value of the conventional offset detection circuit shown in FIG. 1;

FIG. 3 is a view explaining the problem when the sampling period is small in relation to the input signal period in the conventional offset detection circuit shown in FIG. 1;

FIGS. 4A and 4B are views explaining the case where there is no problem even when the sampling period is small in relation to the input signal period in the conventional offset detection circuit shown in FIG. 1;

FIGS. 5A and 5B are views explaining the problem when there is a problem when the sampling period is small in relation to the input signal period in the conventional offset detection circuit shown in FIG. 1;

FIG. 6 is a schematic block diagram of an offset correction circuit of an encoder according to an embodiment of the present invention; and

FIGS. 7A to 7C are views for explaining the offset detection operation in the state of the times t=0, t=t1, and t=t2.

Claims

1. An offset correction circuit of an encoder sampling a first phase signal and second phase signal with phases differing from each other by about 90 degrees at the same timing, converting them from an analog to digital format, and detecting an angle signal based on the obtained digital signals, comprising: offset detection circuits using a second phase A/D converted value of when a first phase A/D converted value is near a first value to find a second phase offset value, using a first phase A/D converted value of when a second phase A/D converted value is near a second value to find a first phase offset value, and using the currently found first offset value for the first value and the currently found second offset value for the second value when calculating the next first offset value and second offset value; anda correction circuit using a first offset value and second offset value to correct offsets of the first phase signal and second phase signal.

2. An offset correction circuit as set forth in claim 1, wherein said offset detection circuits make the initial values of the first value and the second value zero.

3. An offset correction circuit as set forth in claim 1, wherein said offset detection circuits calculate the average value of the second phase positive A/D converted value and second phase negative A/D converted value when the first phase A/D converted value is within a range set by a threshold value near the first value and detect said average value as a second phase offset value and calculate the average value of the first phase positive A/D converted value and first phase negative A/D converted value when the second phase A/D converted value is within a range set by a threshold value near the second value and detect said average value as a first phase offset value.

4. An offset correction circuit as set forth in claim 3, wherein said offset values are values calculated from a plurality of positive A/D converted values and a plurality of negative A/D converted values.

5. An offset correction circuit as set forth in claim 4, wherein the positive A/D converted value and the negative A/D converted value for finding the average value are alternately updated.

6. An offset correction circuit as set forth in claim 1, wherein the correction circuit is comprised of subtraction circuits for subtracting from one phase A/D converted value one phase offset value found by the offset detection circuit.