BACKGROUND OF THE INVENTION
The present invention relates to an on-chip antenna. More particularly, but not exclusively, the present invention relates to an on-chip antenna comprising a substrate having first and second faces, a metal layer on the second face and a dipole antenna structure on the first face, wherein the on-chip antenna is configured to operate simultaneously in at least one dielectric resonator mode and at least one dipole mode to function as a cavity backed dipole antenna.
The present invention also relates to an on-chip antenna array. More particularly, but not exclusively the present invention relates to an on-chip antenna array comprising: a plurality of on-chip antennae arranged on a common base layer in an n*m array, each substrate being separated from an adjacent substrate by a separator that has a dielectric permittivity lower than that of the substrates.
The present invention also relates to an integrated circuit comprising: at least one of an on-chip antenna and/or an on chip antenna array.
The present invention also relates to a communications device comprising at least one of an on-chip antenna, an on-chip antenna array and an integrated circuit.
On-chip antennae are known. These have the advantage of overall system size reduction and lower cost. They also do not require matching networks. Further, there are no parasitic effects due to wire bonding. On-chip antenna however tend to have low gain and narrow bandwidth.
The present invention seeks to overcome the problems of the prior art.
STATEMENT OF INVENTION
Accordingly, in a first aspect, the present invention provides an on-chip antenna comprising an electrically insulating substrate having first and second faces; a metal layer arranged on the second face; and, a dipole antenna structure arranged on the first face, the dipole antenna structure comprising a dipole antenna and a feed structure connected to the dipole antenna; the on-chip antenna being configured such that when the feed structure is fed with an electrical signal it operates simultaneously in (i) at least one dielectric resonator mode to function as a dielectric resonance antenna, and (ii) at least one dipole mode to function as a cavity backed dipole antenna.
Prior art on-chip antennae suffer from narrow bandwidth and low antenna gain. However, the invention provides a possibility of mitigating these two problems, by the combination of a dipole mode and a dielectric resonator mode. Such an on-chip antenna provides a possibility of overall system size and cost reduction and, it provides a possibility of eliminating matching network and parasitic due to wire bonding when compared to off-chip antennae.
The on-chip antenna according to the invention overcomes these problems simultaneously by use of the dielectric resonator mode and the dipole mode.
Preferably the feed structure comprises a co-planar waveguide. Furthermore, it is also preferable that the coplanar waveguide and dipole antenna are coplanar.
Alternatively the coplanar waveguide and dipole antenna lie in different planes separated by a passivation layer.
Preferably the dipole antenna comprises at least one comb shaped dipole element, the comb shaped dipole element comprising a base and a plurality of substantially parallel fingers extending from the base. Advantageously, use of a comb-shaped dipole element provides a possibility of reducing the cross polarization level.
Preferably the length of the fingers increases towards the center of the base. Also, it is preferable that the base is curved.
Preferably the at least one comb shaped dipole element has a mirror symmetry about a symmetry axis in a plane parallel to the first face.
Preferably the dipole antenna further comprises two comb shaped dipole elements arranged back to back
Preferably the dipole antenna has a mirror symmetry about first and second axes, the second symmetry axis being normal to the first.
Preferably the substrate comprises a silicon layer. Optionally, the substrate further comprises a silicon dioxide layer.
The high permittivity of a silicon substrate, the Si-air interface (or other interface between materials with high contrast of permittivity) is equivalent to a magnetic conducting surface. This provides the possibility that back-scattering energy from the feeding source is restricted and resonates inside the silicon substrate.
Preferably the on-chip antenna further comprises a signal source connected to the feed structure and configured to provide a signal at wavelength λ
Preferably the thickness of the substrate is in the range 0.6λ to 0.8λ. Furthermore, it is preferable that the distance between the dipole antenna and the edge of the substrate is in the range 0.6λ to 0.8λ.
Preferably the substrate and dipole antenna structure are dimensioned for mm wave or THz operations.
Preferably the on-chip antenna further comprises at least one separator arranged in or around the substrate, the separator having a dielectric permittivity lower than that of the substrate.
Preferably the separator is an air gap.
In a further aspect of the invention there is provided an on-chip antenna array comprising:
- a plurality of on-chip antennae, each on chip antenna comprising an electrically insulating substrate having first and second faces; a metal layer arranged on the second face; and, a dipole antenna structure arranged on the first face, the dipole antenna structure comprising a dipole antenna and a feed structure connected to the dipole antenna; the on-chip antenna being configured such that when the feed structure is fed with an electrical signal it operates simultaneously in (i) at least one dielectric resonator mode to function as a dielectric resonance antenna, and (ii) at least one dipole mode to function as a cavity backed dipole antenna; the antennae being arranged on a common base layer in an n*m array where n and m are positive integers; each substrate being separated from the adjacent substrate by a separator having a dielectric permittivity lower than that of the substrate.
Preferably the separator is an air gap.
In a further aspect of the invention there is provided an integrated circuit comprising at least one of an on-chip antenna and an on chip antenna array as described.
In a further aspect of the invention there is provided a communications device comprising at least one of an on chip antenna as described, an on chip antenna array as described and an integrated circuit as described.
DRAWINGS
The present invention will now be described by way of example only and not in any limitative sense with reference to the accompanying drawings in which
FIG. 1 shows a first embodiment of an on-chip antenna according to the invention in vertical cross section;
FIGS. 2(a) and 2(b) show the on-chip antenna of FIG. 1 in perspective view and plan view from above;
FIGS. 3(a) and 3(b) show the dipole antenna structure of an on-chip antenna according to the invention dimensioned to operate at 320 GHz;
FIGS. 4(a) to 4(g) show simulated properties of an on-chip antenna according to the invention adapted to operate at 320 GHz; in particular, FIGS. 4(a) to 4 (g) shows the simulated results of the 320 GHz on-chip antenna. (a) realised gain and S11 versus frequency; (b) input impedance Z11; (c) input admittance Y11; (d) magnitude of E-field distributions on xoy plane at z=−120 micron; (e) magnitude of E-field distributions on xoz plane; (f) magnitude of E-field distributions on yoz plane; and (g) current distributions on the dipole antenna and coplanar waveguide;
FIGS. 5(a) to 5(f) show simulated radiation patterns for the on-chip antenna of FIGS. 4(a) to 4(g);
FIGS. 6(a) and 6(b) show on-chip antenna arrays according to the invention in perspective view;
FIGS. 7(a) to 7(d) show simulated properties for the on-chip antenna arrays of FIGS. 6(a) and 6(b); in particular, FIG. 7(d) shows simulated results on the 320 GHz on chip antenna array. (a) Realised gain and S11 vs frequency for the on-chip antenna array of FIG. 6(a). (b) Radiation patterns at center frequency of the on-chip antenna array of FIG. 6(a). (c) Realised gain and S11 vs frequency for the on-chip antenna array of FIG. 6(b). (d) radiation patterns at center frequency of the on-chip antenna array of FIG. 6(b);
FIGS. 8(a) and 8(b) show the dipole antenna structure of an on-chip antenna according to the invention adapted to operate at 1.1 THz;
FIGS. 9(a) to 9(g) show various properties of the on-chip antenna according to FIGS. 8(a) and 8(b); Simulated results of the 1.1 THz on-chip antenna. (a) Realized gain and |S11| versus frequency; (b) input impedance Z11; (c) input admittance Y11; (d) magnitude of E-field distributions on xoy plane at z=−30 μm; (e) magnitude of E-field distributions on xoz plane; (f) magnitude of E-field distributions on yoz plane; and (g) current distributions on the comb-shaped dipole and the coplanar waveguide; and,
FIGS. 10(a) to 10(i) show the radiation pattern of the on-chip antenna of FIGS. 8(a) and 8(b).
DESCRIPTION OF EMBODIMENTS
Shown in FIG. 1 is a first embodiment of an on-chip antenna 1 according to the invention in vertical cross section. The on-chip antenna 1 is a linearly polarised antenna 1 comprising a substrate 2 which in turn comprises first and second faces 3,4. Arranged on the second face 4 is a metal layer 5. Arranged on the first face 3 is a dipole antenna structure 6. The substrate 2 comprises a silicon layer 7 and a silicon dioxide layer 8 with the dipole antenna structure 6 arranged on the silicon dioxide layer 8 and the metal layer 5 arranged on the silicon layer 7.
The dipole antenna structure 6 comprises a feed structure 9, in this case a coplanar waveguide line 9, formed in a metal layer M9 on the silicon dioxide layer 8. Arranged on layer M9 is passivation layer 10. The dipole antenna structure 6 further comprises a dipole antenna 11 formed in a further metal layer M10 arranged on the passivation layer 10. Arranged on metal layer M10 is a further passivation layer 12. The dipole antenna 11 is connected to the coplanar waveguide line 9 by means of a via extending though the passivation layer 10.
Shown in FIGS. 2(a) and 2(b) is the on-chip antenna 1 of FIG. 1 in perspective view and plan view from above. In use the coplanar waveguide line 9 is typically connected to electronic circuitry such that the electronic circuitry and on-chip antenna 1 together form an integrated circuit. The integrated circuit is typically part of a communications device. For simplicity the coplanar waveguide line 9 is shown in FIGS. 2(a) and 2(b) connected to Ground-Signal-Ground (GSG) pads 13 which are used for testing purposes. When connected to a signal source 14 which provides an electrical signal at wavelength λ the substrate 2 is typically of thickness 0.6-0.8λ, more preferably 0.75λ. Similarly, the separation between the dipole antenna 11 and the edge of the substrate 2 is also around 0.6-0.8λ, more preferably 0.75λ.
The dipole antenna structure 6 is best shown in FIG. 2(b). The coplanar waveguide line 9 of the dipole antenna structure 6 extends along a length axis L. The dipole antenna 11 of the dipole antenna structure 6 comprises first and second dipole elements 15, each connected to the coplanar waveguide line 9. Each dipole element 15 is generally comb shaped comprising a curved base 16 and a plurality of spaced apart fingers 17 extending from the base 16. The fingers 17 extend in a direction generally parallel to the length axis L so as to substantially eliminate currents flowing in a direction orthogonal to the length axis L. This reduces cross polarisation. As can be seen, for each dipole element 15 the length of the fingers 17 increases in a direction towards the center of the base 16. Each dipole element 15 has mirror symmetry about a first symmetry axis S1. The two comb shaped dipole elements 15 are arranged back to back such that the dipole antenna 11 has mirror symmetry about a second symmetry axis S2 normal to the first symmetry axis S1.
The geometrical parameters of a dipole antenna 11 and feed structure 9 of an on-chip antenna 1 according to the invention adapted to operate around 320 GHz are shown in FIGS. 3(a) and 3(b) and table I.
In use the on-chip antenna 1 according to the invention operates in the dielectric resonator mode in which it functions as a dielectric resonance antenna. In this mode the on-chip antenna 1 employs the silicon based substrate 2 as a dielectric resonator which has the dipole antenna 11 as its feeding source. Due to the high permittivity of the silicon based substrate 2 the substrate-air interface is equivalent to a magnetic conducting surface. The back scattering energy from the dipole antenna 11 is therefore restricted and resonates inside the silicon based substrate 2. By appropriate choice of dimensions of the silicon-based substrate 2 and the dipole antenna 11 the on-chip antenna 1 according to the invention can also simultaneously work in a dipole mode where it functions as a cavity backed dipole antenna. As the thickness of the substrate 2 is around 0.75λ the on-chip antenna 1 is optimally designed to work in this way.
The shape of the dipole antenna 11 and dimensions of the silicon based substrate 2 are chosen to excite multi-high-order dielectric resonances. Different dielectric resonances resonating at various adjacent frequencies together with the dipole mode excited by the cavity backed dipole antenna 11 itself lead to simultaneous wide bandwidth and relatively high gain.
As mentioned above, the dipole antenna 11 acts not only as a radiator but also as the feeding source to the substrate 2 which acts as a dielectric resonator. The metal layer 5 on the second face 4 of the substrate 2 functions as the reflector for the comb shaped dipole elements 15 and also as the ground for the resonating substrate 2 in the dielectric resonator mode.
In an alternative embodiment of the invention the coplanar waveguide line 9 and the dipole antenna 11 are coplanar, both being formed in the same metal layer M10.
FIG. 4(a) shows the simulated realised gain and |S11| versus frequency for the on-chip antenna according to the invention dimensioned to operate around 320 GHz of FIGS. 3(a) and 3(b) and table 1. Whilst |S11|<−10 dB spans over the entire band from 260 to 400 GHz, the 3-dB gain bandwidth is 34% from 275 to 385 GHz with a peak gain of 6.2 dBi at 300 GHz. For a gain better than 5 dBi, a bandwidth of 25% from 285 to 370 GHz is achieved.
In order to further explain the radiation mechanism of the on-chip antenna 1 according to the invention simulated input impedance Z11 and input admittance Y11 are shown in FIGS. 4(b) and 4(c). As can be seen, there is one peak at around 320 GHz in the real Y11 curve indicating the series resonance of the dipole mode. Four distinctive peaks can be seen at around 275, 290, 350 and 390 GHz in the real Z11 curve indicating the parallel resonance of the dielectric resonator mode. Different series and parallel resonances in dielectric resonator mode and dipole mode at adjacent frequencies lead to simultaneous wide band and high gain. The magnitude of the electric field distributions on the xoy, xoz and yoz planes and the current distributions on the dipole antenna 11 at 275, 290, 320, 350 and 390 GHz are shown in FIGS. 4(d) to 4(g) respectively. Strong electric field confinements inside the silicon based substrate 2 and strong electric current densities along the edge of the dipole antenna 11 suggest the existence of dielectric resonances and a good coupling condition. Mixed resonances can also been seen in FIGS. 4(d) to 4(f).
FIGS. 5(a) to 5(f) show the simulated radiation patterns for the simulated on-chip antenna 1 of FIGS. 4(a) to 4(g). Radiation patterns from 280 GHz to 380 GHz at 20 GHz intervals are shown. In general the broadside radiation patterns are symmetrical and with low cross polarisation (better than −20 dB).
Shown in FIGS. 6(a) and 6(b) are embodiments of an on-chip antenna array 20 according to the invention. In each case the on-chip antenna array 20 comprises a plurality of on-chip antennae 1 as previously described arranged on a common base layer 21. The substrates 2 of adjacent antennae 1 are separated by a separator 22 having a dielectric permittivity less than of the substrates 2. In this embodiment the separators 22 are air gaps. In general, the antennae 1 are arranged in an n*m array with n and m being positive integers. In FIG. 6(a) the antennae 1 are arranged in a 1*4 array. In FIG. 6(b) the antennae 1 are arranged in a 2*2 array.
For the 1*4 antenna array 20 of FIG. 6(a), FIGS. 7(a) and 7(b) show the simulated peak gain is 11.2 dBi and the 3-dB gain bandwidth is 31% from 275 to 375 GHz. For gain better than 10 dBi a 24% bandwidth is achieved from 286 to 363 GHz. The first side lobe in the H plane is lower than −12 dB. For the 2*2 antenna array 20 of FIG. 6(b) simulated results shown in FIGS. 7(c) and 7(d) show that the peak gain 10 dBi and the 3-dB gain bandwidth is 34% from 268 to 377 GHz. Fora gain better than 10 dBi a 15.6% bandwidth is achieved from 312 to 362 GHz. The first side lobe in the H plane is lower than −10 dB.
The frequency of operation of the on-chip antenna 1 according to the invention depends upon the dimensions of the substrate 2 and the dipole antenna structure 6. In the above embodiments the on-chip antenna 1 is dimensioned to operate in the mm wave range. FIGS. 8(a) and 8(b) show the dipole antenna structure 6 of an on-chip antenna 1 according to the invention dimensioned to operate in the 1.1 THz range. The corresponding dimensions of the coplanar waveguide 9 and dipole antenna 11 of the dipole antenna structure 6 are shown in table II.
Simulated results for the 1.1 THz on-chip antenna 1 according to the invention are shown in FIGS. 9(a)-9(g) and 10(a)-10(i). As can be seen the 3 dB gain bandwidth for the on-chip antenna 1 is around 39% from 0.88 to 1.31 THz with a peak gain of 7.8 dBi at 1.21 THz. The cross polarisation level is better than −16 dB. From the input impedance Z11 and input admittance Y11 shown in FIGS. 9(b) and 9(c) five series resonances in dipole mode and six parallel resonances in dielectric resonator mode can be seen. That is, the skilled reader would appreciate that a dielectric resonator mode can comprise a plurality of resonances (i.e. sub-modes). This embodiment of the on-chip antenna 1 has a larger number of resonances than the on-chip antenna 1 adapted to operate around 320 GHz previously described which further expands the on-chip antenna bandwidth. The magnitude of the electric field distributions on the xoy, xoz and yoz planes, and current distributions on the dipole antenna 11 at 880, 1000, 1150 and 1250 GHz are shown in FIGS. 9(d) to 9(g). From the E field distribution different resonances in the dielectric resonator mode can be seen.
Embodiments of an on-chip antenna 1 and on-chip antenna array 20 operating at 320 GHz and 1.1 THz are described above using TSMC 65 nm CMOS technology. In alternative embodiments the on-chip antenna 1 and on-chip antenna array 20 can be arranged to operate at other frequencies or can be fabricated using other IC fabrication technologies.
While there has been described in the foregoing description preferred embodiments of the present invention, it will be understood by those skilled in the technology concerned that many variations or modifications in details of design, construction or operation may be made without departing from the scope of the present invention as claimed.
Patent Application
20210376482
