This invention relates to Integrated Circuits (ICs or ‘chips’), and particularly but not exclusively to Application Specific Integrated Circuits (ASICs) having on-chip diagnostic arrangements.
In the field of this invention it is known that during the bring-up and test of an ASIC design it is invaluable to be able to monitor internal data buses, address buses and control signals within that design through the use of an on-chip diagnostic or debug port. This port can be connected directly to an external logic analyser or oscilloscope and internal chip signals can be multiplexed onto the port so that a trace can be obtained (the multiplexing is integrated as part of the chip design). However, chip pin assignment priority is necessarily given to functional I/Os (inputs/outputs) and power. Often the number of spare pins left over, that can be assigned to a diagnostic port, is severely limited. Traditional methods of diagnostics output the entire bus onto the diagnostic port. However, if the width of an internal bus exceeds that of the diagnostic port, then it is not possible to monitor the entire bus in a single test run. The internal bus must be divided into segments and several test runs must be performed with a different segment multiplexed onto the diagnostic port each time. For instance, to monitor a 128-bit internal data bus through a 32-bit diagnostic port, four separate test runs are needed to trace the entire bus. In addition to this, it is often useful if the trace of the bus is accompanied by a trace of the control signals that operate on that bus. In order to make room for these control signals the size of the internal bus segment being monitored during a test run must be reduced. This results in more test runs required to obtain a complete trace of the internal bus and its control signals. This extends the time necessary for bring-up.
However, this approach has the disadvantage(s) that if the width of an internal bus exceeds that of the diagnostic port, then it is not possible to monitor the entire bus in a single test run. The internal bus must be divided into segments and several test runs must be pertormed with a different segment multiplexed onto the diagnostic port each time.
A need therefore exists for on-chip diagnostics wherein the above-mentioned disadvantage(s) may be alleviated.
In accordance with a first aspect of the present invention there is provided an arrangement for diagnosis in an integrated circuit having a multi-bit bus and a diagnostic port for monitoring the condition of the bus, the arrangement comprising: logic means having inputs coupled to the bus and an output coupled to the diagnostic port, the logic means being arranged to produce at its output a compressed signal representative of the condition of the bus, the compressed signal having a bit-width less than that of the bus.
Preferably, the logic means comprises a plurality p of logic circuits for each producing a logic value from n/p respective bits on the bus, where n represents the bus bit-width and p represents an integer factor of n.
Preferably, the logic means comprises an Exclusive-OR logic arrangement.
Preferably, the bus comprises a data bus.
Preferably, the integrated circuit comprises an ASIC.
In accordance with a second aspect of the present invention there is provided a method for diagnosis in an integrated circuit having a multi-bit bus and a diagnostic port for monitoring the condition of the bus, the method comprising: receiving bits from the bus and producing therefrom in a logic arrangement a compressed signal representative of the condition of the bus, the compressed signal having a bit-width less than that of the bus, and applying the compressed signal to the diagnostic port.
Preferably, the step of producing the compressed signal comprises producing a plurality p of logic values from n/p respective bits on the bus, where n represents the bus bit-width and p represents an integer factor of n.
Preferably, the logic arrangement comprises an Exclusive-OR logic arrangement.
Preferably, the bus comprises a data bus.
Preferably, the integrated circuit comprises an ASIC.
Briefly stated, the present invention allows an on-chip mechanism to increase the amount of information that can be presented for a given sized diagnostic port. It allows the possibility of monitoring an entire internal bus in fewer test runs whilst at the same time making more of the diagnostic port available for tracing control signals. It can reduce the time needed to determine the cause of a chip-related problem.
One method and arrangement for diagnosis in an integrated circuit incorporating the present invention will now be described, by way of example only, with reference to the accompanying drawing, in which:
Referring now to
In each block 1301 . . . 130p the logic circuitry comprises an Exclusive-OR (XOR) gate (not shown) having n/p inputs coupled to the respective bit lines. Each block 1301 . . . 130p produces a respective single-bit output S1 . . . Sp. As will be explained further below, the p XOR outputs S1 . . . Sp form an ‘XOR signature’, which is applied to respective pins of the diagnostic port 120. Bus control signals generated elsewhere on-chip are applied to other pins of the diagnostic port 120.
Thus, it will be understood that the n-bit data on the bus 110 is compressed into a corresponding p-bit signature, S, which is then passed to the diagnostic port 120. Since p is less than the width of the port, other signals, such as control signals that operate on the bus, can also be presented at the same time.
It is to be noted that more than one data pattern on bus 110 can produce the same XOR signature S. However, it should be borne in mind that the arrangement of
As mentioned above, the conventional approach to monitoring internal buses within a chip is to output the whole bus onto the diagnostic port. This means a bus of width 2q bytes will require 2q+3 bits on the diagnostic port. The XOR signature mechanism described in relation to
(by a factor of
i.e., dependent upon the value of p chosen) so that it fits into a smaller number of bits to allow more room for control signals to be included in the same trace. In addition, bus widths may exceed the width of the diagnostic port, in which case it is impossible to monitor the entire bus using the conventional approach. Instead small segments of the bus must be multiplexed onto the diagnostic port which means that only parts of a bus can be monitored in anyone test run. In order to monitor another part of the bus, another segment must be selected and another test run performed. With the XOR signature mechanism described in relation to
It will be appreciated that various modifications to the compressed signature 25 technique described above will be apparent to a person of ordinary skill in the art. For example, the XOR logic circuitry 1301 . . . 130p could be replaced by another logic block as desired. Alternatively, for example, the compressed signature technique could be applied to monitoring an address bus rather than a data bus.
In conclusion, it will be understood that the compressed signature technique for on-chip diagnosis described above provides the following advantages:
Number | Date | Country | Kind |
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0318487.6 | Aug 2003 | GB | national |