This disclosure is directed to audio inputs, and, more specifically, to a system that compensates a conversion circuit that adjusts a first nominal input voltage to a second nominal input voltage.
Typical audio sources such as from a CD player, audio amplifier, or mixer generally produce line outputs in the 2Vrms range. Modern integrated circuits built with modern low-voltage processes, however, cannot handle the full range of a 2Vrms signal, so the input signal must be reduced. This is typically done by dividing the input signal prior to the input voltage signal being applied to the integrated circuit for sound processing.
It is beneficial to have a fully differential input to take advantage of the common mode rejection. The negative terminal is a low impedance ground sense path. Using an external resistor divider causes a mismatch between the external ground to each input of the signal processing chip, which will introduce noise.
Embodiments of the invention address these and other limitations of the prior art.
Embodiments of the invention are directed to an input compensation system, such as for a preamplifier of a coder-decoder (CODEC), that compensates for noise presented on common mode inputs, such as noise on the ground plane and noise on the common mode reference voltage. Without such compensation, the system has a significant common mode noise component. Much of the noise, however, may be eliminated by using embodiments of the invention, which compensates for mismatch in the feedback gains of the signal path and ground sense path.
It is beneficial to use a fully differential input to take advantage of the common mode rejection. As mentioned above, a 2 Vrms input signal is conventionally divided using a resistor divider, such as illustrated in
In
The resistors in the resistor divider circuit formed by RB1, RB2 are chosen in conjunction with the internal resistor network (RS1, RS2, RF1, RF2) to not disturb the total gain of the signal path. The equivalent resistance of the resistor divider is considered as part of the input resistor when considering the gain, as illustrated in
As illustrated in
Feedback ratios for the signal path and ground sense path can be calculated as follows:
The transfer function from common mode inputs to an output of the operational amplifier 10 as a function of the feedback ratios is defined as:
With no adjustments: (RS1=RS2,RF1=RF2(β1≠β2)), the feedback ratios do not cancel out and a significant signal from the common mode inputs to the output exists:
For better common mode rejection, it is best to match β1=β2 as closely as possible.
RS1=RS
RF1=RF
RS2=RS+RX
RF2=RF
Where RS2 is skewed by the Thevenin equivalent resistance so that the two paths match (RX=RTH). With this shift, β1 and β2 closely match and the common mode signal can be canceled.
Although external resistors generally have 1% precision, on-chip resistors are typically formed of polysilicon and may have up to +/−20% variation in their resistance values. This variation limits the ability to match β1 and β2 as closely as desired. Not being able to closely match the desired resistance values, due to the processing variations in making polysilicon resistors, as set forth above, increases noise from the common mode inputs.
Still with reference to
To compensate for this mismatch, embodiments of the invention skew the internal ground sense path with a fine resistor trim, which is performed within a compensation circuit 120 located within the ground sense path. The compensation circuit 120 may be used to account for the +/−20% variation in polysilicon resistance that occurs when producing the IC. The variation of polysilicon resistance can be determined by an on-chip process monitor, as described in detail below:
The compensation circuit 220 is controlled by a control 225 to vary an amount of resistance between the three nodes 221, 222, and 226. In practice, after measuring a resistance value on the IC, such as, for example, measuring a control polysilicon resistor on the IC, the control 225 may be set to compensate for the variation by adjusting an amount of resistance provided at the three nodes 221, 222, and 226. This has the desired effect, of balancing values such that β1Δ=β2Δ, reducing the noise in the preamplifier 104.
The controllable resistor circuit illustrated in
In operation, using embodiments of the invention as illustrated in
The controllable resistor circuit illustrated in
The resistance RY may be related to the resistance RX described above by the following linear transformation:
In operation, using embodiments of the invention as illustrated in
In the compensation circuit 320 of
The series of controllable switches S0−S2n−1 in
In operation, with reference to
In some embodiments the controller 340 may be set to automatically select a middle value of resistance as a starting point. For example, if the production process yields target polysilicon resistance values, then no further “fine-tuning” control may be necessary for input compensation.
Determining which of the controllable switches S0−S2n−1 to operate in
An additional calibration method includes injecting a supersonic (i.e., >20 KHz) signal into the common mode reference voltage VOCM. If the circuit is matched, i.e., the internal and external resistors are in their proper relationships to one another, without variation from the intended resistance values, then the injected signal is attenuated by the common mode rejection. If, however, there is any mismatch between the gain of the signal path and the gain of the ground sense path, then a residual signal from the injected signal will appear in the output signals VOUT− and VOUT+. Then, the residual signal may be isolated from other signals on the output signals using digital sound processing. Finally, the resistance values of the compensation circuit may be trimmed, using techniques described above, to shift the resistance values between the nodes coupled to the compensation circuit. In particular, the resistance values in the compensation circuit are adjusted until the residual signal in the output signals VOUT− and VOUT+ is minimized. This method of calibration is attractive because, since the tone is supersonic, i.e., above the threshold of human hearing, the calibration may run continuously or periodically in the background and never be heard by the user. Additionally, since the calibration takes place while the pre-amplifier circuit is operational, it does not require an additional setup step to perform the calibration.
Other embodiments may use other methods of controlling the resistance between the nodes 321, 322, 326.
The preamplifier 510 passes the reduced-noise input to an internal component, such as an Analog to Digital Converter (ADC) to convert the analog input signal to a digital audio signal. A sound processor such as a Digital Signal Processor (DSP) 530 may perform varied effects on the digital audio signal, such as noise reduction, equalization, balance, or other enhancements. An output of the DSP 530 may be provided as a digital signal output 532 of the CODEC IC 500.
Depending on the type of CODEC IC 500, outputs from the DSP 530 may also be coupled to Digital to Analog converters 540, 560 to convert the processed signals back to audio analog signals. These signals may be provided to, for example, a headphone amplifier 550 coupled to a headphone jack, or to a PWM processor 570 for providing an amplified output to drive speakers.
Embodiments of the invention may be incorporated into integrated circuits such as sound processing circuits, or other audio circuitry. In turn, the integrated circuits may be used in audio devices such as sound bars, audio docks, amplifiers, speakers, etc.
Having described and illustrated the principles of the invention with reference to illustrated embodiments, it will be recognized that the illustrated embodiments may be modified in arrangement and detail without departing from such principles, and may be combined in any desired manner. And although the foregoing discussion has focused on particular embodiments, other configurations are contemplated.
In particular, even though expressions such as “according to an embodiment of the invention” or the like are used herein, these phrases are meant to generally reference embodiment possibilities, and are not intended to limit the invention to particular embodiment configurations. As used herein, these terms may reference the same or different embodiments that are combinable into other embodiments.
Consequently, in view of the wide variety of permutations to the embodiments described herein, this detailed description and accompanying material is intended to be illustrative only, and should not be taken as limiting the scope of the invention.
This application is a continuation of and claims priority to U.S. Non-Provisional patent application Ser. No. 15/385,717, filed Dec. 20, 2016, entitled ON-CHIP RESISTOR DIVIDER COMPENSATION WITH A 2VRMS INPUT, which is a continuation of and claims priority to U.S. Non-Provisional patent application Ser. No. 14/323,657, filed Jul. 3, 2014, entitled ON-CHIP RESISTOR DIVIDER COMPENSATION WITH A 2VRMS INPUT, which claims benefit of U.S. Provisional Application No. 61/842,867, filed Jul. 3, 2013, entitled ON-CHIP RESISTOR DIVIDER COMPENSATION WITH A 2VRMS INPUT, the disclosures of each of which are hereby incorporated by reference herein.
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Number | Date | Country | |
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20190149105 A1 | May 2019 | US |
Number | Date | Country | |
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61842867 | Jul 2013 | US |
Number | Date | Country | |
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Parent | 15385717 | Dec 2016 | US |
Child | 16159281 | US | |
Parent | 14323657 | Jul 2014 | US |
Child | 15385717 | US |