Patent Application
20240258915
A voltage converter converts and input voltage at one magnitude to an output voltage at a different magnitude, either larger than or less than the magnitude of the input voltage. One type of voltage converter is a switching voltage converter in which a modulator controls the ON and OFF timing of one or more power transistors in a power stage to regulate the output voltage. Some switching converters include slope compensation to help improve the stability of the converter.
In at least one example, a voltage converter includes a power stage, a compensator circuit, and a modulator circuit. The power stage circuit has an input voltage terminal, an output voltage terminal, and a pulse width modulation (PWM) control input. The compensator circuit has a voltage input coupled to the output voltage terminal and has a compensation output. The modulator circuit has a compensation voltage input and a PWM control output. The compensation voltage input is coupled to the compensation output, and the PWM control output is coupled to the PWM control input. The modulator circuit includes a slope compensation ramp generator circuit that is configured to generate a slope compensation voltage ramp having a slope that decreases during at least a portion of a switching cycle.
The same reference numbers or other reference designators are used in the drawings to designate the same or similar (either by function and/or structure) features.
The voltage loop compensator circuit 130 includes a voltage input 132 which is coupled to the voltage output terminal 113. The voltage loop compensator circuit 130 also has a compensation output 131. The voltage loop compensator circuit 130 includes resistors RFB1, RBF2, and R1, capacitors C1 and C2, and a transconductance amplifier 134. Resistors RFB1 and RBF2 are coupled in series between the voltage input 132 and the reference terminal 114. The resistors RFB1 and RBF2 form a voltage divider to produce a feedback voltage FB, which is scaled version of the output voltage VOUT (FB is VOUT×RFB2/(RFB1+RFB2). The transconductance amplifier 134 has a positive (+, non-inverting) input and a negative (−, inverting) input. The negative input is coupled to connection between resistors RFB1 and RFB2 to thereby receive the feedback voltage FB. A reference voltage VREF is coupled to the positive input. Resistors R1 and C1 are coupled in series between the output of the transconductance amplifier 134 and the reference terminal 114. Capacitor C2 is coupled in parallel with the series combination of resistor R1 and capacitor C1. The voltage on the output of the transconductance amplifier 134 is the compensation voltage (COMP), which is provided at the compensation output 131 of the voltage loop compensator circuit 130. The transconductance amplifier 134 amplifies the difference between VREF and FB and thus the COMP signal is an error signal representing the difference between the present level of the output voltage VOUT (via its proxy FB) and VREF.
The modulator circuit 120 has and inputs 120, a compensation voltage input 120b, and PWM control output 120c. The output of amplifier 116 within the power stage circuit 110 is coupled to input 120a, and the output of the transconductance amplifier 134 in the voltage loop compensator circuit 130 is coupled to input 120b. The modulator circuit 120 includes a slope compensation ramp generator circuit 122, a data (D) flip-flop 124, a summer 123, a comparator 126, an inverter 127, and a clock generator 129. The summer 123 has inputs 123a and 123b. The input 120a of the modulator circuit 120 is coupled to the summer's input 123a. Accordingly, the output of amplifier 116, which generates the inductor current sense signal IL_SNS, is coupled to input 123a of the summer 123. The slope compensation ramp generator circuit 122 has an output 122a, which is coupled to the other input 123b of summer 123. The slope compensation ramp generator circuit 122 generates a slope compensation (SC) ramp signal 143 on its output 122a which is provided to the input 123b of summer 123.
The comparator 126 has a positive input, a negative input, and an output. The output of summer 123 is coupled to the negative input of comparator 126. The input 120b of the modulator circuit 120 is coupled to the positive input of the comparator 126. Accordingly, the output of the transconductance amplifier 134, which generates the signal COMP, is coupled to the positive input of comparator 126. The output of comparator 126 is coupled to an input of inverter 127.
In this example, the D flip-flop 124 includes a D input, a clear (CLR) input, a clock input (inverted), and a Q output. The output of inverter 127 is coupled to the CLR input. The clock generator 129 generates a clock signal (CLK) 142 on its output, and the output of the clock generator 129 is coupled to the inverted clock input of the D flip-flop 124 and to a clock input 122b of the slope compensation ramp generator circuit 122. The output of comparator 126 is coupled to the D input of flip-flop 124. The D flip-flop 124 generates the PWM signal 141 on its output 120c.
To help improve the stability of the switching voltage converter 100, the slope compensation ramp generator circuit 122 generates the SC ramp signal 143, which is added to the inductor current sense current signal IL_SNS from amplifier 116 by summer 123 to produce a slope-compensated inductor sense current signal 151. The slope-compensated inductor sense current signal 151 is compared to COMP from the voltage loop compensator circuit 130. Comparator 126 asserts its output signal 128 to a logic high state responsive to COMP being larger than the slope-compensated inductor sense current signal 151. Comparator 126 asserts its output signal 128 to a logic low state responsive to the slope-compensated inductor sense current signal 151 being larger than COMP. The comparator's output signal 128 is logically inverted by inverter 127, and the logical inverse of the comparator's output signal is provided to the CLR input of D flip-flop 124.
Before the start of a switching cycle, the HS transistor will be OFF and thus COMP will be larger than the slope-compensated inductor sense current signal 151, and thus the comparator's output signal 128 will be logic high. Responsive to a falling edge of CLK 142, the D flip-flop causes its Q output to transition to the same logic level as its D input, which is the logic level of the comparator's output signal 128 (logic high). The Q output is thus forced high, and the driver 111 responds by turning ON the HS transistor. With the HS transistor ON, current flows from VIN through the HS transistor and inductor L1 to supply the current to a load (not shown) and to charge capacitor COUT. The current IL through the inductor L1 increases while the HS transistor is ON.
In this example, the modulator 120 implements peak mode current control in which the slope-compensated inductor sense current signal 151 is compared to COMP. The comparator 126 trips (its output signal changes from logic high to low) when the slope-compensated inductor sense current signal 151 reaches COMP. Responsive to a logic low for the comparator's output signal 128 (logic high from inverter 127), the D flip-flop 124 is cleared and forces its Q output to a logic low level thereby causing driver 111 to turn OFF the HS transistor and, after a short dead-time, turn ON the LS transistor.
With the HS transistor ON, the inductor current IL and the inductor current sense signal IL_SNS increase linearly as shown at 210. These ideal waveforms assume the bandwidth of amplifier 116 is infinitely high, and thus the inductor current sense signal IL_SNS is able to track the inductor current IL perfectly, that is, with no delay. The slope-compensated inductor sense current signal 151 is the sum (per summer 123) of the SC ramp signal 143 and the inductor current sense signal IL_SNS. The PWM signal 141 is asserted to the logic high state at rising edge 212 by the falling edge 202 of CLK 142 clocking D flip-flop 124. The D flip-flop 124 forces the PWM signal 141 to the logic state at falling edge 214 in response to comparator 126 asserting its output signal 128 in response to the slope-compensated inductor current sense signal 151 reaching the level of COMP. The comparator's output signal 128 is normally logic high because COMP is normally higher than the slope-compensated inductor current sense signal 151. The comparator 126 forces its output signal 128 logic flow for a small period of time 215 because as soon as the comparator 126 forces its output signal 128 logic low, the driver 111 (implementing a small dead time) turns ON the LS transistor and the inductor current IL, and the inductor current sense signal IL_SNS immediately begins to decrease thereby causing the slope-compensated inductor current sense signal 151 to be smaller than VCOMP. The step down 217 in the slope-compensated inductor current sense signal 151 is equal to the magnitude of the SC ramp signal 143 when the LS transistor turns ON and is due to immediately resetting the slope compensation ramp 143 upon PWM transitioning to logic low in order to prepare the slope compensation ramp for the next clock cycle.
As described above, the switching voltage converter 100 implements peak mode current control based on a comparison of VCOMP to the sum of IL_SNS and the SC ramp signal 143. During the delay period 307 in the example of
Additionally, as a result of IL_SNS having a delay relative to IL due to the limit of the bandwidth of the amplifier 116, when the slope-compensated inductor sense current signal 151 eventually does begin to decrease (point 310 in the waveform), it is possible that the slope-compensated inductor sense current signal 151 will not reach VCOMP until after the next clock pulse 320, as indicated at 325. During the time 330 that the slope-compensated inductor sense current signal 151 is higher than VCOMP, the output signal 128 from comparator 126 is logic low. With the comparator's output signal 128 being logic low, the D flip-flop 124 is cleared thereby causing driver 111 to maintain the HS transistor in the OFF state. The cleared state of D flip-flop 124 is not released until the comparator's output signal becomes logic high at 325, but by that time the falling edge 321 of clock pulse 320 has already occurred and a switching cycle that would otherwise have been initiated by falling edge 321 is skipped. This phenomenon is referred to as “pulse skipping.” Pulse skipping is particularly problematic for narrow PWM pulses.
Further, when the HS transistor turns OFF, the magnitude of the SC ramp signal 143 at that moment (a voltage referred to as VSLOPE) is very small (as indicated at 304) due the fact that ramp started after the propagation delay of the slope compensation ramp generation circuit 122 from the clock's falling edge 302. When the HS transistor turns OFF, the slope-compensated inductor sense current signal 151 experiences a step down in voltage at point 311 by an amount equal VRAMP. Because VSLOPE is very small in this example, the step down in the slope-compensated inductor sense current signal 151 also is very small, further increasing the likelihood that the slope-compensated inductor sense current signal 151 will not be able to fall below VCOMP by the time the next clock pulse 320 occurs.
In the example of
In this example, transistors M41-M43 are NFETs but the transistors can be implemented as other types of transistors. Transistor M43 is coupled between current source circuit I41 and the passive component circuit 420. Turning OFF transistor M43 prevents current I41 from flowing into the passive component circuit 420. Turning ON transistor M43 allows current I41 to flow into the passive component circuit 420. The output of OR gate 412 is coupled to an input of inverter 408, and the output of inverter 408 is coupled to the gate of transistor M43. The output of OR gate 412 also is coupled to the gates of transistors M41 and M42. The example passive component circuit 420 of
The drain of transistor M41 is coupled to the current input and the source of transistor M41 is coupled to the reference terminal 114. Accordingly, transistor M41 is coupled across capacitor C42. The drain and source of transistor M42 are coupled across capacitor C42. When transistor M41 is ON, any charge present capacitor C42 is discharged through transistor M41 to ground. When transistor M42 is ON, any charge present capacitor C41 is discharged through transistor M42 to ground.
The output signal 413 from OR gate 412 is labeled the “switch control” signal. When switch control signal 413 is logic high in this example, transistors M41 and M42 turn ON thereby discharging capacitors C42 and C41, respectively, and transistor M43 turns OFF (due to inverter 408) thereby turning OFF current I41 from flowing into the passive component circuit 420. When switch control signal 413 is logic low, transistors M41 and M42 turn OFF and transistor M43 turns ON. With transistor M43 ON, current I41 flows into the passive component circuit 420. As further described below, the shape of the SC ramp signal 143 generated by the passive component circuit 420 is illustrated at 450. The shape of the SC ramp signal 143 is a slope that, for at least a portion of each switching cycle, decreases over time as current I41 continues to flow into the passive component circuit 420. The slope smoothly decreases over time (e.g., no sharp discontinuities).
Referring still to
At the end of the one-shot pulse 403, input 410b of OR gate 412 becomes logic low thereby turning OFF transistors M41 and M42 and turning ON transistor M43. Further, with one-shot pulse 403 now in a logic low level, the reset input of latch 410 is logic high thereby ceasing the reset state of latch 410. With transistor M43 ON and transistors M41 and M42 OFF, current I41 flows into the passive component circuit 420 and the SC ramp signal 143 ramps up initially with a relatively large slope (and then with a progressively decreasing slope).
When the next falling edge of the PWM signal 141 occurs (which occurs when the HS transistor is to be turned OFF), via inverter 406, the clock input of latch 410 receives a rising signal edge, and the latch 410 responds by clocking the logic high signal on its D input onto its Q output to input 410a of OR gate 412. The OR gate 412 responds by causing switch control signal 413 to be logic high again, which causes transistors M41 and M42 to be ON (discharging capacitors C42 and C41) and transistor M43 to be OFF (turning OFF current I41 to the passive component circuit 420).
As described above, the slope compensation ramp generation circuit 422 causes the capacitors within the passive component circuit 420 (e.g., capacitors C41 and C42) to be discharged twice during each switching cycle. The first time is triggered by the rising edge of the CLK 142 pulse and before the switching cycle (to be initiated by the falling edge of CLK 143) begins. The second time that the capacitors are discharged occurs coincident with the decision point at which the HS transistor is turned OFF. At that point, the modulator circuit 120 uses the slope-compensated inductor sense current signal 151 (e.g., compares the slope-compensated inductor sense current signal 151 to VCOMP) to decide when the HS transistor should be turned OFF. Once that occurs, there is no need to continue using quiescent current to continue generating the SC ramp signal 143, and thus latch 410 and logic gate 412 shuts off current I41 to the passive component circuit 420 and discharges capacitors C41 and C42. Discharging capacitors C41 and C42 as soon as possible after a decision has been made to turn OFF the HS transistor also helps to ensure that the ramp is fully discharged before the start of the next clock cycle.
The output signal 128 of comparator 126 transitions briefly to the logic low level in response to the slope-compensated inductor sense current signal 151 reaching VCOMP (at point 510). When that occurs, the HS transistor is turned OFF, and the slope-compensated inductor sense current signal 151 experiences a step down 511 approximately equal to the voltage magnitude of the SC ramp signal at point 510. The size of the step down voltage 511 is larger in the example of
In this description, the term “couple” may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.
Also, in this description, the recitation “based on” means “based at least in part on.” Therefore, if X is based on Y, then X may be a function of Y and any number of other factors.
A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or reconfigurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof.
As used herein, the terms “terminal”, “node”, “interconnection”, “pin” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device or other electronics or semiconductor component.
A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by an end-user and/or a third-party.
While the use of particular transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuitry. For example, a field effect transistor (“FET”) (such as an n-channel FET (NFET) or a p-channel FET (PFET)), a bipolar junction transistor (BJT—e.g., NPN transistor or PNP transistor), an insulated gate bipolar transistor (IGBT), and/or a junction field effect transistor (JFET) may be used in place of or in conjunction with the devices described herein. The transistors may be depletion mode devices, drain-extended devices, enhancement mode devices, natural transistors or other types of device structure transistors. Furthermore, the devices may be implemented in/over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs).
References may be made in the claims to a transistor's control input and its current terminals. In the context of a FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.
References herein to a FET being “ON” means that the conduction channel of the FET is present and drain current may flow through the FET. References herein to a FET being “OFF” means that the conduction channel is not present so drain current does not flow through the FET. An “OFF” FET, however, may have current flowing through the transistor's body-diode.
Circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.
While certain elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and/or some features illustrated as being internal to the integrated circuit may be incorporated outside of the integrated. As used herein, the term “integrated circuit” means one or more circuits that are: (i) incorporated in/over a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and/or (iv) incorporated in/on the same printed circuit board.
Uses of the phrase “ground” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. In this description, unless otherwise stated, “about,” “approximately” or “substantially” preceding a parameter means being within +/−10 percent of that parameter or, if the parameter is zero, a reasonable range of values around zero.
Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.
This application claims priority to U.S. Provisional Application No. 63/441,639, filed Jan. 27, 2023 entitled “Stable Minimum On-Time Improvement Technique for Current Mode Control Systems,” incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63441639 | Jan 2023 | US |
