Patent Application
20100033463
1. Field of the Invention
The present invention relates to an operational amplifier circuit and a display panel driving apparatus.
2. Description of the Related Art
There is a trend that display panels become larger and larger in size. In the field of television, particularly, liquid crystal display panels even exceeding 100 inches have emerged in the market, and this trend is considered to go on in the future.
One problem with a size increase of display panels is that the power consumption of amplifiers (operational amplifier circuits) included in driver ICs (integrated circuits) increases in conjunction with an increase in the capacity of each data line. In order to reduce the number of driver ICs per display panel, recent display devices tend to be equipped with driver ICs each providing a larger and larger number of outputs, and thereby require higher and higher power consumption per driver IC. This causes a problem that the temperature of the driver IC is raised during its operation.
One of approaches for taking measures against the rise in the temperature of the driver IC is to supply the driver IC with both of a power supply voltage VDD and a power supply voltage VDD/2 which is a half of the power supply voltage VDD, and to operate amplifiers with the power supply voltage VDD/2 if possible. Specifically, the driver IC operates in such a way that an amplifier capable of operating with a voltage in a range of VDD/2 to VDD is driven with a voltage in this range, and that an amplifier capable of operating with a voltage in a range of VSS to VDD/2 is driven with a voltage in this range. This approach makes it possible to reduce the power consumption of the amplifiers. This type of technique has been disclosed in Japanese Patent Application Publication No. Hei. 10-31200.
For the purpose of eliminating a restriction on the input voltage ranges, it is desirable to use an amplifier having a rail-to-rail configuration for each of the positive-side amplifier 101 and the negative-side amplifier 102 shown in
The input stage 111 includes PMOS transistors MP1 to MP8 and NMOS transistors MN1 to MN8. The NMOS transistors MN1 and MN2 are respectively connected to an inverting input terminal In− and a non-inverting input terminal In+, and thus constitute a differential transistor pair. Similarly, the PMOS transistors MP1 and MP2 are respectively connected to the inverting input terminal In− and the non-inverting input terminal In+, and thus constitute another differential transistor pair. The PMOS transistor MP3 has a gate supplied with a bias voltage BP1, and thus operates as a constant current source. Similarly, the NMOS transistor MN3 has a gate supplied with a bias voltage BN1, and thus operates as another constant current source. The gates of the PMOS transistors MP6, MP7 are supplied with a bias voltage BP2, and thus the PMOS transistors MP4 to MP7 operate as a cascode current mirror. Similarly, the gates of the NMOS transistors MN6, MN7 are supplied with a bias voltage BN2, and thus the NMOS transistor MN4 to MN7 operate as another cascode current mirror. The gate of the PMOS transistor MP8 is supplied with a bias voltage BP3, whereas the gate of the NMOS transistor MN8 is supplied with a bias voltage BN3. Thereby, the PMOS transistor MP8 and the NMOS transistor MN8 operate as a floating current source. The thus-configured input stage 111 generates an internal current IIN+ corresponding to the difference between the voltage applied to the inverting input terminal In− and the voltage applied to the non-inverting input terminal In+, and thus outputs the internal current IIN+ to the output stage 112.
The output stage 112 includes PMOS transistors MP9, MP10 and NMOS transistors MN9, MN10. The gate of the PMOS transistor MP9 is supplied with the bias voltage BP3, whereas the gate of the NMOS transistor MN9 is supplied with the bias voltage BN3. Thereby, the PMOS transistor MP9 and the NMOS transistor MN9 operate as another floating current source. The floating current source formed of the PMOS transistor MP9 and the NMOS transistor MN9 play a role of driving nodes N1, N2 at voltage levels corresponding to the internal current IIN+. The gate of the PMOS transistor MP10 is connected to the node N1, whereas the gate of the NMOS transistor MN10 is connected to the node N2. The PMOS transistor MP10 and the NMOS transistor MN10 drive an output terminal Out at the voltage levels of the nodes N1, N2, respectively. Thereby, an output voltage is outputted from the output terminal Out. In a case where the amplifier shown in
When the amplifier shown in
Furthermore, a circuit in which the operational amplifier circuit shown in
However, the use of the amplifier shown in
Against this background, it is desired to provide an operational amplifier circuit capable of operating with less power consumption and lower power supply voltage, and a display panel driving apparatus employing the operational amplifier circuit.
A first aspect of the present invention is an operational amplifier circuit including: an input stage which generates an internal current corresponding to a potential difference between an inverting input terminal and a non-inverting input terminal; and an output stage which drives an output terminal corresponding to the internal current. The output stage includes: a floating current source through which the internal current flows; a first output transistor which drives the output terminal corresponding to a potential of a first terminal of the floating current source; and a second output transistor which drives the output terminal corresponding to a potential of a second terminal of the floating current source. The floating current source includes: a PMOS transistor whose source and drain are respectively connected to the first and second terminals; and an NMOS transistor whose drain and source are respectively connected to the first and second terminals. At least one of the PMOS transistor and the NMOS transistor is a depletion transistor.
The operational amplifier circuit thus configured can reduce a voltage needed to operate the floating current source, and thus carry out its low-voltage operation, by employing a depletion transistor for at least one of the PMOS transistor and the NMOS transistor constituting the floating current source.
The foregoing configuration is effective particularly for the operational amplifier circuit where the input stage operates by receiving a power supply voltage and a ground voltage, and the first output transistor and the second output transistor are connected together between a ground line through which the ground voltage is supplied and a power supply line through which an intermediate power supply voltage that is lower than the power supply voltage and higher than the ground voltage is supplied. The operation of the first and second output transistors by being supplied with the intermediate power supply voltage and the ground voltage is effective in reducing the power consumption of the operational amplifier circuit, whereas this operation makes it difficult to operate the floating current source. However, such a problem can be solved by the use of the depletion transistor as the PMOS transistor in the floating current source.
The foregoing configuration is also effective for the operational amplifier circuit in which the first and second output transistors are connected together between a power supply line through which the power supply voltage is supplied and the power supply line through which the intermediate power supply voltage is supplied. The operation of the first and second output transistors by being supplied with the power supply voltage and the intermediate power supply voltage is effective in reducing the power consumption of the operational amplifier circuit, whereas this operation makes it difficult to operate the floating current source. However, such a problem can be solved by the use of the depletion transistor as the NMOS transistor in the floating current source.
Another aspect of the present invention is a display panel driving apparatus for generating a driving voltage for driving a display panel. The apparatus includes: a positive-side amplifier which generates a first driving voltage in a range between a power supply voltage and an intermediate power supply voltage that is a half of the power supply voltage; and a negative-side amplifier which generates a second driving voltage in a range between a ground voltage and the intermediate power supply voltage. Each of the positive-side amplifier and the negative-side amplifier includes: an input stage which generates an internal current corresponding to a potential difference between an input terminal and an output terminal; and an output stage which outputs the first or second driving voltage from the output terminal corresponding to the internal current. The output stage includes: a floating current source through which the internal current flows; a first output transistor which drives the output terminal corresponding to a potential of a first terminal of the floating current source; and a second output transistor which drives the output terminal corresponding to a potential of a second terminal of the floating current source. The floating current source includes: a PMOS transistor whose source and drain are respectively connected to the first and second terminals; and an NMOS transistor whose drain and source are respectively connected to the first and second terminals. Both the PMOS transistor in the floating current source in the output stage of the positive-side amplifier and the NMOS transistor in the floating current source in the output stage of the negative-side amplifier are depletion transistors.
Yet another aspect of the present invention is a display panel driving apparatus for generating a driving voltage for driving a display panel. The apparatus includes: a grayscale voltage supplying circuit which supplies multiple grayscale voltages; a D/A converter which selects one of the multiple grayscale voltages depending on image data; and an amplifier which generates a driving voltage corresponding to the selected grayscale voltage. The grayscale voltage supplying circuit includes: a positive-side γ amplifier which generates a positive-side bias voltage in a range between a power supply voltage and an intermediate power supply voltage that is a half of the power supply voltage; a negative-side γ amplifier which generates a negative-side bias voltage in a range between the intermediate power supply voltage and a ground voltage; and a ladder resistor which generates the grayscale voltages through voltage division upon receipt of the positive-side bias voltage and the negative-side bias voltage. Each of the positive-side γ amplifier and the negative-side γ amplifier includes: an input stage which generates an internal current corresponding to a potential difference between an input terminal and an output terminal; and an output stage which outputs the positive-side bias voltage or the negative-side bias voltage from the output terminal in response to the internal current. The output stage includes: a floating current source through which the internal current flows; a first output transistor which drives the output terminal corresponding to a potential of a first terminal of the floating current source; and a second output transistor which drives the output terminal corresponding to a potential of a second terminal of the floating current source. The floating current source includes: a PMOS transistor whose source and drain are respectively connected to the first and second terminals; an NMOS transistor whose drain and source are respectively connected to the first and second terminals. Both the PMOS transistor in the floating current source in the output stage of the positive-side γ amplifier and the NMOS transistor in the floating current source in the output stage of the negative-side γ amplifier are depletion transistors.
The present invention provides an operational amplifier circuit and a display panel driving apparatus which are capable of operating with less power consumption and lower voltage.
The input stage 11 is a circuit part for generating an internal current IIn+ corresponding to a potential difference between an inverting input terminal In− and a non-inverting input terminal In+, and for supplying the internal current IIn+ to the output stage. The input stage 11 includes PMOS transistors MP1 to MP8 and NMOS transistors MN1 to MN8.
The gates of the NMOS transistors MN1, MN2 are connected to the inverting input terminal In− and the non-inverting input terminal In+, respectively. The sources of the NMOS transistors MN1, MN2 are commonly connected together. Thereby, the NMOS transistors MN1, MN2 constitute a differential transistor pair. The sources of the NMOS transistors MN1, MN2 are connected to the drain of the NMOS transistor MN3. A bias voltage BN1 is supplied to the gate of the NMOS transistor MN3. Thus, the NMOS transistor MN3 operates as a constant current source for supplying a constant current to the differential transistor pair formed of the NMOS transistors MN1, MN2. The source of the NMOS transistor MN3 is connected to a ground line 13 through which a ground voltage VSS is supplied.
Similarly, the gates of the PMOS transistors MP1, MP2 are connected to the inverting input terminal In− and the non-inverting input terminal In+, respectively. The sources of the PMOS transistors MP1, MP2 are commonly connected together. Thereby, the PMOS transistors MP1, MP2 constitute the other differential transistor pair. The sources of the PMOS transistors MP1, MP2 are connected to the drain of the PMOS transistor MP3. A bias voltage BP1 is supplied to the gate of the PMOS transistor MP3. Thus, the PMOS transistor MP3 operates as a constant current source for supplying a constant current to the differential transistor pair formed of the PMOS transistors MP1, MP2. The source of the PMOS transistor MP3 is connected to a power supply line 14 through which a power supply voltage VDD is supplied.
The PMOS transistors MP4 to MP8 and the NMOS transistors MN4 to MN8 operate as an adding circuit for generating the internal current IIN+ and an internal current IIN−. The internal current IIN+ corresponds to the sum of currents flowing through the NMOS transistor MN2 and the PMOS transistor MP2 of their respective differential transistor pairs, whereas the internal current IIN− corresponds to the sum of currents flowing through the NMOS transistor MN1 and the PMOS transistor MP1 of their respective differential transistor pairs.
Specifically, the PMOS transistors MP4 to MP7 constitute a current mirror (concretely, a cascode current mirror). The sources of the PMOS transistors MP4 , MP5 are connected to a power supply line 15. The drains of the PMOS transistors MP4 , MP5 are connected to the sources of the PMOS transistors MP6, MP7, respectively. Further, the drains of the PMOS transistors MP4 , MP5 are respectively connected to the drains of the NMOS transistors MN1, MN2 constituting the former differential transistor pair. The gates of the PMOS transistors MP4 , MP5 are commonly connected together, and are further connected to the drain of the PMOS transistor MP6. The gates of the PMOS transistors MP6, MP7 are commonly connected together. A bias voltage BP2 for operating the current mirror is supplied to the gates of the PMOS transistors MP6, MP7.
Similarly, the NMOS transistors MN4 to MN7 constitute the other current mirror (concretely, a cascode current mirror). The sources of the NMOS transistors MN4 , MN5 are connected to a ground line 16. The drains of the NMOS transistors MN4 , MN5 are connected to the sources of the NMOS transistors MN6, MN7, respectively. Further, the drains of the NMOS transistors MN4 , MN5 are respectively connected to the drains of the PMOS transistors MP1, MP2 constituting the latter differential transistor pair. The gates of the NMOS transistors MN4 , MN5 are commonly connected together, and are further connected to the drain of the NMOS transistor MN6. The gates of the NMOS transistors MN6, MN7 are commonly connected together. A bias voltage BN2 for operating the current mirror is supplied to the gates of the NMOS transistors MN6, MN7.
The source and drain of the PMOS transistor. MP8 are respectively connected to the drain and source of the NMOS transistor MP8. Thereby, the PMOS transistor MP8 and the NMOS transistor MN8 operate as a “floating current source.” One end of a current source formed of general transistors is connected to a power supply terminal or a ground terminal. On the contrary, the two ends of this floating current source are floating, and can be accordingly connected to any places, respectively. A current feedback whose gain is “1” is locally applied to connection nodes between the PMOS transistor MP8 and the NMOS transistor MN8. Because of this feedback effect, a common connection node between the source of the PMOS transistor MP8 and the drain of the NMOS transistor MN8 as well as a common connection node between the drain of the PMOS transistor MP8 and the source of the NMOS transistor MN8 have a high impedance. From this, too, it is understood that the PMOS transistor MP8 and the NMOS transistor MN8 constitute the floating current source. The floating current source formed of the PMOS transistor MP8 and the NMOS transistor MN8 is connected between the drain of the PMOS transistor MP6 and the drain of the NMOS transistor MN6. Bias voltages BP3L, BN3L for operating the floating current source are supplied to the gates of the PMOS transistor MP8 and the NMOS transistor MN8, respectively.
Internal currents IIN+, IIN− are generated by the two current mirrors and the floating current source. The internal current IIN+ thus generated is supplied to the output stage 12A. The sum of the current flowing through the NMOS transistor MN2 and the current flowing through the PMOS transistor MP2 corresponds to the potential difference between the inverting input terminal In− and the non-inverting input terminal In+. As a result, generated is the internal current IIN+ corresponding to the potential difference between the inverting input terminal In− and the non-inverting input terminal In+.
In this embodiment, the input stage 11 is configured to operate by receiving the power supply voltage VDD and the ground voltage VSS. Because the input stage has a rail-to-rail configuration, the range of a voltage inputted to the input stage 11 is not lower than the ground voltage VSS and not higher than the power supply voltage VDD.
The output stage 12A is a circuit part for driving an output terminal Out in response to the internal current IIN+ supplied from the input stage 11. The output stage 12A includes PMOS transistors MP9, MP10, NMOS transistors MN9, MN10, and capacitors C1, C2.
The source and drain of the PMOS transistor MP9 are connected to the drain and source of the NMOS transistor MN9, respectively. Thereby, the PMOS transistor MP9 and the NMOS transistor MN9 operate as a “floating current source” as described above. The floating current source formed of the PMOS transistor MP9 and the NMOS transistor MN9 is connected between the drain of the PMOS transistor MP7 and the drain of the NMOS transistor MN7. Bias voltages BP3R, BN3R for operating the floating current source are supplied to the gates of the PMOS transistor MP9 and the NMOS transistor MN9, respectively.
In this embodiment, a depletion transistor is used as the NMOS transistor MN9. This is one of the characteristics of the amplifier circuit 1A according to this embodiment. In this embodiment, a non-doped NMOS transistor is used as the depletion transistor. The non-doped NMOS transistor is an NMOS transistor which, as shown in
See
Note that the output stage 12A is designed to operate by receiving the power supply voltage VDD and the intermediate power supply voltage VMH (which is higher than the ground voltage VSS). As described later, the operation of the output stage 12A by receiving the power supply voltage VDD and the intermediate power supply voltage VMH is important in reducing the power consumption.
In the circuit shown in
The bias circuit 2A is a circuit for supplying the bias voltages. BP1, BP2, BP3R, BP3L, BN1, BN2, BN3R, BN3L to the amplifier circuit 1A. The bias circuit 2A includes PMOS transistors MP11 to MP16, NMOS transistors MN11 to MN16 and current sources 21 to 28. Each of the PMOS transistors MP11 to MP16 and the NMOS transistors MN11 to MN16 is diode-connected. The PMOS transistors MP11, MP12 and the current source 21 are a circuit part for generating the bias voltage BP3R. The PMOS transistors MP13, MP14 and the current source 22 are a circuit part for generating the bias voltage BP3L. The PMOS transistor MP15 and the current source 23 are a circuit part for generating the bias voltage BP2. The PMOS transistor MP16 and the current source 24 are a circuit part for generating the bias voltage BP1. In addition, the NMOS transistors MN11, MN12 and the current source 25 are a circuit part for generating the bias voltage BN3R. The NMOS transistors MN13, MN14 and the current source 26 are a circuit part for generating the bias voltage BN3L. The NMOS transistor MN15 and the current source 27 are a circuit part for generating the bias voltage BN2. The NMOS transistor MN16 and the current source 28 are a circuit part for generating the bias voltage BN1.
In the bias circuit 2A, the circuit part for generating the bias voltage BN3R is configured to operate by receiving the power supply voltage VDD and the intermediate power supply voltage VMH (which is higher than the ground voltage VSS). Specifically, the NMOS transistors MN11, MN12 and the current source 25 are connected between a power supply line 18A through which the intermediate power supply voltage VMH is supplied and a power supply line 19 through which the power supply voltage VDD is supplied. The drain of the NMOS transistor MN11 is connected to the gate of the NMOS transistor MN11, and the drain of the NMOS transistor MN12 is connected to the gate of the NMOS transistor MN12. The bias voltage BN3R is outputted from the gate of the NMOS transistor MN11. As described later, the operation of the NMOS transistors MN11, MN12 and the current source 25 by receiving the power supply voltage VDD and the intermediate power supply voltage VMH (which is higher than the ground voltage VSS) is important in reducing the power consumption.
In this embodiment, a depletion transistor is used as the NMOS transistor MN11. As described later, this is important for allowing the NMOS transistors MN11, MN12 and the current source 25 to operate with the power supply voltage VDD and the intermediate power supply voltage VMH.
One of the characteristics of the operational amplifier circuit 10A shown in
When the output stage 12A is operated with the power supply voltage VDD and the intermediate power supply voltage VMH, a voltage outputted from the output stage 12A is limited to a range of VMH+0.2V to VDD−0.2V. However, this limitation does not matter to some applications. For example, in a case where the operational amplifier circuit shown in
A problem with the operation of the output stage 12A with the power supply voltage VDD and the intermediate power supply voltage VMH is difficulty in ensuring a voltage large enough to operate the floating current source (formed of the PMOS transistor MP9 and the NMOS transistor MN9) in the output stage 12A. This problem becomes more serious when the power supply voltage VDD is reduced.
The amplifier circuit 1A according to this embodiment uses a depletion transistor as the NMOS transistor MN9 for the purpose of dealing with the problem with the voltage for operating the floating current source. This use makes it possible to operate the amplifier circuit 1A with a low voltage. The following section will discuss the effectiveness of the use of the depletion transistor as the NMOS transistor MN9.
While the operational amplifier circuit 10A shown in
V
BN3R
=V
GS(MN10)
+V
GS(MN9) Formula (1)
where VGS(MN10) denotes the voltage between the gate and source of the NMOS transistor MN10, and VGS(MN9) denotes the voltage between the gate and source of the NMOS transistor MN9.
For the purpose of operating the operational amplifier circuit 10A shown in
V
MH
+V
BN3R
+V
DS(sat)
<V
DD Formula (2)
V
BN3R<(VDD−VMH)−VDS(sat) Formula (2′)
is obtained.
Here, a voltage VGS between the gate and source of a MOS transistor is generally expressed with the following formula:
where W denotes the gate width; L, the gate length; μ, a mobility; C0, a capacitance of a gate oxide film per unit area; VTO, a threshold voltage to be applied when a voltage between the back gate and source is 0V; VB, a voltage between the back gate and source; ε0, the dielectric constant of a free space (8.86×10−12 F/cm); εs, the relative permittivity of a semiconductor (3.9); q, the amount of charge of an electron (1.6×10−12 C); to, the thickness of the gate oxide film; and NA, an acceptor density. γ varies depending on the process of manufacturing the MOS transistor. An average value of γ is approximately 0.5.
Here, the threshold voltage of the NMOS transistor MN9 is voltage, because the NMOS transistor MN9 is a depletion transistor. Specifically, for the NMOS transistor MN9, the value representing the second term of Formula (3) is negative. Consequently, in this embodiment, the voltage VGS(MN9) between the gate and source of the NMOS transistor MN9 is reduced. This makes it possible to satisfy the condition expressed with Formula (2′) even if the power supply voltage VDD becomes lower. In other words, this embodiment enables the operational amplifier circuit 10A to carry out its low-voltage operation.
Another characteristic of the operational amplifier circuit 10A shown in
Here, the foregoing discussion is the case with the NMOS transistors MN11, MN12 as well. In other words, when the power supply voltage VDD becomes lower, it becomes difficult to operate the NMOS transistors MN11, MN12 and the current source 25. For this reason, Formula (5) as follows needs to be satisfied for operating the NMOS transistors MN11, MN12 and the current source 25:
V
GS(MN11)
+V
GS(MN12)
+V
DS(sat)
+V
MH
<V
DD Formula (5)
where VGS(MN11) denotes the voltage between the gate and source of the NMOS transistor MN11, and VGS(MN12) denotes the voltage between the gate and source of the NMOS transistor MN12.
In this embodiment, the value representing the second term of Formula (3) for the NMOS transistor MN11 is negative, because the depletion transistor is used as the NMOS transistor MN11. Consequently, the voltage VGS(MN11) between the gate and source of the NMOS transistor MN11 is reduced. This makes it possible to satisfy Formula (5) even if the power supply voltage VDD becomes lower (that is, even while the operational amplifier circuit 10A is operating with a lower voltage). In other words, this embodiment enables the operational amplifier circuit 10A to carry out its low-voltage operation.
As described above, the operational amplifier circuit 10A of this embodiment can reduce its power consumption by causing the output stage 12A to operate by receiving the power supply voltage VDD and the intermediate power supply voltage VMH (which is higher than the ground VSS). In addition, the operational amplifier circuit 10A of this embodiment realizes its low voltage operation by employing the depletion transistor as the NMOS transistor MN9 in the floating current source of the output stage 12A. Furthermore, the operational amplifier circuit 10A of this embodiment realizes its low-voltage operation by employing another depletion transistor as the NMOS transistor MN11 used to generate the bias voltage BN3R.
The configuration of the operational amplifier circuit 10A shown in
One of approaches for dealing with the occurrence of the offset voltage is to add an offset cancellation circuit to the amplifier circuit 1A.
In the amplifier circuit 1A shown in
Similarly, a switch SW3 is inserted between the drain of the NMOS transistor MN4 and the sources of the NMOS transistors MN6, MN7, as well as a switch SW4 is inserted between the drain of the NMOS transistor MN5 and the sources of the NMOS transistors MN6, MN7. The switches SW3, SW4 are make/break switches as well. The common terminal of the switch SW3 is connected to the drain of the NMOS transistor MN4, the make terminal of the switch SW3 is connected to the source of the NMOS transistor MN7, and the break terminal of the switch SW3 is connected to the source of the NMOS transistor MN6. On the other hand, the common terminal of the switch SW4 is connected to the drain of the NMOS transistor MN5, the make terminal of the switch SW4 is connected to the source of the NMOS transistor MN6, and the break terminal of the switch SW4 is connected to the source of the NMOS transistor MN7.
Furthermore, a switch SW5 is inserted between the non-inverting input terminal In+ and the two differential transistor pairs (i.e., the paired NMOS transistors MN1, MN2 and the paired PMOS transistors MP1, MP2) of the input stage 11, whereas a switch SW6 is inserted between the inverting input terminal In− and the two differential transistor pairs of the input stage 11. The switches SW5, SW6 are make/break switches as well. The common terminal of the switch SW5 is connected to the non-inverting input terminal In+, the make terminal of the switch SW5 is connected to the gates of the NMOS transistor MN1 and the PMOS transistor MP1, and the break terminal of the switch SW5 is connected to the gates of the NMOS transistor MN2 and the PMOS transistor MP2. On the other hand, the common terminal of the switch SW6 is connected to the inverting input terminal In−, the make terminal of the switch SW6 is connected to the gates of the NMOS transistor MN2 and the PMOS transistor MP2, and the break terminal of the switch SW6 is connected to the gates of the NMOS transistor MN1 and the PMOS transistor MP1.
All the switches SW1 to SW6 operate in linkage with one another. Possible conditions of the amplifier circuit 1A are the following two conditions. In a first condition (hereinafter referred to as a “make condition”), the common and make terminals of each of the switches SW1 to SW6 are connected together. In a second condition (hereinafter referred to as a “break condition”), the common and break terminals of each of the switches SW1 to SW6 are connected together.
The switches SW1 to SW6 shown in
V
O
=V
IN
±V
OS Formula (6)
where VOS denotes the offset voltage which occurs due to the four factors, and VIN denotes an input voltage inputted into the non-inverting input terminal In+. When the amplifier circuit 1A is put in one of the make condition and the break condition, “+” is selected from the plus-minus sign “±.” When the amplifier circuit 1A is put in the other condition, “−” is selected therefrom. Thereby, the voltage VO coincides with the voltage VIN in a time-averaged manner by changing the switches SW1 to SW6 between the two conditions at appropriate intervals together. Thus, the problem with the offset voltage is solved.
For example, in a case where the amplifier circuit 1A shown in
In the operational amplifier circuit 10B shown in
A problem with the operation of the output stage 12B with the intermediate power supply voltage VML lower than the power supply voltage VDD is difficulty in ensuring a voltage large enough to operate the floating current source (formed of the PMOS transistor MP9 and the NMOS transistor MN9) in the output stage 12B. The amplifier circuit 1B according to this embodiment avoids this problem by connecting the back gate of the PMOS transistor MP9 to the source thereof.
While the operational amplifier circuit 10B shown in
V
BP3R
=V
GS(MP10)
+V
GS(MP9) Formula (7)
where VGS(MP10) denotes the voltage between the gate and source of the PMOS transistor MP10, and VGS(MP9) denotes the voltage between the gate and source of the PMOS transistor MP9.
For the purpose of operating the operational amplifier circuit 10B shown in
V
BP3R
+V
DS(sat)
<V
ML Formula (8)
V
BP3R
<V
ML
−V
DS(sat) Formula (8′)
is obtained.
Here, for the PMOS transistor MP9, the value representing the second term of Formula (3) is negative, because the depletion transistor is used as the PMOS transistor MP9. Consequently, the voltage VGS(MP9) between the gate and source of the PMOS transistor MP9 is reduced. This makes it possible to satisfy the condition expressed with Formula (8′) even if the intermediate power supply voltage VML becomes lower in conjunction with the reduction in the power supply voltage VDD. In other words, this embodiment enables the operational amplifier circuit 10B to carry out its low-voltage operation.
Furthermore, the operational amplifier circuit 10B shown in
Here, the foregoing discussion is the case with the PMOS transistors MP11, MP12 as well. Specifically, if the intermediate power supply voltage VML becomes lower in conjunction with the reduction in the power supply voltage VDD, it is difficult to operate the PMOS transistors MP11, MP12 and the current source 21. For this reason, for the purpose of operating the PMOS transistors MP11, MP12 and the current source 21, the following formula (9) needs to be satisfied:
V
GS(MP11)
+V
GS(MP12)
+V
DS(sat)
<V
ML Formula (9)
where VGS(MP11) denotes the voltage between the gate and source of the PMOS transistor MP11, and VGS(MP12) denotes the voltage between the gate and source of the PMOS transistor MP12.
In this embodiment, the value representing the second term of Formula (3) for the PMOS transistor MP11 is negative, because the depletion transistor is used as the PMOS transistor MP11. Consequently, the voltage VGS(MP11) between the gate and source of the PMOS transistor MP11 is reduced. This makes it possible to satisfy the condition expressed with Formula (9) even if the intermediate power supply voltage VML becomes lower in conjunction with the reduction in the power supply voltage VDD (that is, even while the operational amplifier circuit 10B is operating with a lower voltage). In other words, this embodiment enables the operational amplifier circuit 10B to carry out its low-voltage operation.
As described above, the operational amplifier circuit 10B of this embodiment can reduce its power consumption by causing the output stage 12B to operate by receiving the ground voltage Vss and the intermediate power supply voltage VML (which is lower than the power supply voltage VDD). In addition, the operational amplifier circuit 10B of this embodiment realizes its low-voltage operation by employing the depletion transistor as the PMOS transistor MP9 in the floating current source of the output stage 12B. Furthermore, the operational amplifier circuit 10B of this embodiment realizes its low-voltage operation because this embodiment connects the back gate of the PMOS transistor MP11, which is used to generate the bias voltage BP3R, to the source thereof.
The configuration of the operational amplifier circuit 10B shown in
The configuration of the amplifier circuit 1B shown in
Specifically, the switch SW1 is inserted between the drain of the PMOS transistor MP4 and the sources of the PMOS transistors of MP6, MP7, as well as the switch SW2 is inserted between the drain of the PMOS transistor MP5 and the sources of the PMOS transistors MP6, MP7. The common terminal of the switch SW1 is connected to the drain of the PMOS transistor MP4, the make terminal of the switch SW1 is connected to the source of the PMOS transistor MP7, and the break terminal of the switch SW1 is connected to the source of the PMOS transistor MP6. On the other hand, the common terminal of the switch SW2 is connected to the drain of the PMOS transistor MP5, the make terminal of the switch SW2 is connected to the source of the PMOS transistor MP6, and the break terminal of the switch SW2 is connected to the source of the PMOS transistor MP7.
Similarly, the switch SW3 is inserted between the drain of the NMOS transistor MN4 and the sources of the NMOS transistors MN6, MN7, as well as the switch SW4 is inserted between the drain of the NMOS transistor MN5 and the sources of the NMOS transistors MN6, MN7. The common terminal of the switch SW3 is connected to the drain of the NMOS transistor MN4, the make terminal of the switch SW3 is connected to the source of the NMOS transistor MN7, and the break terminal of the switch SW3 is connected to the source of the NMOS transistor MN6. On the other hand, the common terminal of the switch SW4 is connected to the drain of the NMOS transistor MN5, the make terminal of the switch SW4 is connected to the source of the NMOS transistor MN6, and the break terminal of the switch SW4 is connected to the source of the NMOS transistor MN7.
Furthermore, the switch SW5 is inserted between the non-inverting input terminal In+ and the two differential transistor pairs (i.e., the paired NMOS transistors MN1, MN2 and the paired PMOS transistors MP1, MP2) of the input stage 11, whereas the switch SW6 is inserted between the inverting input terminal In− and the two differential transistor pairs of the input stage 11. The common terminal of the switch SW5 is connected to the non-inverting input terminal In+, the make terminal of the switch SW5 is connected to the gates of the NMOS transistor MN1 and the PMOS transistor MP1, and the break terminal of the switch SW5 is connected to the gates of the NMOS transistor MN2 and the PMOS transistor MP2. On the other hand, the common terminal of the switch SW6 is connected to the inverting input terminal In−, the make terminal of the switch SW6 is connected to the gates of the NMOS transistor MN2 and the PMOS transistor MP2, and the break terminal of the switch SW6 is connected to the gates of the NMOS transistor MN1 and the PMOS transistor MP1.
All the switches SW1 to SW6 operate in linkage with one another. The amplifier circuit 1B can select the make condition in which the common and make terminals of each of the switches SW1 to SW6 are connected together, and the break condition in which the common and break terminals of each of the switches SW1 to SW6 are connected together. Like the amplifier circuit 1A shown in
First, the operational amplifier circuit 10C shown in
Second, a depletion transistor is used for each of the PMOS transistor MP9 and the NMOS transistor MN9 constituting the floating current source of the output stage 12C, and each of the PMOS transistor MP8 and the NMOS transistor MN8 constituting the floating current source of the input stage 11C. This use is effective in enabling the operational amplifier circuit 10C shown in
Third, a depletion transistor is used for each of the PMOS transistors MP11, MP13 and the NMOS transistors MN11, MN13 in the bias circuit 2C. This is also effective in enabling the operational amplifier circuit 10C shown in
As described above, this embodiment uses the depletion transistor as each of the MOS transistors constituting the floating current sources in the input stage 11C and the output stage 12C. Thereby, this embodiment enables the amplifier circuit 1C to carry out its low-voltage operation. In addition, this embodiment uses the depletion transistor as each of the MOS transistors (the PMOS transistors MP11, MP13 and the NMOS transistors MN11, MN13) constituting the circuit parts for supplying the bias voltages to these floating current sources. Thereby, this embodiment enables the bias circuit 2C to carry out its low-voltage operation.
The above-described operational amplifier circuits are suitable to be used as amplifiers for a driver integrated circuit (IC) for driving a liquid crystal display panel or any other type of display panel. One of their effective uses is a data line driver for driving a data line of a liquid crystal display panel. In recent years, a data line driver of a type capable of making outputs for even more than 1000 channels has emerged for liquid crystal display panels. More than 1000 operational amplifier circuits connected as voltage followers are installed in such a data line driver. Because the number of outputs made from a data line driver is that large, the power consumed by the data line driver as a chip is accordingly large. As a result, the temperature of the chip is likely to rise to approximately 150° C. which is an operating limit on a silicon semiconductor device. On the contrary, the use of the above-described operational amplifier circuits (particularly, the operational amplifier circuits according to the first and second embodiments) makes it possible to drastically reduce the power consumption of the data line driver.
The latch 31p, the level shift circuit 32p, the positive-side D/A converter (DAC) 33p and the positive-side amplifier 34p are circuits for generating the driving voltage which is higher than a common voltage VCOM and lower than the power supply voltage VDD in response to the image data D1. In this embodiment, the common voltage VCOM is the voltage VDD/2 which is a half of the power supply voltage VDD. For this reason, the driving voltage outputted from the positive-side amplifier 34p is higher than the voltage VDD/2 and lower than the power supply voltage VDD.
Specifically, the latch 31p latches the image data D1, and transmits the latched image data D1 to the positive-side DAC 33p through the level shift circuit 32p. The level shift circuit 32p matches the level of the output from the latch 31p to the level of the input into the positive-side DAC 33p by shifting the levels. The positive-side DAC 33p converts the resultant image data D1 from digital to analog. More specifically, the positive-side DAC 33p receives grayscale voltages V1+ to Vm+ from the grayscale voltage generating circuit 38, and selects a grayscale voltage corresponding to the image data D1 out of the received grayscale voltages V1+ to Vm+. Thereby, the positive-side DAC 33p supplies the thus-selected grayscale voltage to the positive-side amplifier 34p. Here, ail the grayscale voltages V1+ to Vm+ are higher than the voltage VDD/2 and lower than the power supply voltage VDD. The positive-side amplifier 34p operates as a voltage follower, and thus outputs a driving voltage having the same voltage level as the grayscale voltage received from the positive-side DAC 33p. As described later, the positive-side amplifier 34p operates by receiving the intermediate power supply voltage VDD/2 in addition to the power supply voltage VDD and the ground voltage VSS.
On the other hand, the latch 31n, the level shift circuit 32n, the negative-side DAC 33n and the negative-side amplifier 34n are circuits for generating the driving voltage which is higher than the ground voltage VSS and lower than the common voltage VCOM in response to the image data D2. In this embodiment, because the common voltage VCOM is the voltage VDD/2 which is a half of the power supply voltage VDD, the driving voltage outputted from the negative-side amplifier 34n is accordingly higher than the ground voltage VSS and lower than the voltage VDD/2.
Specifically, the latch 31n latches the image data D2, and transmits the latched image data D2 to the negative-side DAC 33n through the level shift circuit 32n. The level shift circuit 32n matches the level of the output from the latch 31n and the level of the input into the negative-side DAC 33n by shifting the levels. The negative-side DAC 33n converts the resultant image data D2 from digital to analog. More specifically, the negative-side DAC 33n receives grayscale voltages V1− to Vm− from the grayscale voltage generating circuit 38, and selects a grayscale voltage corresponding to the image data D2 out of the received grayscale voltages V1− to Vm−. Thereby, the negative-side DAC 33n supplies the thus-selected grayscale voltage to the negative-side amplifier 34n. Here, all the grayscale voltages V1− to Vm− are higher than the voltage VDD/2 and lower than the power supply voltage VDD. The negative-side amplifier 34n operates as a voltage follower, and thus outputs the driving voltage having the same voltage level as the grayscale voltage received from the negative-side DAC 33n. As described later, the negative-side amplifier 34n operates by receiving the intermediate power supply voltage VDD/2 in addition to the power supply voltage VDD and the ground voltage VSS.
The switch circuit 35 is a circuit for switching the connection of the positive-side amplifier 34p between the output terminal 36 and the output terminal 37, as well as the connection of the negative-side amplifier 34n between the output terminal 37 and the output terminal 36. In a case where the driving voltage which is higher than the common voltage VCOM and lower than the power supply voltage VDD is outputted from the output terminal 36 whereas the driving voltage which is higher than the ground voltage VSS and lower than the common voltage VCOM is outputted from the output terminal 37, the switch circuit 35 sets the switches 35a, 35d to ON, and sets the switches 35b, 35c to OFF. Thereby, the positive-side amplifier 34p is connected to the output terminal 36, and the negative-side amplifier 34n is connected to the output terminal 37. Consequently, the driving voltage which is higher than the common voltage VCOM and lower than the power supply voltage VDD is outputted from the output terminal 36, and the driving voltage which is higher than the ground voltage VSS and lower than the common voltage VCOM is outputted from the output terminal 37. On the other hand, in a case where the driving voltage which is higher than the ground voltage VSS and lower than the common voltage VCOM is outputted from the output terminal 36 whereas the driving voltage which is higher than the common voltage VCOM and lower than the power supply voltage VDD is outputted from the output terminal 37, the switch circuit 35 sets the switches 35b, 35c to ON, and sets the switches 35a, 35d to OFF.
The grayscale voltage generating circuit 38 supplies the grayscale voltages V1+ to Vm+ to the positive-side DAC 33p, and the grayscale voltages V1− to Vm− to the negative-side DAC 33n.
The power supply system 39 generates the power supply voltage VDD, the intermediate power supply voltage VDD/2 and the ground voltage VSS, and supplies these voltages to the circuit parts in the liquid crystal display panel driving apparatus 30.
The liquid crystal display panel driving apparatus 30 shown in
For the purpose of further reducing the power consumption of the liquid crystal display panel driving apparatus 30, it is desirable that the above-described operational amplifier circuits be used as γ amplifiers in the grayscale voltage generating circuit 38 for generating the grayscale voltages V1+ to Vm+ and the grayscale voltages V1− to Vm−. Here, the γ amplifiers are amplifiers for supplying bias voltages to a ladder resistor used to generate the grayscale voltages V1+ to Vm+ and the grayscale voltages V1− to Vm−, for the purpose of allowing the grayscale voltages V1+ to Vm+ and the grayscale voltages V1− to Vm− to be generated in accordance with a desired gamma curve.
In the grayscale voltage generating circuit 38 shown in
The foregoing descriptions have been provided for the specific embodiments of the present invention. However, note that the present invention can be carried out as various modifications, and that the present invention shall not be construed as being limited to the above-described embodiments. In particular, it should be noted that the present invention can be applied to a display panel driving apparatus for driving data lines of a display panel other than the liquid crystal display panel, although the foregoing descriptions have been provided for the embodiment in which the operational amplifier circuits are applied to the liquid crystal display panel driving apparatus for driving the liquid crystal display panel. Furthermore, the operational amplifier circuits according to the present invention are applicable to other various uses requiring an operation with a lower voltage and with less power consumption.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201649/2008 | Aug 2008 | JP | national |
