Patent Grant
11456715
The disclosed technology generally relates to an operational amplifier.
Settling time reduction may be one issue with an operational amplifiers. A reduced settling time of the operational amplifier may enhance the operation speed, and therefore an operational amplifier may be designed to reduce the settling time.
This summary is provided to introduce in a simplified form a selection of concepts that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.
In one or more embodiments, an operational amplifier is provided. The operational amplifier includes a first output transistor having a gate coupled to an output node, at least one first intermediate transistor each having a common gate node, a first input transistor having a gate coupled to an input node, and a first load device coupled to sources of the first output transistor, the at least one first intermediate transistor, and the first input transistor. The operational amplifier further includes an output stage coupled to the output node, configured to drive the voltage on the output node based on a first current through the first output transistor, a second current through the at least one first intermediate transistors, and a third current through the first input transistor. The operational amplifier further includes a first switch coupled between the common gate node of the at least one first intermediate transistor and the gate of the first input transistor, and a second switch coupled between the output node and the common gate node of the at least one first intermediate transistors.
In one or more embodiments, a method to control input capacitance in an amplifier circuit. The method includes generating a first current through a first output transistor having a gate coupled to an output node, generating a second current through the at least one first intermediate transistor each having a common gate node, and generating a third current through an input transistor having a gate coupled to an input voltage, the sources of the first output transistor, the at least one first intermediate transistors and the first input transistor being coupled to a load device. The method further includes driving the output voltage on the output node based on the first current, the second current, and the third current, electrically connecting the common gate node of the at least one first intermediate transistors to the gate of the input transistor during a first period, and electrically connecting the common gate node of the at least one first intermediate transistors to the output node during a second period that follows the first period. The second period begins with a change in the input voltage.
Other aspects of the embodiments will be apparent from the following description and the appended claims.
So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments, and are therefore not to be considered limiting of inventive scope, as the disclosure may admit to other equally effective embodiments.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized in other embodiments without specific recitation. Suffixes may be attached to reference numerals for distinguishing identical elements from each other. The drawings referred to herein should not be understood as being drawn to scale unless specifically noted. Also, the drawings are often simplified and details or components omitted for clarity of presentation and explanation. The drawings and discussion serve to explain principles discussed below, where like designations denote like elements.
The following detailed description is merely exemplary in nature and is not intended to limit the disclosure or the application and uses of the disclosure. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding background, summary, or the following detailed description.
In the present application, the term “coupled” means connected directly to or connected through one or more intervening components or circuits.
One issue with operational amplifiers is the settling time, which may be the time required for an output to reach and remain within a given error band after the input is given. Reduction in the settling time may advantageously enhance the operational speed of the system. For example, in embodiments where operational amplifiers are used in a display driver configured to drive a display panel, reduction in the settling time may allow an increased refresh rate.
One approach to reduce the settling time of an operational amplifier is to reduce the input capacitance of the operational amplifier. The reduction in the input capacitance of the operational amplifier may reduce an input current at the input of the operational amplifier and thereby suppress fluctuation in the voltage level of a signal line coupled to the input. The suppression of the voltage level fluctuation may contribute to the reduction in the settling time. The reduction of the input capacitance may be especially advantageous in the case where an increased number of operational amplifiers are commonly coupled to the same signal line that provides the input voltage to the respective operational amplifiers.
The present disclosure provides various approaches to reduce the input capacitance of an operational amplifier. In one embodiment, an operational amplifier includes a first transistor, a second transistor, a third transistor, a constant current source, and an output stage. The first transistor has a first gate configured to receive an output voltage from an output node. The second transistor has a second gate. The third transistor has a third gate configured to receive an input voltage. The constant current source is coupled to sources of the first transistor, the second transistor, and the third transistor. The output stage is configured to drive the output voltage on the output node based on a first current through the first transistor, a second current through the second transistor, and a third current through the third transistor. A first switch is coupled between the second gate of the second transistor and the third gate of the third transistor, and a second switch is coupled between the output node and the second gate of the second transistor. This configuration of the operational amplifier allows selectively connecting and disconnecting the gate of the second transistor to and from the gate of the third transistor, which may reduce the effective input capacitance of the operational amplifier. The first, second, and third transistors may have a first channel conductivity type. In some embodiments, the first channel conductivity type is a positive channel conductivity type. In other embodiments, the first channel conductivity type is a negative channel conductivity type.
In some embodiments, the operational amplifier may further include a fourth transistor, a fifth transistor, a sixth transistor, and a second constant current source. The fourth, fifth, and sixth transistors may have a second channel conductivity type opposite to the first channel conductivity type. In some embodiments, the first channel conductivity type may be a positive channel conductivity type and the second channel conductivity type may be a negative channel conductivity type. In other embodiments, the first conductivity type may be a negative channel conductivity type and the second channel conductivity type may be a positive channel conductivity type. The fourth transistor may have a fourth gate configured to receive the output voltage from the output node. The fifth transistor may have a fifth gate coupled to the second gate of the second transistor. The sixth transistor may have a sixth gate coupled to the third gate of the third transistor to receive the input voltage. The second constant current source may be coupled to sources of the fourth transistor, the fifth transistor, and the sixth transistor. In such embodiments, the output stage may be configured to drive the output voltage based on the first current, the second current, the third current, a fourth current through the fourth transistor, a fifth current through the fifth transistor and a sixth current through the sixth transistor.
The sources of the PMOS transistors P1, P2, and P3 are commonly coupled to the constant current source 112, and the drains of the PMOS transistors P1, P2, and P3 are coupled to the output stage 104. In the illustrated embodiment, the drains of the PMOS transistors P2 and P3 are commonly coupled, and the commonly coupled drains are coupled to the output stage 104. In other embodiments, the drains of the PMOS transistors P2 and P3 may be individually coupled to the output stage 104 (e.g., as illustrated in
The sources of the NMOS transistors N1, N2, and N3 are commonly coupled to the constant current source 114, and the drains of the NMOS transistors N1, N2, and N3 are coupled to the output stage 104. In the illustrated embodiment, the drains of the NMOS transistors N2 and N3 are commonly coupled, and the commonly coupled drains are coupled to the output stage 104. In other embodiments, the drains of the NMOS transistors N2 and N3 may be individually coupled to the output stage 104 (e.g., as illustrated in
The constant current source 112 is coupled between a high-side power supply line 116 on which a high-side power supply voltage VDD is generated and the commonly-coupled sources of the PMOS transistors P1, P2, and P3. The constant current source 112 is configured to feed a constant current to the commonly-coupled sources of the PMOS transistors P1, P2, and P3.
The constant current source 114 is coupled between the commonly-coupled sources of the NMOS transistors N1, N2, and N3 and a low-side power supply line 118 on which a low-side power supply voltage VSS lower than the high-side power supply voltage VDD is generated. In one implementation, the low-side power supply voltage VSS is at a circuit ground level and the high-side power supply voltage VDD is at a voltage level higher than the circuit ground level. The constant current source 114 is configured to draw a constant current from the commonly-coupled sources of the NMOS transistors N1, N2, and N3.
The gates of the PMOS transistor P1 and the NMOS transistor N1 are commonly coupled to the output node 108 to receive the output voltage Vout, and the gates of the PMOS transistor P3 and the NMOS transistor N3 are commonly coupled to the input node 106 to receive the input voltage Vin.
The gates of the PMOS transistor P2 and the NMOS transistor N2 are commonly coupled to the switch SW1 and the switch SW2. The switch SW1 is coupled between the input node 106 and the commonly-coupled gates of the PMOS transistor P2 and the NMOS transistor N2, and the switch SW2 is coupled between the output node 108 and the commonly-coupled gates of the PMOS transistor P2 and the NMOS transistor N2. The switch SW1 may be configured to turn on and off in response to a control signal CTRL1 received from the control circuitry 120 and the switch SW2 may be configured to turn on and off in response to a control signal CTRL2 received from the control circuitry 120.
The output stage 104 is configured to generate the output voltage Vout based on the current Ip1 through the PMOS transistor P1, the current Ip2 through the PMOS transistor P2, and the current Ip3 through the PMOS transistor P3. In the illustrated embodiment in which the drains of the PMOS transistors P2 and P3 are commonly coupled, the output stage 104 may be configured to generate the output voltage Vout based on the difference between the current Ip1 and the sum current of the currents Ip2 and Ip3.
The output voltage Vout is generated further based on the current In1 through the NMOS transistor N1, the current In2 through the NMOS transistor N2, and the current In3 through the NMOS transistor N3. In the illustrated embodiment in which the drains of the NMOS transistors N2 and N3 are commonly coupled, the output stage 104 may be configured to generate the output voltage Vout based on the difference between the current In1 and the sum current of the currents In2 and In3.
In one or more embodiments, the operational amplifier 100 has two operation states in which the switches SW1 and SW2 are exclusively turned on. In a first operation state, the switch SW1 is on and the switch SW2 is off. In the first operation state, the gates of the PMOS transistor P2 and the NMOS transistor N2 are electrically connected to the input node 106 (that is, the commonly-coupled gates of the PMOS transistor P3 and the NMOS transistor N3), and are electrically disconnected from the output node 108. In a second operation state, the switch SW1 is off and the switch SW2 is on. In the second operation state, the gates of the PMOS transistor P2 and the NMOS transistor N2 are electrically connected to the output node 108, and are electrically disconnected from the input node 106.
In one or more embodiments, the gate widths of the PMOS transistors P1, P2, and P3 may be adjusted such that the gate width of the PMOS transistor P1 is substantially equal to the sum of the gate widths of the PMOS transistors P2 and P3. The term “substantially equal” in this application is intended to refer to the fact that the variances for the gate widths are within the range of manufacturing tolerances. The thus-adjusted gate widths of the PMOS transistors P1, P2, and P3 effectively reduces the offset of the output voltage Vout of the operational amplifier 100 in the first operation mode, in which the switch SW1 is on and the switch SW2 is off.
In one or more embodiments, the gate widths of the NMOS transistors N1, N2, and N3 may be adjusted such that the gate width of the NMOS transistor N1 is substantially equal to the sum of the gate widths of the NMOS transistors N2 and N3. The thus-adjusted gate widths of the NMOS transistors N1, N2, and N3 may reduce the offset of the output voltage Vout in the first operation mode.
In one or more embodiments, the gate widths of the PMOS transistors P2 and P3 may be adjusted such that the gate width of the PMOS transistor P2 is larger than the gate width of the PMOS transistor P3. The thus-adjusted gate widths of the PMOS transistors P2 and P3 effectively reduce the input capacitance of the operational amplifier 100 in the second operation mode, in which the switch SW1 is off and the switch SW2 is on.
In one or more embodiments, the gate widths of the NMOS transistors N2 and N3 may be adjusted such that the gate width of the NMOS transistor N2 is larger than the gate width of the NMOS transistor N3. The thus-adjusted gate widths of the NMOS transistors N2 and N3 effectively reduce the input capacitance of the operational amplifier 100 in the second operation mode. A description is given below of the reduction in the input capacitance in the second operation mode with reference to
Period #2 that follows period #1 begins with a change in the input voltage Vin to a second voltage Vmax higher than the first voltage Vmin. The second voltage Vmax may be the maximum voltage the operational amplifier 100 is configured to output. In one implementation, the input voltage supply circuitry 110 (illustrated in
During period #2, the operational amplifier 100 is placed into the second operation state in which the switch SW1 is off and the switch SW2 is on. During period #2, the switch SW1 electrically disconnects the gates of the PMOS transistor P2 and the NMOS transistor N2 from the gates of the PMOS transistor P3 and the NMOS transistor N3, while the switch SW2 electrically connects the gates of the PMOS transistor P2 and the NMOS transistor N2 to the output node 108. The operational amplifier 100 is kept in the second operation state during period #2.
As is described in relation to
The output voltage Vout is pulled up towards the second voltage Vmax in response to the input voltage Vin being changed to the second voltage Vmax. It is noted that, although the gates of the PMOS transistor P2 and the NMOS transistor N2 are electrically disconnected from the input node 106, the voltages on the gates of the PMOS transistor P2 and the NMOS transistor N2 also approach the second voltage Vmax during period #2 as the gates of the PMOS transistor P2 and the NMOS transistor N2 are charged with the output voltage Vout. Charging the gates of the PMOS transistor P2 and the NMOS transistor N2 with the output voltage Vout also helps reduction in the input current Iin. During period #2, the output voltage Vout may not reach the second voltage Vmax due to the load capacitance coupled to the output node 108 and/or an offset potentially caused by electrically connecting the gates of the PMOS transistor P2 and the NMOS transistor N2 to the gates of the PMOS transistor P1 and the NMOS transistor N1, which may cause an unbalance of the differential input stage 102.
During period #3 that follows period #2, the operational amplifier 100 is returned to the first operation state in which the switch SW1 is on and the switch SW2 is off. During period #3, the switch SW1 electrically connects the gates of the PMOS transistor P2 and the NMOS transistor N2 to the gates of the PMOS transistor P3 and the NMOS transistor N3, while the switch SW2 electrically disconnects the gates of the PMOS transistor P2 and the NMOS transistor N2 from the output node 108. The input voltage Vin is kept at the second voltage Vmax during period #3, and the output voltage Vout reaches the second voltage Vmax in the initial phase of period #3. It is noted that the differential input stage 102 recovers from the unbalance during period #3 by electrically connecting the gates of the PMOS transistor P2 and the NMOS transistor N2 to the gates of the PMOS transistor P3 and the NMOS transistor N3.
Period #4 that follows period #3 begins with a change in the input voltage Vin to the first voltage Vmin. During period #4, the operational amplifier 100 is placed into the second operation state in which the switch SW1 is off and the switch SW2 is on. In one implementation, the input voltage supply circuitry 110 (illustrated in
The output voltage Vout is pulled down towards the first voltage Vmin in response to the input voltage Vin being changed to the first voltage Vmin. During period #4, the output voltage Vout may not reach the first voltage Vmin due to the load capacitance coupled to the output node 108 and/or an offset potentially caused by electrically connecting the gates of the PMOS transistor P2 and the NMOS transistor N2 to the gates of the PMOS transistor P1 and the NMOS transistor N1, which may cause an unbalance of the differential input stage 102.
During period #5 that follows period #4, the operational amplifier 100 is returned to the first operation state in which the switch SW1 is on and the switch SW2 is off. The input voltage Vin is kept at Vmin during period #5, and the output voltage Vout reaches the first voltage Vmin in the initial phase of period #5.
The current mirror 122 includes PMOS transistors P4 and P5 that have commonly-coupled gates coupled to the drain of the PMOS transistor P5. The sources of the PMOS transistors P4 and P5 are commonly coupled to the high-side power supply line 116. The drain of the PMOS transistor P4 is coupled to a node 132 that is coupled to the drain of the NMOS transistor N1, and the drain of the PMOS transistor P5 is coupled to a node 134 that is coupled to the drains of the NMOS transistors N2 and N3.
The current mirror 124 includes NMOS transistors N4 and N5 that have commonly-coupled gates coupled to the drain of the NMOS transistor N5. The sources of the NMOS transistors N4 and N5 are commonly coupled to the low-side power supply line 118. The drain of the NMOS transistors N4 is coupled to a node 136 that is coupled to the drain of the PMOS transistor P1, and the drain of the NMOS transistor N5 is coupled to a node 138 that is coupled to the drains of the NMOS transistors P2 and P3.
The floating current source 126 is configured to draw a first constant current from the node 132 and supply the first constant current to the node 136. In one implementation, the floating current source 126 includes an NMOS transistor N6 and a PMOS transistor P6. The NMOS transistor N6 has a drain coupled to the node 132, a source coupled to the node 136, and a gate biased with a fixed bias voltage VBN. The PMOS transistor P6 has a source coupled to the node 132, a drain coupled to the node 136, and a gate biased with a fixed bias voltage VBP.
The floating current source 128 is configured to draw a second constant current from the node 134 and supply the second constant current to the node 138. In one implementation, the floating current source 128 includes an NMOS transistor N7 and a PMOS transistor P7. The NMOS transistor N7 has a drain coupled to the node 134, a source coupled to the node 138, and a gate biased with the fixed bias voltage VBN. The PMOS transistor P7 has a source coupled to the node 134, a drain coupled to the node 138, and a gate biased with the fixed bias voltage VBP.
The PMOS output transistor PO1 is configured to pull up the output node 108 based on the voltage level on the node 132. The PMOS output transistor PO1 has a gate coupled to the node 132, a source coupled to the high-side power supply line 116, and a drain coupled to the output node 108. Correspondingly, the NMOS output transistor NO1 is configured to pull down the output node 108 based on the voltage level on the node 136. The NMOS output transistor NO1 has a gate coupled to the node 136, a source coupled to the low-side power supply line 118, and a drain coupled to the output node 108.
In one or more embodiments, the operational amplifiers illustrated in
In one or more embodiments, the display driver 200 may include an array of source amplifiers 202, grayscale voltage generating circuitry 204, a set of grayscale voltage lines 206, an array of digital-to-analog converters (DACs) 208, control circuitry 210, and source outputs S1 to S2n, where n is a natural number. The source amplifiers 202 are configured as operational amplifiers configured to supply output voltages to the source lines 304 of the display panel 300 coupled to the source outputs S1 to S2n. The grayscale voltage generating circuitry 204 is configured to generate a set of different grayscale voltages on the grayscale voltage lines 206. The grayscale voltage lines 206 are extended across the array of the DACs 208 to deliver the grayscale voltages to the DACs 208. The DACs 208 are coupled to the source amplifiers 202, respectively. The DACs 208 are configured to receive pixel data, denoted by D[1] to D[2n], respectively. Pixel data D[i] may include a graylevel defined for a corresponding pixel 302 coupled to the source line 304 coupled to the source output Si, where i is a natural number between 1 and 2n, inclusive. The graylevel may correspond to a specified luminance level of the corresponding pixel 302. The DAC 208 that receives the pixel data D[i] is configured to generate an input voltage of the source amplifier 202 coupled to the source output Si. In one implementation, the DAC 208 that receives the pixel data D[i] is configured to select one of the grayscale voltages generated on the grayscale voltage lines 206 and supply the selected grayscale voltage as the input voltage to the input of the source amplifier 202 coupled to the source output Si. In one implementation, the DAC 208 that receives the pixel data D[i] is configured to electrically connect the input of the corresponding source amplifier 202 to the grayscale voltage line 206 on which the selected grayscale voltage is generated and thereby supply the selected grayscale voltage to the input of the corresponding source amplifier 202. The source amplifiers 202 are configured to update the pixels 302 coupled to the corresponding source outputs S1 to S2n with the output voltages output therefrom. The control circuitry 210 is configured to control the source amplifiers 202.
One issue of the display driver 200 may be that, in embodiments where an increased number of source amplifiers 202 (e.g., 1000 or more source amplifiers 202) are integrated in the display driver 200, the input currents (indicated by “I1” to “I2n” in
To mitigate or eliminate the effect of the input currents of the source amplifiers 202, in one or more embodiments, the operational amplifiers 100 illustrates in
Method 1100 of
The method includes generating a first current through a first transistor (e.g., the PMOS transistors P1 and the NMOS transistor N1 illustrated in
The method further includes driving the output voltage on the output node based on the first current, the second current, and the third current at step 1108. The method further includes electrically connecting the second gate of the second transistor to the third gate of the third transistor during a first period (e.g., period #1 in
While many embodiments have been described, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope. Accordingly, the scope of the invention should be limited only by the attached claims.
This application is a continuation of, and thereby claims benefit under 35 U.S.C. § 120 to, U.S. patent application Ser. No. 17/359,257, which is incorporated herein by reference in its entirety.
| Number | Name | Date | Kind |
|---|---|---|---|
| 20140340288 | Yamashita | Nov 2014 | A1 |
| 20180061307 | Inoue | Mar 2018 | A1 |
| 20190068148 | Oishi | Feb 2019 | A1 |
| 20190108809 | Zheng | Apr 2019 | A1 |
| 20200020266 | Feng | Jan 2020 | A1 |
| 20200312264 | Tsuchi | Oct 2020 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17359257 | Jun 2021 | US |
| Child | 17565370 | US |
