Operational amplifier with stabilized DC operations

Abstract

An operational amplifier with improved operational speed, as well as low power consumption, arranges a current mirror made of the pMOS transistors PT.sub.17 and PT.sub.18 in the stage after the initial-stage differential amplifier, supplies the output of the initial-stage differential amplifier to the gate of the nMOS transistor NT.sub.14, supplies the current flowing through the current mirror to the output stage side by a current mirror made of the pMOS transistors PT.sub.15 and PT.sub.16, and lastly a pMOS transistor PT.sub.19 is connected as a constant-current source between the supply line for the power supply voltage V.sub.DD and the node ND.sub.12, and makes the idling current I.sub.19 flow in the node ND.sub.12. Due to this, stabilization of DC operations during normal states and when shifting its states can be designed without considering the characteristics in the vicinity of the threshold voltage of pMOS transistor PT.sub.16, and thus stringent controls in the manufacturing process and the like are unnecessary.

Description

FIELD OF THE INVENTION

Our invention relates to operational amplifiers, and more particularly to operational amplifiers for use with liquid-crystal displays or the like.

BACKGROUND OF THE INVENTION

A conventional source driver integrated circuit for a thin-film transistor (TFT-type) LCD display samples and holds an analog input signal voltage, buffers the sampled voltage in an operational amplifier, and correspondingly drives the source terminals of the LCD display. The operational amplifier used in such a source driver must be able to quickly charge the LCD (liquid crystal display) panel's capacitance of several hundred picofarads. As there is a trend toward using large-sized LCD panels having multiple channels, each channel having at least one operational amplifier, such amplifiers must be made very small.

A conventional CMOS operational amplifier is shown in FIG. 8, in which PT.sub.11 to PT.sub.16 are pMOS transistors, NT.sub.11 -NT.sub.13 are nMOS transistors, and I.sub.11 and I.sub.12 are current sources.

The sources of pMOS transistors PT.sub.11 and PT.sub.12 are connected together, the sources of pMOS transistors PT.sub.13 -PT.sub.16 are connected to supply voltage V.sub.DD, and the sources of the nMOS transistors NT.sub.11 -NT.sub.13 are connected to ground.

A high gain, initial stage differential amplifier is formed as follows. The gate of pMOS transistor PT.sub.11 is connected to an input terminal T.sub.IN for receiving an input signal IN, and the gate of pMOS transistor PT.sub.12 is connected for negative feedback to an output-side node ND.sub.12. The drains of PT.sub.11 and nMOS transistor NT.sub.11 are connected at node ND.sub.11, and the drains of PT.sub.12 and nMOS transistor NT.sub.12 are also connected together. The gates of NT.sub.11 and NT.sub.12 are connected to each other and to the drain of NT.sub.12. The output of this differential amplifier at node ND.sub.11 is connected to the gate of nMOS transistor NT.sub.13 in an output amplifier stage.

The output amplifier stage is formed by connecting together the drains of pMOS transistor PT.sub.16 and nMOS transistor NT.sub.13 at output-side node ND.sub.12 which is connected to an output terminal T.sub.OUT.

In the initial stage, a current mirror is formed by connecting the gates of PT.sub.13 and PT.sub.14 to each other, to the drain of PT.sub.13, and to current source I.sub.11. The drain of pMOS transistor PT.sub.14 is connected to the common connecting point for the sources of PT.sub.11 and PT.sub.12 of the differential amplifier. This current mirror supplies a constant current to the differential amplifier.

Similarly, in the output amplifier stage a current mirror is formed by connecting the gates of pMOS transistors PT.sub.15 and PT.sub.16 to each other, to the drain of PT.sub.15, and to current source I.sub.12. This current mirror supplies a constant current to the output amplifier stage. The output of the differential amplifier at node ND.sub.11 determines whether the gate of NT.sub.13 switches that transistor OFF (for VIN>VOUT) or ON (for VIN.ltoreq.VOUT), thereby controlling whether this constant current primarily flows into a capacitive external load (not shown) attached to terminal T.sub.OUT or is shunted to ground via the drain and source of NT.sub.13.

In the differential amplifier, the gate of PT.sub.11 forms the noninverting input and the gate of PT.sub.12 forms the inverting input. Because the differential amplifier's inverting input is connected to the output terminal T.sub.OUT of the overall operational amplifier, the operational amplifier has a gain of "1."

A capacitor C.sub.11 is connected between the gate and drain of nMOS transistor NT.sub.13 of the output stage to provide phase compensation.

Thus, the conventional operational amplifier of FIG. 8 receives an input signal voltage V.sub.IN at a high impedance input terminal T.sub.IN and outputs the same voltage as an output signal voltage V.sub.OUT at a low impedance output terminal T.sub.OUT. Because the output stage is constant current driven, it is a class A operational amplifier.

Its output with NT.sub.13 ON can quickly discharge a load capacitance, but its charging speed with NT.sub.13 OFF is limited by the constant current value of the current mirror made of transistors PT.sub.15 and PT.sub.16. To obtain a high charging speed, the constant current must be made large. Because this current continues to flow even after the output voltage becomes equal to the input voltage (NT.sub.13 goes ON), this conventional circuit's current consumption is large.

To reduce current consumption, the circuit of FIG. 9 having separate, parallel amplifiers AMP.sub.A, AMP.sub.B respectively for charging and discharging has been proposed. However, because this circuit requires two substantial amplifiers per channel and switches SW.sub.11A, SW.sub.12A, SW.sub.11B and SW.sub.12B for switching between them, it is difficult to keep small.

Therefore, it is an object of our invention to provide a small operational amplifier with improved operating speed and low power consumption.

SUMMARY OF INVENTION

An operational amplifier of our invention has a first current source that supplies a first and second current in a proportional relationship, a second current source that supplies a third current, a constant current means that keeps the sum of the second and third current constant, a first transistor that charges or discharges the output terminal at a current made proportional to the third current, a second transistor that charges or discharges the output terminal in response to an input signal, a third transistor that controls the value of the first current to have a relationship wherein it is made proportional to the current flowing in the second transistor in response to the input signal, and a third current source that supplies a fourth to the output terminal at least in a normal state, during neither charging nor discharging.

Also, the operational amplifier of our invention has a first current source that supplies a first and second current in a proportional relationship, a second current source that supplies a third current, a constant current means that keeps the sum of the second and third current constant, a first transistor that charges or discharges the output terminal at a current made proportional to the third current, a second transistor that charges or discharges the output terminal in response to an input signal, a third transistor that controls the value of the first current to have a relationship wherein it is made proportional to the current flowing in the second transistor in response to the input signal, and a circuit that limits the first current during charging.

According to the operational amplifier of our invention, since there is a proportional relationship between the first and second current flowing through a second transistor, the sum of the second and third current is constant, there is a proportional relationship between the third current and the current flowing through the first transistor, the current flowing through the second transistor increases, the third current is reduced due to the increase in the first and second current, and the current flowing through the first transistor is reduced.

In contrast to this, if the current flowing through the second transistor is reduced, the third current is increased due to the decrease in the first and second current, and the current flowing through the first transistor is increased. This circuit charges and discharges the output terminal with a class-AB operation.

Also, at least during normal operations, the so-called idling current is supplied by a third current source to the output terminals.

In this case, if consideration is given to a case in which the third current source is nonexistent, during normal states, the small amount of current that is equivalent to the idling current must be made to flow by the first transistor.

Originally, to increase the rising speed of the output voltage during discharging, i.e. throughput, the transistor size of the first transistor was designed to be large. At this time, to make a very small amount of current flow by the first transistor, the first transistor has to operate in the vicinity of the threshold voltage.

This fact meant that if the threshold voltage of the first transistor varied depending on the state of the process, it became extremely unstable from the standpoint of the circuit.

In contrast to this, due to the fact that there is a third current source, stable operation becomes possible without considering the characteristics in the vicinity of the threshold voltage of the first transistor.

Also, during discharging, the upper limit of the first current is kept from being becoming extremely large, and the current consumption is restrained.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic of a first embodiment of an operational amplifier according to our invention.

FIG. 2 is a schematic of an embodiment of a constant-voltage supply circuit according to our invention.

FIG. 3 is a current vs. time graph of the simulation effects of the operational amplifier of FIG. 1.

FIG. 4 is a schematic of a second embodiment of an operational amplifier according to our invention.

FIG. 5 is a schematic of a third embodiment of an operational amplifier according to our invention.

FIG. 6 is a current vs. time graph showing the simulation effects of the operational amplifier of FIG. 5.

FIG. 7 is a schematic of a fourth embodiment of an operational amplifier according to our invention.

FIG. 8 is a schematic of a conventional CMOS operational amplifier.

FIG. 9 is a schematic of a conventional CMOS operational amplifier having an amplifier for charging and an amplifier for discharging.

In the figures, PT.sub.11 -PT.sub.19, PT.sub.11a -PT.sub.16a, PT101-102, PT11A-13A, PT11B-16B are pMOS transistors, NT.sub.11 -NT.sub.16, NT.sub.11a -NT.sub.19a, NT101-103, NT13A-16A are nMOS transistors, C.sub.11 and C.sub.11a are phase compensating circuits, and I.sub.11, I.sub.11a, I.sub.12 are current sources.

DETAILED DESCRIPTION

Embodiment 1

FIG. 1 shows a first embodiment of a CMOS operational amplifier according to our invention, in which parts the same as those in FIG. 8 have the same reference numerals.

An input terminal T.sub.IN receives an input signal V.sub.IN and an output terminal T.sub.OUT provides an output signal V.sub.OUT to a capacitive external load C.sub.L. PT.sub.11 -PT.sub.19 are pMOS transistors, NT.sub.11 -NT.sub.15 are nMOS transistors, I.sub.11 is a current source, and C.sub.11 is a phase compensating capacitor.

A high gain, initial-stage differential amplifier like that in FIG. 8 receives the input voltage V.sub.IN at the gate of PT.sub.11 from input terminal T.sub.IN and the feedback signal V.sub.OUT at the gate of PT.sub.12 from an output node ND.sub.12 coupled to output terminal T.sub.OUT. The initial-stage differential amplifier's output at node ND.sub.11 is supplied to the gates of an nMOS transistor switch NT.sub.14 and an output stage nMOS transistor switch NT.sub.13. The drain current I.sub.14 of NT.sub.14 is the control current I.sub.17 for a current mirror formed by pMOS transistors PT.sub.17 and PT.sub.18.

Another current mirror made of pMOS transistors PT.sub.15 and PT.sub.16 supplies the drain current of PT.sub.16 to output node ND.sub.12 connected to output terminal T.sub.OUT.

The pMOS transistor PT.sub.19 is connected as a constant-current source between supply voltage V.sub.DD and output node ND.sub.12 so that it maintains a constant idling current I.sub.19 into output node ND.sub.12. The gate of pMOS transistor PT.sub.19 is connected to a constant reference voltage V.sub.B1.

The sources of mirror transistors PT.sub.17 and PT.sub.18 are connected to supply voltage V.sub.DD, their gates are connected to each other, to the drain of PT.sub.17 (node ND.sub.13), and to the drain of NT.sub.14.

The drains of transistors PT.sub.18 and PT.sub.15 are connected to each other to form node ND.sub.14, which is also connected to the gates of mirror transistors PT.sub.15 and PT.sub.16 and the drain of nMOS transistor NT.sub.15. Because the source of NT.sub.15 is connected to ground and its gate to a constant reference voltage V.sub.B2, NT.sub.15 maintains a constant drain current I.sub.15. Lastly, the source of nMOS transistor NT.sub.14 is connected to ground and its gate to node ND.sub.11.

FIG. 2 is a schematic of a constant-voltage supply circuit 100 that supplies constant reference voltages V.sub.B1, V.sub.B2 respectively to the gates of transistors PT.sub.19 and NT.sub.15 to make them work as constant current sources. It has a resistor R.sub.101, pMOS transistors PT.sub.101 and PT.sub.102, and nMOS transistors NT.sub.101 -NT.sub.103. Resistor R.sub.101 and nMOS transistor NT.sub.101, pMOS transistor PT.sub.101 and nMOS transistor NT.sub.102, and pMOS transistor PT.sub.102 and nMOS transistor NT.sub.103 are each respectively connected in series between supply voltage V.sub.DD and ground.

Also, the connecting point for the resistor R.sub.101 and the drain of NT.sub.101 is connected to the gates of nMOS transistors NT.sub.101 and NT.sub.102. Also, the common connecting point for ND.sub.101 for the drains of PT.sub.101 and NT.sub.102 is connected to the gates of the pMOS transistors PT.sub.101 and PT.sub.102, which form a current mirror. The potential of this node ND.sub.101 is supplied as the constant voltage V.sub.B1 to the gate of the pMOS transistor PT.sub.19.

The common connecting point node ND.sub.102 for the drains of transistors PT.sub.102 and NT.sub.103 is connected to the gate of the nMOS transistor NT.sub.103, and its voltage is supplied to the gate of nMOS transistor NT.sub.15 as the constant voltage V.sub.B2.

Load Charging (V.sub.IN >V.sub.OUT)

Now the working of my operational amplifier of FIG. 1 will be described. During charging of the load C.sub.L, because V.sub.IN >V.sub.OUT the voltage at ND.sub.11 drops near ground (0 V), cutting OFF nMOS transistor switches NT.sub.13 and NT.sub.14 . This causes the current I.sub.17 flowing through the pMOS transistor PT.sub.17 to approach 0.

The current I.sub.18 flowing in the drain of transistor PT.sub.18 of the current mirror formed by PT.sub.17 and PT.sub.18 is proportional to the size ratio of pMOS transistors PT.sub.17 and PT.sub.18 :

I.sub.18 ={(W.sub.18 /L.sub.18)/(W.sub.17 /L.sub.17)}.multidot.I.sub.17 (Eq. 1) where W.sub.18 and W.sub.17 are the transistors' respective channel widths and L.sub.18 and L.sub.17 the respective channel lengths.

Because current I.sub.17 approaches 0, the current I.sub.18 also approaches 0. Then since current I.sub.15N flowing in the drain of NT.sub.15 is constant, I.sub.15P =I.sub.15N ; i.e. almost 100% of current I.sub.15N flows in pMOS transistor PT.sub.15.

Also, because PT.sub.15 and PT.sub.16 also make up a current mirror:

I.sub.16 ={(W.sub.16 /L.sub.16)/(W.sub.15 /L.sub.15)}.multidot.I.sub.15P ={(W.sub.16 /L.sub.16)/(W.sub.15 /L.sub.15)}.multidot.I.sub.15N (Eq. 2)

Then the output current I.sub.OUT to the output terminal T.sub.OUT becomes:

I.sub.OUT =I.sub.16 +I.sub.19 ={(W.sub.16 /L.sub.16)/(W.sub.15 /L.sub.15)}.multidot.I.sub.15N +I.sub.19 (Eq. 3)

Thus, if transistor PT.sub.16 is made large in relation to PT.sub.15 it can deliver to the load an output current which is a substantial multiple {(W.sub.16 /L.sub.16)/(W.sub.15 /L.sub.15)} of the constant current I.sub.15N. For example, the idling current I.sub.19 due to the pMOS transistor PT.sub.19 that acts as a constant-current source during this charging can be about 4.8 .mu.A, and the drain current I.sub.16 of pMOS transistor PT.sub.16 during charging about 280 .mu.A.

Load Discharging (V.sub.IN <V.sub.OUT)

Next, suppose that after the capacitive load C.sub.L has been charged, the input signal V.sub.IN next drops to less than V.sub.OUT, so the capacitive load must be discharged. Then because V.sub.IN <V.sub.OUT, the voltage at ND.sub.11 rises above the threshold voltages of nMOS transistor switches NT.sub.13 and NT.sub.14, causing them to switch ON, so that respective drain currents I.sub.13 and I.sub.14 flow. Further, let us assume that nMOS transistors NT.sub.13 and NT.sub.14 are the same size transistors.

In this way, corresponding currents I.sub.15P and I.sub.18 will flow into node ND.sub.14 from PT.sub.15 and PT.sub.18, which respectively belong to the two current mirrors PT.sub.15 -PT.sub.16 and PT.sub.17 -PT.sub.18.

Because transistor NT.sub.15 has its source at ground and its gate is supplied with a constant voltage V.sub.B2, it has a constant drain current I.sub.15N. Constant current I.sub.15N is the sum of drain currents I.sub.18 of PT.sub.18 and I.sub.15P of PT.sub.15 flowing into note ND.sub.14 :

Therefore, I.sub.15N =I.sub.18 +I.sub.15P (Eq. 4) I.sub.15P =I.sub.15N -I.sub.18 (Eq. 5)

Because the current I.sub.18 increases with an increase in the drain current I.sub.14 of the nMOS transistor NT.sub.14, the drain current I.sub.15P of the pMOS transistor PT.sub.15 decreases.

In this case, as established in equation 6 listed below, the drain current I.sub.15P of the pMOS transistor PT.sub.15 can be made almost 0 by appropriately setting the sizes of nMOS transistor NT.sub.14 and pMOS transistors PT.sub.17, PT.sub.18, PT.sub.15 and PT.sub.16, so that

I.sub.15N =I.sub.18 ={(W.sub.18 /L.sub.18)/W.sub.17 /L.sub.17)}.multidot.I.sub.17 (Eq. 6)

Because drain current I.sub.15P of the pMOS transistor PT.sub.15 is almost 0, the mirror drain current I.sub.16 of large transistor PT.sub.16 is also reduced and approaches 0, substantially reducing the operational amplifier's current consumption.

As a result, the "intake" current entering node ND.sub.12 from output terminal T.sub.OUT becomes I.sub.13 -I.sub.19. Assuming I.sub.l9 is relatively small compared to I.sub.13, the capacitive load C.sub.L can be quickly discharged by the switching ON of transistor NT.sub.13.

For example, during discharge the idling current I.sub.l9 can be about 4.8 .mu.A, the drain current I.sub.16 of transistor PT16 about 0 .mu.A, and current I.sub.19 a substantially larger value determined by the voltage to which capacitor C.sub.L has been charged and the internal resistance of transistor NT.sub.13.

Normal State (V.sub.IN =V.sub.OUT, No Charging or Discharging)

Next, we consider a normal state when V.sub.OUT =V.sub.IN, so the output load C.sub.L is neither being charged nor discharged. In that case, there is no current flowing to or from the load C.sub.L. Therefore, the initial-stage differential amplifier must set its output node ND.sub.11 at a voltage just high enough to causes the drain current I.sub.13 of transistor NT.sub.13 to equal the sum of drain currents I.sub.16 and I.sub.19.

If we assume I.sub.16 is still very small relative to I.sub.19 in this state, then I.sub.13 .apprxeq.I.sub.19. In fact, the value of idling current I.sub.19 due to transistor PT.sub.19 during this normal state, as well as the drain current I.sub.16 of transistor PT.sub.16, can be about the same as during discharging. For example, idling current I.sub.19 can be about 4.8 .mu.A, and drain current I.sub.16 of the pMOS transistor PT.sub.16 about 0 .mu.A.

Now, in the circuit of FIG. 1, let us consider the case where the constant-current source realized by pMOS transistor PT.sub.19 does not exist. Then in the normal state when V.sub.OUT =V.sub.IN, a very small current equivalent to idling current I.sub.19 must flow in the drain of pMOS transistor PT.sub.16.

Originally, to increase the rising speed of the output voltage during charging when V.sub.IN >V.sub.OUT, i.e. throughput, the transistor size of the pMOS transistor PT.sub.16 was made large in relation to pMOS transistor PT.sub.15. And to make a very small current flow during the normal state in transistor PT.sub.16, it is necessary to operate pMOS transistor PT.sub.16 in the vicinity of its threshold voltage. But if the threshold voltage of PT.sub.16 varies depending on other process conditions, the operational amplifier becomes extremely unstable.

Therefore, the constant current source transistor PT.sub.19 enables stable operation to be realized without considering the characteristics of pMOS transistor PT.sub.16 in the vicinity of its threshold voltage.

A graph of simulation results for the characteristics of the circuit of FIG. 1 are shown in FIG. 3. The simulation shows that this circuit can obtain nearly perfect amplifier characteristics.

Embodiment 2

FIG. 4 shows a second embodiment of an operational amplifier according to our invention. In this circuit, the polarity of each transistor is reversed from that of FIG. 1. It uses n-channel transistors in place of the p-channel transistors and p-channel transistors used in place of n-channel transistors of FIG. 1. To work like the circuit of FIG. 1, the IN(-) inverting input must be connected to output terminal T.sub.OUT, and suitable constant voltages V.sub.C1 and V.sub.C2 must be provided, for example by a constant voltage supply circuit which reverses the polarity of the transistors and voltages of the supply circuit of FIG. 2. An explanation of connection relationships and operation is omitted because adjusting for polarity these are about the same as in the first embodiment.

Embodiment 3

FIG. 5 shows a third embodiment of an operational amplifier which differs from the first embodiment in that an nMOS transistor NT.sub.16, the gate of which is connected to the supply line for the fixed voltage V.sub.B2, is further provided between the source of the nMOS transistor NT.sub.14 and the ground line as a current source used for current limiting during discharging.

If there is no nMOS transistor NT.sub.16, during discharging when V.sub.IN <V.sub.OUT, especially in the case when the output voltage V.sub.OUT is much higher than V.sub.IN, the gate voltage rises so that the nMOS transistor NT.sub.13 can cause a large current to flow. At this time, a large current also flows in the nMOS transistor NT.sub.14 with the same gate potential.

If the basic operations are considered, the following equation can be established.

I.sub.17.gtoreq.{(W.sub.17 /L.sub.17)/W.sub.18 /L.sub.18)}.multidot.I.sub.18 =I.sub.15N (Eq. 7)

However, temporarily, current I.sub.17 becomes an extremely large current compared to I.sub.15N.

This fact is not desirable when viewed from the standpoint of current consumption.

So that there are no problems from the standpoint of operation, within the meaning that the current I.sub.17 is limited, a constant-current source made of nMOS transistor NT.sub.16 is provided. This constant-current source is constructed to cause a slightly larger current than current I.sub.15N to flow.

Since a constant-current source is provided for minimizing the current consumption of that section without changing the operating characteristics, in addition to the effects of the first embodiment, the current consumption of the entire circuit can be further suppressed.

Simulation results for the circuit characteristics of FIG. 5 are shown in FIG. 6.

As shown in FIG. 3, the circuit of FIG. 1 can obtain almost perfect amplification characteristics, but the circuit of FIG. 5 can obtain still better amplification characteristics as shown in FIG. 6.

In the construction of FIG. 5, in the circuit that provided a constant-current source used for the idling current of FIG. 1, a construction was made which added the nMOS transistor NT.sub.16 as a current source used for a current limiter during discharge, but needless to say, low current consumption can still be realized even if it is a circuit that is not generally used as a constantcurrent source for idling current.

Embodiment 4

FIG. 7 is a schematic of a fourth embodiment of an operational amplifier according to our invention. Compared to the third embodiment, the polarity of each transistor is reversed. The n-channel transistors are used in place of the p-channel transistors in FIG. 5, and p-channel transistors are used in place of n-channel transistors.

The explanation regarding the specific connection relationships as well as the operation is omitted here because these are made in about the same manner as in the case of the first embodiment.

Even in this circuit, about the same effects as those of the third embodiment can be obtained.

Also, in each of the embodiments, an explanation was given using MOS transistors as an example, but needless to say, the same type of output circuit can be constructed using bipolar transistors.

As explained above, since the operational amplifier of our invention operates as a class-AB operation, a large current is output only during the charging and discharging of the load capacitor, and only a small current is output in the normal state wherein the charging and discharging of the load capacitor is not being conducted, and both a low power consumption and a high-speed operation can be realized. Also, since the provision of amplifiers used for charging and discharging is not individually necessary, there is the advantage that enlarging of the operational amplifier can be prevented.

Also, stabilization of DC operations during normal states and when shifting states can be designed without considering the characteristics in the vicinity of the threshold voltage of the first transistor. Because of this, there is the advantage that stringent controls in the manufacturing process and the like are unnecessary.

Claims

1. An operational amplifier for driving a capacitive load, comprising:

a signal input terminal of voltage V.sub.IN, and a power input terminal for a supply voltage;

an output terminal of voltage V.sub.OUT and a ground terminal, for coupling to the capacitive load:

a comparator responsive to V.sub.IN and V.sub.OUT for generating a control signal respectively indicating CHARGE, STANDBY, or DISCHARGE according to whether V.sub.IN >V.sub.OUT, V.sub.IN =V.sub.OUT, or V.sub.IN <V.sub.OUT ;

a charging circuit, responsive to the comparator, (i) for drawing a charging current from the power input terminal into the output terminal when the control signal is CHARGE, and (ii) for quenching the drawing of charging current from the power input terminal when the control signal is STANDBY or DISCHARGE, wherein the charging circuit has a first current mirror for drawing the charging current from the power input terminal into the output terminal responsive to a second current mirror which quenches the first current mirror charging current when the control signal is STANDBY or DISCHARGE; and

a shunting circuit, responsive to the comparator, for providing a shunt from the output terminal to ground whose resistance is (i) high when the control signal is CHARGE or STANDBY, and (ii) low when the control signal is DISCHARGE.

2. The operational amplifier of claim 1 further comprising:

a quenching circuit for generating a quench signal which is INACTIVE when the control signal is CHARGE, and ACTIVE when the control signal is STANDBY or DISCHARGE; and

wherein the charging circuit draws the charging current from the power input terminal into the output terminal when the quench signal is INACTIVE and quenches the drawing of charging current from the power input terminal when the quench signal is ACTIVE.

3. The operational amplifier of claim 1 further comprising:

a quenching circuit for generating a quench signal which is INACTIVE when the control signal is CHARGE, and ACTIVE when the control signal is STANDBY or DISCHARGE; and

wherein the shunting circuit provides the shunt from the output terminal to ground whose resistance is high when the quench signal is INACTIVE and low when the quench signal is ACTIVE.

4. The operational amplifier of claim 1 wherein the shunting circuit is stabilized by an idle circuit which continuously provides a constant idle current that is small relative to the charging current to the output terminal.

5. An operational amplifier comprising:

an input terminal for receiving an input signal;

a comparator responsive to said input signal for generating a control signal for controlling said operational amplifier in a CHARGE, STANDBY or DISCHARGE mode;

an output terminal for coupling to a capacitive load;

a first current mirror PT.sub.17 -PT.sub.18 for supplying first and second currents in a proportional relationship;

a current source PT.sub.15 for supplying a third current;

a constant current source NT.sub.15 coupled to said current source for maintaining the sum of the second and third currents constant;

a first transistor PT.sub.16 coupled to said current source for charging the capacitive load coupled to the output terminal at a current proportional to the third current;

a second transistor NT.sub.14 coupled to said current mirror responsive to the input signal for controlling the charging of the capacitive load coupled to the output terminal;

wherein the first current is proportional to a current in the second transistor; and

a third current source P.sub.19 for supplying a constant idling current to the output terminal in a normal-state when the first transistor is not charging the capacitive load coupled to the output terminal.

6. An operational amplifier comprising:

an input terminal for receiving an input signal;

a comparator responsive to said input signal for generating a control signal for controlling said operational amplifier in a CHARGE, STANDBY or DISCHARGE mode;

a first current source for supplying first and second currents in a proportional relationship;

a second current source for supplying a third current;

constant current means coupled to said first and second current sources for maintaining the sum of the second and third currents constant;

a first transistor for charging a load coupled to an output terminal at a current proportional to the third current;

a second transistor for controlling the charging of the load in response to the control signal;

wherein the first current is proportional to a current flowing in the second transistor in response to the input signal; and

a limiting circuit for limiting the first current during discharging.

7. An operational amplifier comprising:

an input terminal for receiving an input signal;

a comparator responsive to said input signal for generating a control signal for controlling said operational amplifier in a CHARGE, STANDBY or DISCHARGE mode;

an output terminal for coupling to a capacitive load;

a first current source for supplying first and second currents in a proportional relationship;

a second current source for supplying a third current;

constant current means coupled to said first and second current sources for maintaining the sum of the second and third currents constant;

a first transistor for charging the capacitive load at a current proportional to the third current;

a second transistor for controlling the charging of the capacitive load coupled to the output terminal in response to the input signal;

wherein the first current is proportional to a current flowing in the second transistor in response to the input signal;

a third current source for supplying a fourth current to the output terminal at least in a normal state, during neither charging nor discharging of the capacitive load; and

a limiting circuit for limiting the first current during discharging.