OPERATIONAL AMPLIFIER WITH ZERO OFFSET

Abstract

A circuit for minimizing a voltage offset between inverting and non-inverting input terminals of an operational amplifier circuit is provided. The circuit includes a chopper circuit connected to the inverting and non-inverting input terminals of the operational amplifier circuit, the chopper circuit including: an amplifier having differential outputs; and a switching circuit for periodically reversing the input terminals to the amplifier and periodically reversing the outputs of the amplifier to provide an output signal having an offset adjustment signal to the operational amplifier circuit to adjust the offset of the operational amplifier circuit.

Description

BACKGROUND OF THE INVENTION

The present invention is directed to operational amplifiers and more particularly to providing an operational amplifier with a zero voltage offset between its input terminals.

The amount of the voltage offset between the input terminals of an operational amplifier is important because a voltage offset in the 1 millivolt range can create a standard deviation of 0.4 amperes current offset in a current sensing power MOSFET (5 m Ohm RDS_ON) in the output stage.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a circuit in which the voltage offset between input terminals of an operational amplifier is reduced, for example, by a factor of 10, thereby to improve the accuracy of the output current sensing in a power stage.

A circuit for minimizing a voltage offset between inverting and non-inverting input terminals of an operational amplifier circuit is provided. The circuit includes a chopper circuit connected to the input terminals of the operational amplifier circuit, the chopper circuit including an amplifier and a switching circuit for periodically reversing the input terminals to the amplifier and periodically reversing outputs of the amplifier to provide an output signal as an offset adjustment signal to the operational amplifier circuit for adjusting the offset of the operational amplifier circuit.

Other features and advantages of the present invention will become apparent from the following description of the invention that refers to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified circuit diagram comprising an operational amplifier and the offset adjustment circuit according to the invention;

FIG. 2 is a diagram showing an implementation of the circuit of FIG. 1;

FIG. 3 is a diagram showing an implementation of the chopper circuit of FIG. 1; and

FIG. 4 is a diagram showing an implementation of the clock generator for driving the chopper circuit of FIG. 1.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

With reference now to the drawings, FIG. 1 shows a power MOSFET Q₂ comprising a sense cell Q_2A and a main current carrying cell Q_2B. The transistor Q₂ drives the load indicated from a potential source V+. The transistor Q₂ is driven by a driver circuit, (not shown) at the terminal GATE.

An operational amplifier 10 is provided to drive a transistor Q₁ to adjust the current in the sense cell Q_2A. It is important that the offset voltage across the amplifier 10 input terminals 10a and 10b be as low as possible in order to adjust the current through the transistor Q₁ so that the current in the transistor Q₂ can be accurately sensed.

In order to do this, a chopper circuit 20 is employed.

As shown in FIG. 1, the operational amplifier 10 has an offset voltage between its inverting and non-inverting input terminals 10a and 10b. The output of the amplifier 10 is connected to a gate of the transistor Q₁ for driving that transistor Q1 to adjust the current in a resistor R_A and thus in the sense cell Q_2A.

As stated above, it is important to minimize the offset voltage between the input terminals 10a and 10b of the operational amplifier 10, connected respectively to isens and source of the transistor Q₂. To this end, i.e., to minimize the offset voltage between the input terminals 10a and 10b of the amplifier 10, the input terminals are coupled to a chopper circuit 20. The chopper circuit 20 comprises a differential amplifier 22, a first input switching circuit 24, a second output switching circuit 25, and an RC noise filter circuit including a resistor R and a capacitor C1.

The first switch 24 is implemented electronically to reverse the isens and source signal inputs to the differential amplifier 22. The second electronic switch 25 reverses the differential outputs. The reversing is performed periodically when initiated by a clock signal. Thus, when the clock signal activates switches 14a and 14b, the isens signal is provided to the non-inverting input and the source signal is connected to the inverting input of the differential amplifier 22. At the output, switch 14c connects the positive output of the differential amplifier 22 to the RC filter.

A second related clock signal is used to activate switches 15a and 15b. These switches reverse the isens and source signal inputs to the differential amplifier 22. At the same time, switch 15c connects the negative output of the amplifier 22 to the RC filter. This input/output switching results in an output of the chopper circuit 20 comprising a positive and negative going square wave B at the input to the RC filter. This signal is filtered by the RC filter into a DC level signal to adjust the offset of the amplifier 10. The output of amplifier 10 then is provided to the gate of the transistor Q₁ to adjust the current in the sense cell Q_2A.

The differential amplifier 22 itself has an offset voltage at its input due to the internal circuitry of the amplifier 22. The offset of the amplifier 22 will be amplified positive or negative in the output signal from the amplifier 22 after the output switch 25. After filtering, the average of the offset of the amplifier 22 will be zero if the duty cycle of the amplifier, set by the clock, is 50%. Other techniques can be used to remove the offset of the amplifier 22, such as switched capacitors or auto calibration.

Since the main amplifier 10 offset signal (across its input terminals) is before the input switch 24 of the chopper circuit 20, this offset signal will be inverted twice (by the switches 24 and 25), so its polarity will always be the same. After filtering by the RC circuit, the chopped waveform B will have an average DC level that will compensate the main amplifier 10 for its offset voltage.

The average output value of the chopper circuit 20 is thus independent of the chopper differential amplifier 22 offset voltage. Therefore, when the offset voltage of the amplifier 10 increases, the chopped output of the differential amplifier 22 increases to drive the offset of the amplifier 10 to a lower value. The circuit 5 operates in a closed loop so that the resulting voltage across the input terminals 10a and 10b of the amplifier 10 is zero.

FIG. 2 illustrates a schematic implementation of the circuit 5 of FIG. 1. The power transistor Q₂ is not shown in FIG. 2. The circuit of FIG. 2 is a normal closed loop amplifier system. The inputs to the amplifier 10 are indicated at isens and source, as in FIG. 1. With the circuit shown, the offset voltage across the inputs of the amplifier 10 is close to zero (output/gain). As discussed above, without the chopper circuit, an offset voltage of about 1 mV of the amplifier 10 would generate a standard deviation of 0.4 A current offset in a current sensing power MOSFET having a 5 m Ohm RDS_ON.

The circuit shown in FIG. 1 is simplified. The circuit of FIG. 2 shows additional components in an actual implementation. For example, the signals isens and source from the main power transistor Q₂ are provided through pass transistors Q₃ and Q₄ respectively, becoming signals sensb and sb provided to the inputs of the chopper circuit 20. The chopper circuit 20 is shown as a block in FIG. 2, and its implementation is shown in FIG. 3.

The circuit of FIG. 2 includes a 50% duty cycle clock circuit 34 (e.g., at 10 kHz or 20 kHz). The chopper circuit 20 inputs sensb and sb are connected to sources of transistors Q₅ and Q₆ of the amplifier 10. The output (OUT) from the chopper circuit 20 effectively corrects the amplifier 10 offset to below 0.1 mV giving less than a 0.04 A offset error in the output stage. This offset measurement is a ten-times improvement in the output current offset. The amplifier 10 output (500 kHz bandwidth) is provided to the gate of the transistor Q₁ via a transistor Q₇. Terminal Ifb is provided with a feedback current proportional to the main power MOSFET Q₂ current.

In the present embodiment, standard techniques, e.g., capacitor switching, cannot be used directly on the amplifier 10 because output signal needs to be available at all times. The circuit 30 only operates when the voltage at the input of the amplifier 10 is offset, with the amplifier used in a closed loop system.

In the circuit of FIG. 2, the size of a current mirror comprising transistors Q₈ and Q₉, which receives the output (OUT) from the chopper circuit 20, is intentionally not matched to create a systematic amplifier offset of 3 mV. The systematic offset is designed to be larger than the maximum offset of the amplifier shown. The chopper circuit 20 adds a current in the transistor Q₈ to compensate for its size, which is small in comparison with the size of the transistor Q₉.

The current mirror circuit, comprising the transistors Q₈ and Q₉, adjusts the amplifier offset. The amplifier output from transistors Q₅ and Q₆ is provided by the transistor Q₇ to the gate of the transistor Q₁.

FIG. 3 illustrates the chopper circuit 20 of FIG. 1. The chopper circuit 20 comprises a number of switches that function as the first and second switches 24, 25 of FIG. 1: input amplifier switch transistors Q₁₀, Q₁₁, Q₁₂, and Q₁₃, and output amplifier switch transistors Q₁₄, Q₁₅, Q₁₆, and Q₁₇. The input switches connect directly or reverse the inputs to the first stage of the chopper amplifier differential input pair transistors Q₁₈, Q₁₉ coupled to a current mirror comprising transistors Q₂₀ and Q₂₁. The differential amplifier comprising the four transistors Q₁₈, Q₁₉, Q₂₀, and Q₂₁ has a gain of about 200. These transistors provide very low bias current without the use of a resistor, i.e., in the range of 0.1 uA, and provide the RC filter together with the capacitor C1. The output switches periodically reverse the differential amplifier outputs.

In particular, in the input switch side, the P-channel transistor Q₁₀ has a gate terminal connected to receive a clock (clkb) signal, a source terminal connected to receive the sensb input signal, and a drain terminal connected to the base of a transistor Q₂₂. The P-channel transistor Q₁₁ has a gate terminal connected to receive a clock (clk) signal, a source terminal connected to receive the sensb input signal, and a drain terminal connected to the base of a transistor Q₂₃. The P-channel transistor Q₁₂ has a gate terminal connected to receive the clk signal, a source terminal connected to receive the sb input signal, and a drain terminal connected to the base of the transistor Q₂₂; and the P-channel transistor Q₁₃ has a gate terminal connected to receive the clkb signal, a source terminal connected to receive the sb signal, and a drain terminal connected to the base of the transistor Q₂₃.

On the output switch side, the chopper circuit 20 further comprises the P-channel transistor Q₁₄ having a gate terminal connected to receive the clk signal, a source terminal connected to drains of the transistors Q₁₉ and Q₂₁, and a drain terminal connected to gate terminals of the transistors Q₁₈ and Q₁₉; the P-channel transistor Q₁₅ having a gate terminal connected to receive the clkb signal, a source terminal connected to the drains of the transistors Q₁₉ and Q₂₁, and a drain terminal connected to the capacitor C1; the P-channel transistor Q₁₆ having a gate terminal connected to receive the clkb signal, a source terminal connected to the drains of the transistors Q₁₈ and Q₂₀, and a drain terminal connected to the gate terminals of the transistors Q₁₈ and Q₁₉; the P-channel transistor Q₁₇ having a gate terminal connected to receive the clkb signal, a source terminal connected to the drains of the transistors Q₁₈ and Q₂₀, and a drain terminal connected to the capacitor C1 of the RC circuit.

These switches are switched at a specified clock frequency of two complementary clock signals clk and clkb provided by the clock circuit 34 (FIGS. 2 and 4) and the inputs and outputs and thus periodically reversed with the signal information maintained.

The chopper circuit 20 also includes a second stage that includes the RC filter circuit, e.g., a 1 ms filter, i.e., a 2.3 pF capacitor C1 charged with very low polarization current of the first stage amplifier in a range of 0.1 uA. A long time constant filter is thus needed. Such filter time constant should be much greater than the period of the 10 kHz or 20 kHz clock oscillator which in turn is much greater than the amplifier chopper bandwidth. A transistor Q₂₄ coupled to a transistor Q₂₅, amplifies the difference between the sensb and sb inputs and generates a current proportional to this difference and provides it to a third stage.

In the third stage, the signal from a drain terminal of the transistor Q₂₄ is converted via a follower transistor Q₂₆ and a resistor R1. The current is mirrored by mirror transistors Q₂₇ and Q₂₈ and is added to a small current leg (the transistor Q₈ of FIG. 2) of the amplifier 10 to adjust the amplifier 10 offset. In a closed loop, the circuit 20 adjusts current in the amplifier 10 so that the input difference (offset) in the main amplifier 10 is zero. When the chopper is used, it results in 0.1 mV standard deviation offset, as compared with a 1 mV standard offset when amplifier 10 is used alone with the same size current mirror transistor pair Q₈, Q₉.

To reduce silicon area, the Miller effect is used. The capacitor C1 is connected between the gate of the transistor Q₂₄ and the drain of transistor Q₂₉. Connecting between the gate of the transistor Q₂₄ and the supply would require a capacitor that is 100 times larger. This explains how a very long time constant is obtained with a very small capacitor C1. Another advantage is that the circuit 20 operates very rapidly until being close to its final state. Therefore, as long as the output of the transistor Q₂₄ is saturated up or down, the Miller effect does not occur and the circuit responds 100 times faster.

The pcap side of C1 is driven indirectly via a follower transistor Q₃₀. Low impedance is needed on this node since the pcap to epi side of the capacitor C1 may be leaky. If connected directly to the drain of the transistor Q₂₄, leakage larger than 0.1 uA, i.e., a bias of the transistor Q₂₄, makes the circuit 20 not functional when hot or in case of large load levels. No leakage problem exists on the poly side of capacitor C1.

Various circuit designs may be used to implement the clock generator 34. In particular, FIG. 4 illustrates a clock generator circuit 34 that drives the chopper circuit. The circuit 34 provides a sawtooth generated by charging a capacitor CAP at 21 or discharging at I. The sawtooth clock signal is amplified by an amplifier 45 having two inputs (A and B). The output of the amplifier is provided to a number of CMOS gain stages 50. A divider is needed for division by two, because in order to remove all offsets, the duty cycle must be exactly 50%. The gain stages 50 feed gate circuits NAND1 and NAND2, followed by inverters 51 and 52 and then into the divide by 2 stage, finally resulting in clock signals clk and clkb.

The output of the clock generator comprises two complementary clock signals clk and clkb out of phase by 180°.

Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention not be limited by the specific disclosure herein.

Claims

1. A circuit for minimizing a voltage offset between inverting and non-inverting input terminals of an operational amplifier circuit, the circuit comprising: a chopper circuit connected to the inverting and non-inverting input terminals of the operational amplifier circuit, the chopper circuit comprising: an amplifier having differential outputs; and a switching circuit for periodically reversing the input terminals to the amplifier and periodically reversing the outputs of the amplifier to provide an output signal comprising an offset adjustment signal to the operational amplifier circuit to adjust the offset of the operational amplifier circuit.

2. The circuit of claim 1, wherein the switching circuit comprises a first switching circuit connecting the input terminals of the operational amplifier circuit to the amplifier and a second switching circuit connecting the output of the amplifier as the offset adjustment signal.

3. The circuit of claim 2, further comprising a clock circuit for providing a clock signal to the switching circuit for periodically operating switches thereof.

4. The circuit of claim 3, further comprising a filter circuit connected at the output of the chopper circuit to provide a DC level signal as the offset adjustment signal.

5. The circuit of claim 4, wherein when the voltage offset between the inverting and non-inverting input terminals of the operational amplifier circuit increases, the offset adjustment signal increases to drive the voltage offset between the inverting and non-inverting input terminals of the operational amplifier circuit to a lower value.

6. The circuit of claim 2, wherein the amplifier comprises a differential amplifier and the second switching circuit provides alternate ones of said outputs to the operational amplifier circuit.

7. The circuit of claim 1, wherein the operational amplifier circuit comprises a current mirror receiving said offset adjustment signal to adjust the offset voltage between the inputs of the operational amplifier circuit.

8. The circuit of claim 7, wherein the current mirror comprises two unmatched transistors, thereby to create a systematic offset of the amplifier circuit, which is compensated by said offset adjustment signal.

9. The circuit of claim 4, wherein the filter circuit has a long time constant compared to a clock period of the clock signal and the clock period is long compared to a period corresponding to the chopper circuit bandwidth.

10. The circuit of claim 9, wherein the filter circuit comprises an RC filter having a resistance and a capacitance, and the capacitance is provided by a capacitor that is connected to a supply voltage by a transistor stage.