Optical disc reproducing apparatus

Abstract

An optical disc reproducing apparatus includes an A/D converter; an asymmetry compensator for detecting 4T sampling signals; a phase locked loop including a frequency detector that counts and detects run-length signals from the digital signals and compensates frequency errors of the digital signals; a binary module including a Viterbi decoder, a slicer, and a minimum T compensator that compensates the digital signal with a minimum signal having a unit cycle; an equalizer; an adaptive level error detector detecting a base level of the Viterbi decoder from both an input signal into the equalizer and an output signal from the Viterbi decoder, and computing a filtering coefficient of the equalizer from the base level; and a signal quality measurer measuring a jitter or an SbER of the digital signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view that illustrates an optical disc reproducing apparatus according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram that illustrates an asymmetry compensator according to an exemplary embodiment of the present invention.

FIG. 3 is a block diagram that illustrates a signal detector of the asymmetry compensator according to an exemplary embodiment of the present invention.

FIG. 4 is a view that illustrates a 4T sampling signal according to an exemplary embodiment of the present invention.

FIG. 5 is a view that illustrates signal waveforms used in the signal detector of the asymmetry compensator according to an exemplary embodiment of the present invention.

FIG. 6 is a view that illustrates a DSV method for an RLL(1,10) code according to an exemplary embodiment of the present invention.

FIG. 7 is a block diagram that illustrates a frequency detector according to an exemplary embodiment of the present invention.

FIG. 8 is a view that illustrates a run-length distribution density to a channel coding feature of the optical disc reproducing apparatus according to an exemplary embodiment of the present invention.

FIG. 9 is a view that illustrates run-length boundaries in the run-length distribution density.

FIG. 10 is a view that illustrates a shift of a run-length signal distribution in the run-length distribution density when the frequency of a sampling clock is lower than a target frequency.

FIG. 11 is a view that illustrates a relation among a real signal count, a predicted signal count, and a threshold value when the run-length signal distribution is shifted as shown in FIG. 10.

FIG. 12 is a view that illustrates a shift of a run-length signal distribution in the run-length distribution density when the frequency of a sampling clock is higher than a target frequency.

FIG. 13 is a view that illustrates a relation among a real signal count, a predicted signal count, and a threshold value when the run-length signal distribution is shifted as shown in FIG. 12.

FIG. 14 is a block diagram that illustrates a channel identifier of an adaptive level error detector according to an exemplary embodiment of the present invention.

FIG. 15 is a view that illustrates a trellis diagram of a 5-tap Viterbi decoder of a (1,7) code according to an exemplary embodiment of the present invention.

FIG. 16 is a view that illustrates a level estimation result by the Viterbi decoder in FIG. 15.

FIG. 17 is a block diagram that illustrates an SbER controller of a signal quality measurer according to an exemplary embodiment of the present invention.

FIG. 18 is a view that illustrates a reference table according to an exemplary embodiment of the present invention.

FIG. 19 is a view that illustrates a jitter controller according to an exemplary embodiment of the present invention.

FIG. 20 is a view that illustrates a jitter detector of the jitter controller according to an exemplary embodiment of the present invention.

FIG. 21 is a view that illustrates a calculation method of a jitter value according to an exemplary embodiment of the present invention.

FIG. 22 is a view that illustrates a cycle examiner of the jitter controller according to an exemplary embodiment of the present invention.

FIG. 23 is a view that illustrates a timing diagram of a counter of the cycle examiner according to an exemplary embodiment of the present invention.

Claims

1. An optical disc reproducing apparatus comprising: an A/D converter which converts analog RF signals, obtained from an optical disc, to digital signals;an asymmetry compensator which detects 4T sampling signals, a polarity of which changes four-times in a half cycle among the digital signals, and corrects a level of the digital signals according to counted asymmetric error values;a phase locked loop which includes a frequency detector that counts and detects run-length signals from the digital signals and corrects frequency errors of the digital signals;a binary module which includes a Viterbi decoder that detects binary data from the digital signals, a slicer which determines the binary data depending on a predetermined threshold value, and a minimum T compensator which corrects the digital signal with a minimum signal having a unit cycle; an equalizer which equalizes a specific frequency of the digital signal;an adaptive level error detector which detects a base level of the Viterbi decoder from both an input signal into the equalizer and an output signal from the Viterbi decoder, and computes a filtering coefficient of the equalizer from the base level; anda signal quality measurer which measures a jitter or an SbER of the digital signal.

2. The apparatus of claim 1, wherein the asymmetry compensator detects the 4T sampling signals, a polarity of which changes four-times in a half cycle among the digital signals, calculates asymmetric error values from the 4T sampling signals, counts the asymmetric error values, and corrects a level of the digital signals according to the counted asymmetric error values.

3. The apparatus of claim 1, wherein the asymmetry compensator adds first, fourth, fifth, and eighth digital signals among the 4T sampling signals and then computes asymmetric error values.

4. The apparatus of claim 1, wherein the asymmetry compensator outputs variable frequency oscillator (VFO) detection signals while VFO signals are reproduced from the optical disc, and outputs the received digital signals as the 4T sampling signals while the VFO detection signal is outputted.

5. The apparatus of claim 4, wherein the asymmetry compensator measures an elapsed time from a point when a header information is reproduced, and when the counted time exceeds a predetermined time, outputs the VFO detection signal for a predetermined time.

6. The apparatus of claim 1, wherein the frequency detector counts and detects run-length signals from the sampling digital signals during a frequency detection cycle according to a run-length distribution density depending on a channel coding feature, generates frequency errors during the frequency detection cycle through the count value of the run-length signals and predetermined threshold values, and corrects the frequency errors of the digital signals.

7. The apparatus of claim 6, wherein the predetermined threshold values are critical points determined based on the run-length distribution density that appears in a run-length region during the frequency detection cycle.

8. The apparatus of claim 6, wherein the run-length region corresponds to at least one xT run-length signal, where the x is an integer ranging from 2 to n, and n is determined by the maximum run-length of the optical discs.

9. The apparatus of claim 6, wherein the frequency detector detects most frequently generated run-length signals from the digital signals according to a predicted run-length distribution density.

10. The apparatus of claim 9, wherein the predetermined threshold value is the predicted distribution density of the most frequently generated run-length signals and wherein the frequency detector generates the frequency errors according to signals obtained by subtracting the run-length signal count values from the predetermined threshold value.

11. The apparatus of claim 1, wherein the phase locked loop further includes a phase detector correcting phase errors of the digital signals.

12. The apparatus of claim 1, wherein a partial response (PR) type of the Viterbi decoder is PR (a, b, c, d, e).

13. The apparatus of claim 1, wherein the adaptive level error detector detects a base level of the Viterbi decoder from both an input signal into the equalizer and an output signal from the Viterbi decoder, and computes a filtering coefficient of the equalizer from the base level, the input signal of the equalizer, and the output signal of the equalizer.

14. The apparatus of claim 13, wherein the adaptive level error detector generates a selection signal by multiplexing the output signals of the Viterbi decoder, the output signals being split and delayed by a number of delays which are less than the number of taps of the Viterbi decoder.

15. The apparatus of claim 13, wherein the adaptive level error detector detects the base level value by dividing a difference between a delayed input signal and a former level value by a constant, and then adding the former level value to the result of the difference between the delayed input signal and the former level value.

16. The apparatus of claim 15, wherein the adaptive level error detector computes a filtering coefficient of the equalizer according to a difference between an output signal of the equalizer and the detected base level value.

17. The apparatus of claim 13, wherein the adaptive level error detector detects the base level value by using a least mean square method.

18. The apparatus of claim 17, wherein the adaptive level error detector computes a filtering coefficient of the equalizer based on the following equation: Wk+1=Wk+2*μ*ek*Xk where ‘Wk+1’, ‘Wk’, ‘μ’, ‘ek’, and ‘Xk’ indicate the filtering coefficient of the equalizer, a former coefficient of the equalizer, a tracking velocity, a difference between an output signal of the equalizer and the detected level, and an input signal of the equalizer, respectively.

19. The apparatus of claim 1, wherein the Viterbi decoder has a 5-tap type and a 16 level, and wherein the binary module supports both RLL(1,10) and RLL(2,10) codes, and selectively uses an input of the adaptive level error detector.

20. The apparatus of claim 1, wherein the minimum T compensator corrects the digital sampling signal with a minimum signal having a unit cycle when the digital sampling signal has a smaller cycle than a unit cycle of the minimum signal corresponding to a code of the optical disc.

21. The apparatus of claim 20, wherein the minimum T compensator controls a path of a 1T digital signal through a switch when the unit cycle T of the minimum signal is 2T, and controls paths of the 2T and 1T digital signals through the switch when the unit cycle T of the minimum signal is 3T.

22. The apparatus of claim 1, wherein the signal quality measurer includes an SbER controller computing quality characteristics of the digital signal from the output signals of both the equalizer and the Viterbi decoder.

23. The apparatus of claim 22, wherein the SbER controller computes quality characteristics of the digital signal by adding products of a probability (CT) that a pattern T of the digital signal occurs, a probability (erf(0)) that the pattern T is detected corresponding to a pattern F of the digital signal, and a Hamming distance between the pattern T and the pattern F.

24. The apparatus of claim 1, wherein the apparatus supports a HD-DVD with blue ray wavelength, a DVD with red ray wavelength, and a CD with IR wavelength.

25. The apparatus of claim 1, wherein the signal quality measurer includes a jitter controller that detects a jitter between a system clock and a digital signal, outputs an enable signal when a cycle of the digital signal satisfies a defined condition, and executes a calculation to detect jitter according to the enable signal.

26. The apparatus of claim 25, wherein the jitter controller computes the jitter of the digital signal by outputting a delayed input signal that the digital signal is delayed by the system clock and outputting a sign detection signal indicating a point when a sign of the digital signal shifts.

27. The apparatus of claim 26, wherein the jitter controller detects most significant bits from both the delayed signal and the digital signal, and outputs the sign detection signal after an XOR operation of the detected most significant bits.

28. The apparatus of claim 26, wherein the jitter controller computes a first absolute value of the digital signal and a second absolute value of the delayed input signal, selects one from a zero and a value dividing a smaller absolute value by a sum of both absolute values, and outputs by multiplying the selected value and a predetermined value.

29. An optical disc reproducing apparatus for correcting asymmetric errors in data reproduced from optical discs, comprising: an asymmetry compensator which detects sampling signals from received digital signals, the sampling signal being determined when a change in polarity occurs in the digital signals, the digital signals being sampled a predetermined number of times in a sampling region every half cycle of an analog signal, wherein the predetermined number of times is at least one; andwherein the asymmetry compensator calculates asymmetric error values from the sampling signals, counts the error values, and corrects a level of the digital signals based on the counted asymmetric error values.

30. The apparatus of claim 29 further comprising an A/D converter which converts RF signals obtained from an optical disc to the digital signals.

31. The apparatus of claim 29, wherein the predetermined number of times the digital signal is sampled corresponds to 4T sampling signals.

32. The apparatus of claim 31, wherein the asymmetry compensator adds first, fourth, fifth, and eighth digital signals among the 4T sampling signals to produce a sum, and then computes asymmetric error values based on the sum.

33. The apparatus of claim 29, further comprising a phase locked loop which includes a frequency detector that counts and detects run-length signals from the digital signals and corrects frequency errors of the digital signals.

34. The apparatus of claim 33, wherein the frequency detector counts and detects run-length signals from the sampling digital signals during a frequency detection cycle according to a run-length distribution density depending on a channel coding feature, generates frequency errors during the frequency detection cycle through the count value of the run-length signals and predetermined threshold values, and corrects the frequency errors of the digital signals.

35. The apparatus of claim 29, further comprising a binary module which includes a Viterbi decoder that detects binary data from the digital signals, a slicer which determines the binary data depending on a predetermined threshold value, and a minimum T compensator which corrects the digital signal with a minimum signal having a unit cycle; an equalizer which equalizes a specific frequency of the digital signal; andan adaptive level error detector which detects a base level of the Viterbi decoder from both an input signal into the equalizer and an output signal from the Viterbi decoder, and computes a filtering coefficient of the equalizer from the base level.

36. The apparatus of claim 35, wherein a partial response (PR) type of the Viterbi decoder is PR (a, b, c, d, e).

37. The apparatus of claim 35, wherein the adaptive level error detector detects a base level of the Viterbi decoder from both an input signal into the equalizer and an output signal from the Viterbi decoder, and computes a filtering coefficient of the equalizer from the base level, the input signal of the equalizer, and the output signal of the equalizer.

38. The apparatus of claim 35, wherein the Viterbi decoder has a 5-tap type and a 16 level, and wherein the binary module supports both RLL(1,10) and RLL(2,10) codes, and selectively uses an input of the adaptive level error detector.

39. The apparatus of claim 35, wherein the minimum T compensator corrects the digital sampling signal with a minimum signal having a unit cycle when the digital sampling signal has a smaller cycle than a unit cycle of the minimum signal corresponding to a code of the optical disc.

40. The apparatus of claim 35, further comprising a signal quality measurer which measures a jitter or an SbER of the digital signal.

41. The apparatus of claim 29, wherein the apparatus supports a HD-DVD with blue ray wavelength, a DVD with red ray wavelength, and a CD with IR wavelength.

42. The apparatus of claim 29, wherein the asymmetry compensator executes asymmetric error compensation in response to one of multiple run-length limited code environments.