Optical disc reproducing apparatus

Abstract

An optical disc reproducing apparatus includes an analog-to-digital (A/D) converter which converts an analog signal obtained from an optical disc to a digital signal; an asymmetry compensator which detects and corrects an offset of the digital signal; a phase locked loop (PLL) which estimates a clock of the digital signal and compensates for a frequency error; a binary module which converts the digital signal to binary data; an equalizer which equalizes a particular frequency of the digital signal; and a channel identifier which detects a reference level of the binary module, based on an input signal of the equalizer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects of the present invention will become apparent and more readily appreciated from the following detailed description, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a block diagram illustrating an optical disc reproducing apparatus according to an exemplary embodiment of the present invention;

FIG. 2 is a block diagram illustrating an asymmetry signal compensation loop of an asymmetry compensator according to an exemplary embodiment of the present invention;

FIG. 3 is a block diagram illustrating an asymmetry counter according to an exemplary embodiment of the present invention;

FIG. 4 is a graph illustrating an operation principle of a zero crossing detector according to an exemplary embodiment of the present invention;

FIG. 5 is a graph illustrating an operation principle of a decimal asymmetry detector according to an exemplary embodiment of the present invention;

FIG. 6 is a diagram illustrating a detailed operation principle of a decimal asymmetry detector according to an exemplary embodiment of the present invention;

FIG. 7 is a block diagram illustrating an asymmetry counter according to another exemplary embodiment of the present invention;

FIG. 8 is a graph illustrating a method of detecting an asymmetry signal of a two times resolution input signal by a zero crossing section detector according to another exemplary embodiment of the present invention;

FIG. 9 is a diagram illustrating an exemplary embodiment in a two times resolution input signal by a zero crossing section detector according to another exemplary embodiment of the present invention;

FIG. 10 is a graph illustrating a method of detecting an asymmetry signal of a four times resolution input signal by a zero crossing section detector according to another exemplary embodiment of the present invention;

FIG. 11 is a diagram illustrating an exemplary embodiment in a four times resolution input signal by a zero crossing section detector according to another exemplary embodiment of the present invention;

FIG. 12 is a block diagram illustrating an equalizer according to an exemplary embodiment of the present invention;

FIG. 13 is a graph illustrating an interpretation sample of an interpretation sample value sequence R and an interpolation interpretation sample of an interpolation interpretation sample value sequence RR according to each case of run-length is 2T, 3T, and 4T according to an exemplary embodiment of the present invention;

FIG. 14 is a block diagram illustrating a channel identifier according to an exemplary embodiment of the present invention.

FIG. 15 is a diagram illustrating a trellis diagram of a 5-tap Viterbi decoder of a (1,7) code according to an exemplary embodiment of the present invention.

FIG. 16 is a diagram illustrating a level estimation result by the Viterbi decoder in FIG. 15.

FIG. 17 is a block diagram illustrating a simulated bit error rate (SbER) controller of a signal quality measurer according to an exemplary embodiment of the present invention.

FIG. 18 is a diagram illustrating a reference table according to an exemplary embodiment of the present invention.

FIG. 19 is a block diagram illustrating a jitter controller according to an exemplary embodiment of the present invention.

FIG. 20 is a block diagram illustrating a jitter detector of the jitter controller according to an exemplary embodiment of the present invention.

FIG. 21 is a diagram illustrating a calculation method of a jitter value according to an exemplary embodiment of the present invention.

FIG. 22 is a block diagram illustrating a cycle examiner of the jitter controller according to an exemplary embodiment of the present invention.

FIG. 23 is a diagram illustrating a timing diagram of a counter of the cycle examiner according to an exemplary embodiment of the present invention.

Claims

1. An optical disc reproducing apparatus comprising: an analog-to-digital (A/D) converter which converts an analog signal obtained from an optical disc to a digital signal;an asymmetry compensator which detects and corrects an offset of the digital signal;a phase locked loop (PLL) which estimates a clock of the digital signal and compensates for a frequency error;a binary module which converts the digital signal to binary data;an equalizer which equalizes a particular frequency of the digital signal; anda channel identifier which detects a reference level of the binary module, based on an input signal of the equalizer.

2. The apparatus of claim 1, wherein the asymmetry compensator comprises: a zero crossing detector which detects a zero crossing point by comparing each sign of two consecutive sample signals with respect to the digital signal;a decimal asymmetry detector which computes a jitter value used for an asymmetric waveform level compensation of the digital signal; anda count determinator which determines a coefficient quantity by using a sign bit of a sample signal according to the zero crossing point, the jitter value, and a system clock cycle.

3. The apparatus of claim 2, wherein the decimal asymmetry detector computes the jitter value by dividing a system clock by a value which is obtained by multiplying a greater value and a smaller value of a size of the sample signals with respect to the zero crossing point, and multiplying a result of the division and the smaller value.

4. The apparatus of claim 2, wherein the count determinator computes the coefficient quantity by multiplying an offset to a right of a decimal point and −2, when the zero crossing point exists among the sample signals, the size of the sample signal before the zero crossing point is greater among the sample signals, and the sign of the sample signal after the zero crossing point is negative.

5. The apparatus of claim 2, wherein the count determinator computes the coefficient quantity by multiplying an offset to a right of a decimal point and 2, when the zero crossing point exists among the sample signals, the size of the sample signal before the zero crossing point is greater among the sample signals, and the sign of the sample signal after the zero crossing point is positive.

6. The apparatus of claim 2, wherein the count determinator computes the coefficient quantity by adding −2 and a value which is obtained by multiplying an offset to a right of a decimal point and 2, when the zero crossing point exists among the sample signals, the size of the sample signal after the zero crossing point is greater among the sample signals, and the sign of the sample signal after the zero crossing point is negative.

7. The apparatus of claim 2, wherein the count determinator computes the coefficient quantity by adding 2 and a value which is obtained by multiplying an offset to a right of a decimal point and −2, when the zero crossing point exists among the sample signals, the size of the sample signal after the zero crossing point is greater among the sample signals, and the sign of the sample signal after the zero crossing point is positive.

8. The apparatus of claim 2, wherein the count determinator computes the coefficient quantity as −1, when the zero crossing point does not exist among the sample signals and the signs of the sample signals around the zero crossing point are all negative.

9. The apparatus of claim 2, wherein the count determinator computes the coefficient quantity as 1, when the zero crossing point does not exist among the sample signals and the signs of the sample signals around the zero crossing point are all positive.

10. The apparatus of claim 1, wherein the asymmetry compensator comprises: a zero crossing detector which detects the zero crossing point by comparing each sign of two consecutive sample signals with respect to the digital signal;a zero crossing section detector which detects a section value in which the zero crossing point is located; anda count determinator which determines the coefficient value by the detected section value.

11. The apparatus of claim 10, wherein the zero crossing section detector detects the section value in which the zero crossing point is located by dividing a system clock cycle by n.

12. The apparatus of claim 10, wherein the count determinator divides the system clock cycle by n, and when a section in which the zero crossing point is located is a kth section from the sample signal before the zero crossing point, the count determinator determines that the coefficient value is n+k−2 in the sample signal before the zero crossing point, and determines that the coefficient quantity is n−k in the sample signal after the zero crossing point.

13. The apparatus of claim 1, wherein the PLL detects a frequency only when a maximum T with an identical cycle is consecutively outputted twice among the maximum T's which are consecutively outputted from a synchronous pattern of the digital signal.

14. The apparatus of claim 1, wherein the equalizer comprises: an interpolator which generates an interpolation interpretation sample value sequence by sampling the digital signal according to a clock timing of a certain channel clock signal;an amplitude limiter which generates an amplitude limit interpretation sample value sequence by limiting the interpolation interpretation sample value sequence by a certain amplitude limit value;a filter which outputs a result which is obtained by giving and adding each weight between the amplitude limit interpretation sample value among the amplitude limit interpretation sample value sequence;a delay line which generates a delay interpretation sample value sequence by delaying the interpolation interpretation sample value sequence; andan adder which generates an equalizer compensation interpretation sample value sequence by adding the delay interpretation sample value sequence and an output of the filter.

15. The apparatus of claim 14, wherein the amplitude limit interpretation sample value sequence is generated to be greater than a maximum value of a signal level in a section having a shortest level inversion interval in the digital signal.

16. The apparatus of claim 15, wherein the shortest level inversion interval has a period of two times one clock cycle in the channel clock signal.

17. The apparatus of claim 14, wherein the interpolator generates the interpolation interpretation sample value sequence by sampling the digital signal according to a clock timing having twice a frequency of the channel clock signal.

18. The apparatus of claim 14, wherein the filter increases a value of a high section component in the amplitude limit interpretation sample value sequence.

19. The apparatus of claim 18, wherein the high section component is a component having a shortest level inversion interval in the amplitude limit interpretation sample value sequence.

20. The apparatus of claim 1, wherein the channel identifier detects the reference level based on the input signal of the equalizer inputted for a certain time, and detects the reference level by computing an average of an input signal of the equalizer and a former reference level value.

21. The apparatus of claim 20, wherein the channel identifier comprises: a selection signal generator which generates a selection signal from an output signal of the binary module;a level selector which selects a level to be detected from an input signal of the equalizer according to the selection signal; andan average filter which generates a new level value with respect to the selected level, based on a former level value and a level value of an input signal inputted as the selected level.

22. The apparatus of claim 21, wherein the selection signal generator generates the selection signal by multiplexing a signal that delays an output signal of the binary module by a same amount as taps of a Viterbi.

23. The apparatus of claim 21, wherein the average filter is a low pass filter.

24. The apparatus of claim 21, wherein the average filter detects the reference level value by subtracting a former level value from the delayed input signal, dividing a result of the subtraction by a constant, and adding the former level value and a result of the division.

25. The apparatus of claim 1, wherein the binary module comprises: a minimum T compensator which compensates the digital signal with a minimum T signal having a certain unit cycle;a Viterbi decoder which detects the binary data from the digital signal; anda slicer which determines the binary data according to a threshold.

26. The apparatus of claim 25, wherein a partial response (PR) type of the Viterbi decoder is PR (a, b, c, d, e).

27. The apparatus of claim 25, wherein the minimum T compensator compensates a digital sampling signal with a minimum signal having the unit cycle when the digital sampling signal has a lower cycle than the unit cycle of the minimum signal corresponding to a code of the optical disc.

28. The apparatus of claim 27, wherein the minimum T compensator controls a path of the 1 T digital signal through a switch when the unit cycle T of the minimum signal is 2T, and controls paths of the 2T and 1T digital signals through the switch when the unit cycle T of the minimum signal is 3T.

29. The apparatus of claim 1, further comprising: a signal quality measurer which measures a jitter or a simulated bit error rate (SbER) of the digital signal.

30. The apparatus of claim 29, wherein the signal quality measurer includes an SbER controller which computes quality characteristics of the digital signal using output signals of both the equalizer and the Viterbi decoder.

31. The apparatus of claim 30, wherein the SbER controller computes quality characteristics of the digital signal by adding products of a probability (CT) that a pattern T of the digital signal occurs, a probability (erf(0)) that the pattern T is detected corresponding to a pattern F of the digital signal, and a Hamming distance between the pattern T and the pattern F.

32. The apparatus of claim 30, wherein the signal quality measurer includes a jitter controller which detects a jitter between a system clock and a digital signal, outputs an enable signal when a cycle of the digital signal satisfies a defined condition, and executes a calculation to detect jitter according to the enable signal.

33. The apparatus of claim 32, wherein the jitter controller computes the jitter of the digital signal by outputting a delayed input signal, obtained by delaying the digital signal by the system clock, and outputting a sign detection signal indicating a point when a sign of the digital signal shifts.

34. The apparatus of claim 33, wherein the jitter controller detects most significant bits from both the delayed input signal and the digital signal, and outputs the sign detection signal after an XOR operation of the detected most significant bits.

35. The apparatus of claim 33, wherein the jitter controller computes a first absolute value of the digital signal and a second absolute value of the delayed input signal, selects a zero or a value obtained by dividing a smaller absolute value of the first absolute value and the second absolute value by a sum of both absolute values, and outputs a value obtained by multiplying the selected value and a certain value.