BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram showing a manner in which a plurality of values are represented by varying the length of a multilevel information pit as measured in a direction along a track, wherein corresponding 3-bit binary values are also shown.
FIG. 2 is a diagram showing the amplitude distribution of each level of a reproduced multilevel information signal.
FIG. 3 is a block diagram showing a multilevel data decoder according to a conventional technique.
FIG. 4 is a block diagram showing an optical disk apparatus according to an embodiment of the present invention.
FIG. 5 is a block diagram showing a reproduced signal correction circuit according to an embodiment of the present invention.
FIG. 6 is a flow chart showing a process performed by a reproduced signal correction circuit.
FIG. 7 shows a learning table stored in a learning data memory according to an embodiment of the present invention.
FIG. 8 is a diagram showing an example of a convolutional encoder according to an embodiment of the present invention.
FIG. 9 is a table indicating a rule of a bit conversion performed by a mapping circuit according to an embodiment of the present invention.
FIG. 10 is a table indicating a rule of conversion between binary data and octal data performed by a multilevel converter according to an embodiment of the present invention.
FIG. 11 is a diagram schematically showing a multilevel-data level detector according to an embodiment of the present invention.
FIG. 12 is a diagram showing an error power calculation circuit according to an embodiment of the present invention.
FIG. 13 is a table showing combinations of a metric and error power according to an embodiment of the present invention.