Patent Application
20220109508
The disclosure relates to an optical receiver that receives optical signals in a station-side device in an optical communication system, and the station-side device.
In recent years, a point-to-multipoint access optical communication system called a passive optical network (PON) system that allows a plurality of users to share a single optical fiber has been widely used. A PON system consists of a single optical line terminal (OLT), which is a station-side device, optical network units (ONUs), which are a plurality of subscriber-side terminal devices, an optical star coupler, which is a passive element connecting the OLT and the ONUs, and optical fibers connecting the CLT, the ONUs, and the optical star coupler.
In such a PON system, ONUs are installed in locations at different distances from an OLT. Thus, light reception levels in the OLT of optical signals transmitted by the ONUs vary from received packet to received packet received by the OLT from the ONUs. Therefore, an optical receiver of the OLT is required to have a wide dynamic range characteristic for reproducing packets of different light reception levels with stability and at high speed. Thus, the optical receiver of the OLT includes an automatic gain control (AGC) circuit that rapdly changes the conversion gain of a transimpedance amplifier that converts a photocurrent output from a light-receiving element into a voltage signal to a proper gain according to the light reception level.
The AGC circuit has a time constant from the start of adjustment of the conversion gain with the start of reception of a packet signal to the convergence of the conversion gain. Thus, the OLT optical receiver requires a predetermined time to perform stable data reproduction after the start of reception of a packet signal. Here, the time required for the conversion gain to converge is limited according to the transmission speed of the system. For example, in 1.25-Gbit/s up G-PON systems standardized in ITU-T G.984 series, 2.5-Gbit/s up XG-PON systems standardized in ITU-T G.987 series, and 10-Gbit/s up XGS-PON systems standardized in ITU-T G.9807 series, the conversion gain needs to be converged in some tens of nanoseconds or less, and a high-speed AGC function is required.
Here, each packet signal consists of an overhead field and a data field. The overhead field is a “01” alternating fixed code string, and the data field is a random code string. For the AGC function of the OLT optical receiver, it is an ideal operation to converge at a high speed in the overhead field and hold a fixed gain in the data field. For the AGC function implementing this function, various methods have been proposed. For example, the invention described in Japanese Patent No. 6058140 includes a gain control circuit that controls conversion gain on the basis of the bottom voltage of a voltage signal output from a transimpedance amplifier, and a convergence determination circuit that determines whether the gain control circuit is in a convergent state. When the convergence determination circuit detects a transition to the convergent state, the gain control circuit holds the conversion gain at the time of the transition to the convergent state.
In the invention described in Japanese Patent No. 6058140, when it is detected that the output voltage of an operational amplifier constituting a circuit that detects the bottom voltage of a voltage signal output from the transimpedance amplifier, that is, the cathode-side voltage of a diode connected to an output terminal of the operational amplifier has risen with the convergence of AGC, it is determined that a transition to the convergent state has been made, and the operation of the operational amplifier is stopped, and accordingly, the control of the conversion gain is stopped.
However, depending on operating conditions such as temperature and power supply voltage, and a combination of the output voltage of the transimpedance amplifier and bias voltage, there may be a case where the output voltage of the operational amplifier does not increase even though the gain of the operational amplifier has decreased, and the AGC circuit is operating. In this case, the convergence determination circuit cannot detect a transition to the convergent state. Consequently, when identical digits are consecutively input to the optical receiver in the data field, the AGC circuit unnecessarily operates to change the conversion gain, resulting in the problem of an increased bit error rate.
The disclosure has been made in view of the above, and an object thereof is to provide an optical receiver capable of preventing an unnecessary change of the conversion gain of a transimpedance amplifier after the adjustment of the conversion gain of the transimpedance amplifier has been completed.
In order to solve the above-stated problem and achieve the object, an optical receiver according to the disclosure includes a transimpedance amplifier to convert a current signal output from a light-receiving element to receive an optical signal into a voltage signal, the transimpedance amplifier having a variable conversion gain when performing the conversion; a gain control circuit to detect a bottom voltage of the voltage signal output from the transimpedance amplifier and control the conversion gain of the transimpedance amplifier based on a result of the detection; and a signal detect on circuit to output a signal detection signal indicating a signal detection result of whether or not an optical signal is being received, wherein, when the signal detection signal indicates a transition from a non-reception state that is a state in which an optical signal is not being received to a reception state that is a state in which an optical signal is being received, the gain control circuit terminates the control of the conversion gain and holds a value of the conversion gain at a point in time when the control of the conversion gain is terminated.
Hereinafter, an optical receiver and a station-side device according to embodiments of the disclosure will be described in detail with reference to the drawings.
An optical communication system 300 according co the present embodiment is a PON system in the form of point-to-multipoint optical communication. As illustrated in
The OLT 100 includes an optical receiver 1. In
In the optical communication system 300, upstream communications from the ONUs 200 to the OLT 100 are performed by time-division multiplexing. That is, the OLT 100 allocates times at which data transmission is permitted to the ONUs 200 based on the data amounts of data scheduled to be transmitted by the ONUs 200 or the like, so that the collision of optical signals transmitted by the ONUs 200 is prevented. The ONUs 200 transmit data at the respective allocated times.
The transimpedance amplifier 12 includes an operational amplifier 121, a fixed resistor 122, and a variable resistance element 123. In the transimpedance amplifier 12, the resistance values of the fixed resistor 122 and the variable resistance element 123 connected in parallel to the operational amplifier 121 determine the conversion gain in converting a current signal into a voltage signal. The variable resistance element 123 is formed of, for example, a field-effect transistor (FET) or the like, and is a circuit element whose resistance value can be controlled by an input voltage. The variable resistance element 123 receives the input of a gain control signal generated by the gain control circuit 13 based on the bottom voltage of a voltage signal. Thus, the transimpedance amplifier 12 can output a voltage signal subjected to current-to-voltage conversion by the conversion gain controlled on the basis of the bottom voltage.
The gain control circuit 13 includes an operational amplifier 131, a diode 132 with a cathode terminal connected to an output terminal of the operational amplifier 131, a capacitor 133 with one end connected to an anode terminal of the diode 132, and a switch 134 connected in parallel to the capacitor 133. An output terminal of the transimpedance amplifier 12 is connected to a non-inverting input terminal of the operational amplifier 131, and the anode terminal of the diode 132 is connected to an inverting input terminal of the operational amplifier 131. The capacitor 133 is charged by the voltage of the anode terminal of the diode 132. The switch 134 operates according to the state of the reset signal input from the outside (hereinafter referred to as an external reset signal) to release the charge stored in the capacitor 133. Here, the external reset signal is a pulse signal output from any circuit that detects the end of a packet signal. When the end of a packet signal is detected, a pulse signal is input to the switch 134. The external reset signal is a signal indicating that the input of a packet signal has been completed. When the external reset signal is input, that is, when the input of a packet signal is completed, the switch 134 goes into the ON state and releases the charge stored in the capacitor 133.
The signal detection circuit 16 is a circuit that outputs as the signal detection signal a high voltage when a received packet signal is present and a low voltage when no received packet signal is present. For example, when the amplitude of an input signal becomes a predetermined value, the signal deter ion circuit 16 determines that a received packet signal is present. At this time, to prevent erroneous detection, the signal detection circuit 16 may determine that a received packet is present when a state in which the amplitude has become a predetermined value has continued for a certain period of time, or to achieve instantaneous signal detection, the signal detection circuit 16 may determine that a received packet is present when a transition is once made to a state in which the amplitude has become a predetermined value. The signal detection circuit 16 may be a circuit that continues to output a high signal until the reset signal is input even when a received packet signal is no longer present after starting the output of the high voltage. In this case, the optical receiver 1 is configured such that the external reset signal is also input to the signal detection circuit 16. If the relationship between high and low in the output voltage is switched, that is, if the signal detection circuit 16 outputs the low voltage when a received packet signal is present, there is no problem as long as the determination circuit 14 downstream thereof performs operation described later.
The determination circuit 14 starts to output a low voltage on the rising edge of the external reset signal and starts to output a high voltage on the rising edge of the signal detection signal. That is, the determination circuit 14 is a logic circuit that outputs a signal that becomes the high voltage when the signal detection circuit 16 detects a signal and becomes the low voltage when the rising edge of the external reset signal is detected. Here, the low voltage means an operation start signal to the operational amplifier 131, and the high voltage means an operation stop signal to the operational amplifier 131. The signal output from the determination circuit 14 is input to a shutdown terminal of the operational amplifier 131. In the following description, the signal output from the determination circuit 14 is referred to as a convergence determination signal. In a configuration where the signal detection circuit 16 outputs the low voltage when a received packet is present, the determination circuit 14 operates to start to output the high voltage on the falling edge of the signal detection signal.
Based on the convergence determination signal input from the determination circuit 14, in a non-convergent state, that is, when the convergence determination signal has the low voltage, the gain control circuit 13 operates to detect the bottom voltage following an input voltage waveform. On the other hand, in a convergent state, that is, when the convergence determination signal has the high voltage, the gain control circuit 13 stops the operation of following an input voltage waveform, and operates to hold the conversion gain of the transimpedance amplifier 12 at a point in time of a transition from the non-convergent state to the convergent state regardless of the input voltage waveform.
The operation of each part of the optical receiver 1 configured as described above will be described with reference to timing charts in
As illustrated in
Packet signals input from the ONUs 200 to the OLT 100 are transmitted by time division multiplexing so that they do not collide with each other. The external reset signal as illustrated in
When the optical receiver 1 receives the next packet signal, as illustrated in
When the voltage at point C decreases, the resistance value of the variable resistance element 123 decreases, and the conversion gain of the transimpedance amplifier 12 also decreases, so that the amplitude of the voltage waveform at point A transitionally decreases in the operation. When the voltage at point C becomes equal to the bottom voltage at point A, no current flows through the diode 132, and no charge is stored in the capacitor 133 of the gain control circuit 13, so that the voltage at point C does not decrease further.
The anode terminal of the diode 132 is connected to the inverting input terminal of the operational amplifier 131. That is, the voltage at point C is input to the inverting input terminal of the operational amplifier 131. Thus, the voltage at point B indicating the voltage output from the operational amplifier 131 decreases after the reception of the packet signal like the voltage at point C. When the voltage at point C becomes equal to the bottom voltage value at point A, the voltage at point B starts to rise if the operational amplifier 131 operates normally. However, depending on operating conditions such as temperature and power supply voltage, and a combination of the output voltage of the transimpedance amplifier 12 and bias voltage, there may be a case where the voltage at point B does not rise even though the gain of the operational amplifier 131 has decreased, and the voltage at point C has become equal to the bottom voltage value at point A as illustrated in
On the other hand, the signal detection circuit 16 determines whether or not a signal is present, based on the amplitude of the output signal from the transimpedance amplifier 12 or the amplitude of the output signal from the transimpedance amplifier 12 after being amplified, and outputs the high voltage when it is determined that a signal is present. For example, when the amplitude of the signal becomes a predetermined value, and that state continues for a predetermined period of time, the signal detection circuit 16 determines that a signal is present and outputs the high voltage. When the signal detection circuit 16 outputs the high voltage in the preamble field as illustrated in
As described above, the optical receiver 1 according to the present embodiment determines whether a signal of a desired amplitude is present on the basis of a signal output from the transimpedance amplifier 12. When the signal is present, the optical receiver 1 stops the operation of adjusting the conversion gain of the transimpedance amplifier 12 by the gain control circuit 13 so that the transimpedance amplifier 12 continues to use the conversion gain at that point in time. Consequently, even when operation performed under conditions where the output voltage of the operational amplifier 131 of the gain control circuit 13 does not rise even after the control of the conversion gain of the transimpedance amplifier 12 has converged, the operation of the gain control circuit 13 can be stopped. Thus, the conversion gain can be prevented from being unnecessarily changed after the control of the conversion gain of the transimpedance amplifier 12 has converged, and as a result, the bit error rate can be prevented from increasing.
The first embodiment above has described the optical receiver 1 that stops the operation of the gain control circuit 13 when detecting the rising edge of the output signal from the signal detection circuit 16 The following describes an optical receiver that delays the output signal from the signal detection circuit 16 by a proper time to obtain similar effects to the first embodiment even when a signal is detected before the completion of the AGC operation.
Consider a case where, as illustrated in.
To avoid this, the delay circuit 17 is added which delays the rising timing and the falling timing of the signal detection signal output from the signal detection circuit 16, so that, as illustrated in
The delay circuit 17 can be composed of, for example, an RC filter including a resistor and a capacitor and a buffer circuit connected to an output terminal of the RC filter. Thus, the rising timing and the falling timing of the signal detection signal can be delayed by a period of time during which the rising waveform and the falling waveform of an input signal are rounded by the RC filter. When a desired amount of delay cannot be achieved by a single-stage RC filter and a buffer circuit, such circuits may be connected in multiple stages in cascade to increase the amount of delay to achieve the desired amount of delay. It is also possible to make the amount of delay variable instead of being fixed by preparing a plurality of delay circuits having different amounts of delay in parallel and selecting one of them by a switch or the like.
As described above, the optical receiver 1a according to the present embodiment includes the delay circuit 17 that delays the rising edge and the falling edge of the signal output from the signal detection circuit 16 and inputs the delayed signal to the determination circuit 14. Consequently, the AGC operation by the gain control circuit 13 can be stopped after the control of the conversion gain of the transimpedance amplifier 12 has converged, and the conversion gain of the transimpedance amplifier 12 can be prevented from being fixed at an improper value.
The first embodiment and the second embodiment have described the configuration in which the operation of the gain control circuit 13 is stopped using only the signal detection signal as a trigger. An optical receiver that can obtain similar effects to the first embodiment will be described which uses either the output voltage of the operational amplifier 131 of the gain control circuit 13 or the output voltage of the signal detection circuit 16 as a trigger.
The convergence determination circuit 18 includes a comparator 181 that compares the output voltage of the operational amplifier 131 of the gain control circuit 13 with a convergence determination threshold that is a preset threshold voltage, and outputs a comparison result at a high or low voltage, a logic circuit 182 that generates a convergence determination signal on the basis of an output signal from the comparator 181 and the external reset signal, and a determination circuit 183 that stops the operation of the operational amplifier 131 when detecting the rising edge of the signal output from the signal detection circuit 16 or the rising edge of the signal output from the logic circuit 182.
The logic circuit 182 starts to output a low voltage on the rising edge of the external reset signal and starts to output a high voltage on the rising edge of the output signal from the comparator 181. That is, the logic circuit 182 outputs the signal that becomes the high voltage when the control of the conversion gain by the gain control circuit 13 has converged, and the comparator 181 detects that the output voltage of the operational amplifier 131 has exceeded the threshold voltage with the conversion, and becomes the low voltage when the rising edge of the external reset signal is detected.
The operation of the optical receiver 1b according to the third embodiment will be described with reference to timing charts in
First, the first example operation illustrated in
As illustrated in.
On the other hand, as illustrated in
Next, the second example operation illustrated in
In
As descried above, the optical receiver 1b according to the present embodiment includes the convergence determination circuit 18 that stops the operation of the operational amplifier 131 of the gain control circuit 13 when the output voltage of the operational amplifier 131 of the gain control circuit 13 rises after the conversion gain of the transimpedance amplifier 12 has converged, or the rising edge of the signal detection signal output from the signal detection circuit 16 is detected. Thus, even when the output voltage of the operational amplifier 131 of the gain control circuit 13 does not increase after the conversion gain of the transimpedance amplifier 12 has converged, the AGC operation by the gain control circuit 13 can be stopped.
The third embodiment has described the optical receiver 1b that stops the operation of the operational amplifier 131 of the gain control circuit 13 using the rising edge of the signal detection signal output from the signal detection circuit 16 and the rising edge of the convergence determination signal as a trigger. The present embodiment describes an optical receiver that delays the rising edge of the signal detection signal and stops the operation of the operational amplifier 131 when either the rising edge of the delayed signal detection signal or the rising edge of the convergence determination signal detected.
The operation of the optical receiver 1c is the similar to that of the optical receiver 1b according to the third embodiment except that the delay circuit 17 delays the timing of input of the signal detection signal to the convergence deter enation circuit 18.
In the optical receiver 1c according to the present embodiment, as in the optical receiver 1a according to the second embodiment, a timing at which the voltage at point F rises can be set to the timing after the completion of the operation of adjusting the conversion gain of the transimpedance amplifier 12 by the gain control circuit 13.
The optical receiver according to the disclosure has the effect of being able to prevent an unnecessary change of the conversion gain of the transimpedance amplifier after the adjustment of the conversion gain of the transimpedance amplifier has been completed.
The configurations described in the above embodiments illustrate an example, and can be combined with another known art, and can be partly omitted or changed without departing from the scope.
This application is a continuation application of International Application PCT/JP2019/031700, filed on Aug. 9, 2019, and designating the U.S., the entire contents of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2019/031700 | Aug 2019 | US |
| Child | 17551527 | US |
