The disclosure relates to an optical sensing device, and particularly relates to an optical sensing device providing two power rails.
The optical sensing device includes a plurality of pixel units arranged in an array and a power rail, wherein the power rail enables a bias current to flow through the pixel units by providing an operating voltage. In short, current is loaded from the power rail via the trace. However, in practice, the current value of the load current needs a period of time (related to the time constant value (τ=RC)) to stabilize before becoming a preset current value of the bias current. Moreover, due to the instability of the load current, the IR drop of the trace is also unstable. The above factor will cause the actual operating voltage received by the pixel units to fluctuate according to the distribution positions of the pixel units and the operating voltage received by each pixel unit at different times is also different. This leads to the sensing accuracy of the optical sensing device to be reduced. Therefore, a demand for solutions to improving the sensing accuracy of the optical sensing device.
The disclosure provides an optical sensing device and a method thereof, which can improve the sensing accuracy of the optical sensing device.
An optical sensing device of the disclosure includes a first power rail, a second power rail, and a plurality of optical sensing elements arranged in an array. Each optical sensing element includes a photo diode, a reset switch, and a buffer. The reset switch has a control terminal configured to receive a reset signal. A first terminal of the reset switch is coupled to the first power rail and a second terminal of the reset switch is coupled to the photo diode. A first terminal of the buffer is coupled to the second power rail, a second terminal of the buffer is coupled to the second terminal of the reset switch and the photo diode, and a third terminal of the buffer is configured to provide a sensing signal. The second power rail is independent from the first power rail.
An optical sensing method of the disclosure is applicable to an optical sensing device, wherein the optical sensing device includes a plurality of optical sensing elements arranged in an optical sensing element array. Each optical sensing element includes a photo diode, a reset switch coupled to the photo diode, and a buffer coupled to the reset switch and the photo diode. The optical sensing method of the disclosure includes the following steps. The first power rail is provided to a first terminal of the reset switch. The second power rail independent from the first power rail is provided to a first terminal of the buffer. A reset signal is provided to control the reset switch according to the reset signal. A sensing signal is provided by the buffer.
An optical sensing device of the disclosure includes a first power rail, configured to provide a first voltage; a second power rail, configured to provide a reset voltage; and a plurality of optical sensing elements, arranged in an optical sensing element array, coupled to the first power rail and the second power rail to receive the first voltage and the reset voltage, and configured to be reset respectively according to the reset voltage in each of two sensing operations during a pixel read-out cycle. The reset voltage can be independent or separate from the first voltage provided by the first power rail such that a voltage level of the reset voltage is substantially the same during the two sensing operations of the pixel read-out cycle.
Based on the above, since the first power rail and the second power rail are independent from each other, the reset operation of the optical sensing element is not affected by the sensing operation, so that the operating voltage source of the reset operation is relatively stable. In this way, the signal difference component of the optical sensing element obtained through a correlated double sampling (CDS) mechanism is relatively pure, thereby improving the sensing accuracy of optical sensing.
To make the aforementioned and other features of the disclosure more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
The power rail 120 provides an operating voltage VDDSF for each optical sensing element to form a bias current. The power rail 130 provides an operating voltage VDDReset for resetting the photo diode of each optical sensing element. The power rail 120 and the power rail 130 are independent from each other. The power rail 120 may be coupled to one power supply and the power rail 130 may be coupled to another power supply different from the aforementioned power supply. This means that the providing the operating voltage VDDSF is independently performed from the providing the operating voltage VDDReset. In other words, the current or voltage level provided by the operating voltage VDDSF is not affected by the operating voltage VDDReset.
The bias current generating circuit 140 is coupled to each optical sensing element via a plurality of sensing lines including the sensing line SL1 and is configured to generate the bias current of each optical sensing element (such as the bias current ISF0 of the optical sensing element P00) with a bias voltage VB.
Each of the optical sensing element may include a reset switch, a photo diode, a buffer, and a selection switch. In the embodiment, the optical sensing element may be a thin-film transistor (TFT) unit. The buffer may be implemented as a source follower.
In addition,
As will also explained more, since the voltage sources of the reset operation and the sensing operation are separate (i.e., the power rail 130 is independent from the power rail 120), the reset voltage sensed at different time points may be regarded as substantially the same. Consequently, a signal difference component ΔVsig representing a sensing result is relatively accurate.
More specifically, since the power rail 130 to which the reset switch MRST is coupled is arranged to be independent from the power rail 120, the operating voltages V00, V10, and V20 etc. applied to each reset switch MRST may not be influenced by the IR drop caused by the load current flowing through the buffer MSF. That is to say the load current flowing through the power rail 120 is independent from the load current flowing through the power rail 130. This means that a reset operation is less affected by the sensing operation. Moreover, the influence of a time constant on the reset operation is also mitigated. The above factors cause the voltage of the node FN to approach quickly the operating voltage V00. Consequently, the reset voltage (charged to the operating voltage V00) sensed at different time points may be regarded as the same, enhancing accuracy of the signal difference component ΔVsig.
In the embodiment, the voltage level of the operating voltage VDDSF provided by the power rail 120 is different from the voltage level of the operating voltage VDDReset provided by the power rail 130. However, in other embodiments, the voltage level of the operating voltage VDDSF may also be the same as the voltage level of the operating voltage VDDReset. In an embodiment, the voltage values of the operating voltages VDDSF and VDDReset may both be 5V. In another embodiment, the voltage values of the operating voltages VDDSF and VDDReset may both be 3.3V. The focus of the above two embodiments is that for the reset operation and the sensing operation are from different operating voltage sources. Moreover, the power rail 120 and the power rail 130 do not necessarily need to be located at the same side of the optical sensing array 110 as shown in
In the following, details are provided for the reason why the signal difference component ΔVsig sensed is relatively accurate by utilizing two independent power rails 120 and 130. The optical sensing element is reset before sensing. At this time, the voltage value (equivalent to the voltage value of the node FN[0,0] in
For the optical sensing element P00, the reset switch MRST of the optical sensing element P00 is turned on by changing the voltage level of a reset line Reset[0] to pull up the voltage of the node FN[0,0] to the current operating voltage (recorded as VV00(T1)). Next, the reset switch MRST is turned off and the integration time begins. At this time, the node FN[0,0] is floating, the voltage of the node FN[0,0] gradually drops from a high point (operating voltage VV00(T1)), and the degree of drop will be affected by the sensing result of the photo diode PD. The voltage of the node FN[0,0] is reflected on the source voltage of the buffer MSF, thereby affecting the magnitude of the bias current ISF0. At a time point when the integration time is almost ending, the optical sensing device 100 turns on the selection switch MSEL by changing the voltage level of the selection line SEL[0], so that the bias current (reflecting the voltage value of the photo diode PD) flows into the sensing line SL1 to obtain a first sensing result. The first sensing result includes the signal difference component of the optical sensing element due to light sensitivity and is recorded as ΔVsig.
Then, the optical sensing device 100 turns on the reset switch MRST to reset the voltage of the photo diode PD again, so as to pull up the voltage of the node FN[0,0] to the current operating voltage (recorded as VV00(T2)). The optical sensing device 100 also senses the bias current (reflecting the voltage value of the reset photo diode PD) to obtain a second sensing result. Finally, the pure signal difference component ΔVsig is obtained by subtracting the two sensing results (VV00(T2)−(VV00(T1)−ΔVsig)).
Since the voltage sources of the reset operation and the sensing operation are separate (i.e., the power rail 130 is independent from the power rail 120), the reset voltage sensed at different time points may be regarded as substantially the same, so that the signal difference component ΔVsig sensed is relatively accurate.
The difference between using the disclosure and not using the disclosure (prior art) will be explained below from the signal timing diagrams.
As illustrated in paragraph [0020] of the present invention, the optical sensing element undergoes a reset before a sensing operation, then performs the first sensing to obtain the voltage value recorded as VVDD(T1)−ΔVsig, wherein ΔVsig represents the voltage value change of the optical sensing element. A second sensing is performed after the optical sensing element is reset again, and the voltage value of the current operating voltage recorded as VVDD(T2) is obtained. Finally, a signal Vcds(=VVDD(T2)−(VVDD(T1)−ΔVsig)) may be read through a correlated double sampling (CDS) mechanism. However, the disclosure is not limited to CDS mechanism.
Ideally, the values of the operating voltages VVDD(T1) and VVDD(T2) are the same or almost the same, so the pure ΔVsig may be obtained through the CDS mechanism and the factor of the operating voltage being different due to the distribution position of the pixel unit may be neglected. However, in practice, the operating voltage fluctuates, so the values of the operating voltages VVDD(T1) and VVDD(T2) measured at different times have errors, which makes it impossible to obtain the pure ΔVsig through the CDS mechanism. In other words, the sensing accuracy of the optical sensing device is reduced.
In details, before a time point t0, a selection switch of a corresponding optical sensing element is turned on through a selection line SEL[0]. Between the time point t0 and a time point t1, a reset switch of the optical sensing element is turned on through a reset switch Reset[0] to pull up the voltage of a node FN[0,0] to a high point (operating voltage VVDD(T1)). Then, the reset switch is turned off and an integration time T1 begins. At a time point t2 when an integration time T1 is almost ending, a selection switch is turned on again for a first sensing.
At this time, a voltage value Vsense of the node FN[0,0] is reflected on the bias current to be sensed. It can be seen from
At this time, the voltage value Vsense of the node FN[0,0] is reflected on the bias current ISF0 to be sensed. It can be seen from
In more detail, although the VDDReset in
In summary, the optical sensing device of the embodiments have two power rails to respectively provide operating voltages of different sources for the reset operation and the sensing operation of the optical sensing element. Since the reset operation is not affected by the sensing operation, the reset voltage (reset to the current operating voltage) of the same optical sensing element at different times may be regarded as the same. Therefore, the signal difference component of the optical sensing element obtained through the CDS mechanism can be relatively pure. Through the optical sensing device and the optical sensing method of the disclosure, the sensing accuracy of optical sensing can be improved.
Lastly, it should be mentioned that the above embodiments are configured to explain the technical solution of the disclosure and are not intended to limit the same. Please refer to the embodiments for detailed explanation of the disclosure. It will be apparent to persons skilled in the art that modifications can be made to the technical solution disclosed by the embodiments or equivalent replacements of some or all technical features can be made. However, the modifications or replacements do not make the essence of the corresponding technical solution to depart from the scope according to the embodiments of the disclosure.