Patent Application
20240154699
Embodiments of this application relate to the field of communication technologies, and in particular, to an optical/electrical module, a communication method, and a related device.
A high performance computing (HPC) cluster usually includes a plurality of levels of switches, a plurality of servers, and the like. A high-speed cable or an optical fiber may be used for data transmission between the switch and the server or between the switches, to reduce a transmission latency.
As an amount of data to be transmitted increases, a data rate of a single port is increasingly high, and a mainstream server interface has evolved from 4×10 Gbps to 4×25 Gbps. A higher port rate indicates higher bandwidth and a larger loss coefficient for transmission of an electrical signal in a medium such as a printed circuit board (PCB) or a cable. Therefore, to resolve problems of signal attenuation and signal distortion that are caused in a transmission and optical/electrical conversion process of the electrical signal or an optical signal, a manner of adding one clock and data recovery (CDR) unit inside the switch, the server, or the like is mostly used in the market, to regenerate, re-time and re-amplify the received electrical signal.
However, although the additional CDR unit can resolve, to some extent, a problem caused by the large loss coefficient in the transmission process of the electrical signal, in a process of regenerating, re-timing, and re-amplifying the received electrical signal by using the CDR, a received high-speed electrical signal needs to be converted into a low-speed electrical signal through serial-to-parallel conversion and digital logic processing needs to be performed, and then the low-speed electrical signal is converted into a high-speed electrical signal through parallel-to-serial conversion. The digital logic processing, serial-to-parallel conversion, and the like cause a large latency. This in turn increases computing waiting time and reduces an overall computing capability of the HPC cluster. Therefore, how to reduce a transmission latency while ensuring signal transmission quality is an urgent problem to be resolved.
Embodiments of this application provide an optical/electrical module, a communication method, and a related device, to reduce a transmission latency while ensuring signal transmission quality.
According to a first aspect, an embodiment of this application provides an optical/electrical module, including an analog equalizer and an optical/electrical conversion unit, where the analog equalizer is connected to the optical/electrical conversion unit. The analog equalizer is configured to: perform first analog signal equalization processing on a first electrical signal to obtain a second electrical signal, and send the second electrical signal to the optical/electrical conversion unit, or is configured to: receive a third electrical signal from the optical/electrical conversion unit, and perform second analog signal equalization processing on the third electrical signal to obtain a fourth electrical signal. The optical/electrical conversion unit is configured to: receive the second electrical signal from the analog equalizer and convert the second electrical signal into a first optical signal, or is configured to: convert a second optical signal into the third electrical signal and send the third electrical signal to the analog equalizer.
In this embodiment of this application, the analog equalizer may be used in the optical/electrical module to replace an original CDR. In this way, analog signal equalization processing may be directly performed, in an analog domain by using the analog equalizer, on an electrical signal that is input (for example, the first electrical signal, where the first electrical signal may be an electrical signal that is input to the analog equalizer when a local device sends a signal to another device, or for another example, the third electrical signal, where the third electrical signal may be an electrical signal that is received by the optical/electrical conversion unit of the local device and output to the analog equalizer when the another device sends a signal to the local device), to compensate for a loss generated in a transmission process of the electrical signal, and efficiently and quickly output an electrical signal (for example, the second electrical signal or the fourth electrical signal) with better quality and less inter-symbol interference. In this way, complex and time-consuming processing processes such as digital logic processing and serial-to-parallel conversion in the CDR are avoided while ensuring signal transmission quality, so that a signal transmission latency between communication devices is greatly reduced, thereby reducing computing waiting time of each communication device, and improving an overall computing capability.
In a possible implementation, the optical/electrical conversion unit includes a first optical/electrical converter, configured to: receive the second electrical signal from the analog equalizer and convert the second electrical signal into the first optical signal. The analog equalizer includes a transmit equalizer, configured to: perform the first analog signal equalization processing on the first electrical signal to obtain the second electrical signal, and send the second electrical signal to the first optical/electrical converter. In this embodiment of this application, when the local device sends a signal to the another device, a transmission loss exists in a transmission process before a to-be-sent electrical signal (for example, the first electrical signal) in the local device is input to the analog equalizer. Therefore, the electrical signal received by the analog equalizer usually has signal distortion and attenuation to some extent. Consequently, inter-symbol interference of the electrical signal is greater than inter-symbol interference of an electrical signal that is originally output. Based on this, in a sending direction, the analog equalizer in this application may perform equalization processing on the received electrical signal in the analog domain, to compensate for the loss in the previous transmission process of the electrical signal, and efficiently and quickly output an electrical signal (for example, the second electrical signal) with better quality and less inter-symbol interference to the optical/electrical conversion unit in the optical/electrical module. Then, the optical/electrical conversion unit may convert the received electrical signal into a corresponding optical signal, so that the signal is subsequently quickly transmitted to the another device through an optical fiber, thereby ensuring that the another device can quickly receive a signal with better quality. In some possible embodiments, as described above, because the electrical signal output by the analog equalizer needs to subsequently undergo electrical-to-optical conversion and then be transmitted to the another device, the analog equalizer may further perform pre-equalization processing on the electrical signal based on a transmission loss that may be generated in a subsequent transmission process, to compensate for the loss in the subsequent transmission process, and further ensure quality and the like of a signal received by the another device. This is not specifically limited in this embodiment of this application.
In a possible implementation, the transmit equalizer includes at least one of a first continuous time linear equalizer CTLE, a first low frequency equalizer LFEQ, and a first level mismatch compensation circuit. In this way, in the sending direction, the analog equalizer may compensate a high-frequency part and/or a low-frequency part of the received signal (for example, the first electrical signal) to be sent by the local device, to reduce inter-symbol interference of the high-frequency part and/or the low-frequency part of the signal, so that compared with the received electrical signal, a high-quality electrical signal with less inter-symbol interference can be obtained and output.
In a possible implementation, the transmit equalizer includes the first CTLE, the first LFEQ, and the first level mismatch compensation circuit that are connected in series. In this embodiment of this application, all frequency bands of the signal may be compensated by using the analog equalizer, to obtain a higher-quality electrical signal, thereby more reliably ensuring the quality of the signal received by the another device.
In a possible implementation, the optical/electrical conversion unit includes a second optical/electrical converter, configured to: convert the second optical signal into the third electrical signal and send the third electrical signal to the analog equalizer. The analog equalizer includes a receive equalizer, configured to: receive the third electrical signal from the second optical/electrical converter, and perform the second analog signal equalization processing on the third electrical signal to obtain the fourth electrical signal. In this embodiment of this application, when the local device receives a signal sent by the another device, the optical/electrical conversion unit in the local device may receive an optical signal output by the another device, convert the optical signal into a corresponding electrical signal (for example, the third electrical signal), and output the corresponding electrical signal to the analog equalizer. Correspondingly, a loss exists in a transmission process before the electrical signal is input to the analog equalizer. Based on this, in a receiving direction, the analog equalizer in this application may perform equalization processing on the received electrical signal in the analog domain, to compensate for the loss in the previous transmission process of the electrical signal, and efficiently and quickly output an electrical signal (for example, the fourth electrical signal) with better quality and less inter-symbol interference, thereby ensuring quality of an electrical signal that is finally received by the local device and that is used to perform corresponding computing, analysis, or the like.
In a possible implementation, the receive equalizer includes at least one of a second CTLE, a second LFEQ, and a second level mismatch compensation circuit. In this way, in the receiving direction, the analog equalizer may compensate a high-frequency part and/or a low-frequency part of the received signal (for example, the third electrical signal) to be sent by the another device, to reduce inter-symbol interference of the high-frequency part and/or the low-frequency part of the signal, so that compared with the received electrical signal, a high-quality electrical signal with less inter-symbol interference can be obtained and output.
In a possible implementation, the receive equalizer includes the second CTLE, the second LFEQ, and the second level mismatch compensation circuit that are connected in series. In this embodiment of this application, all frequency bands of the signal may be compensated by using the analog equalizer, to obtain a higher-quality electrical signal, thereby more reliably ensuring the quality of the signal received by the local device.
According to a second aspect, an embodiment of this application provides a communication device, including a digital signal interface unit and the optical/electrical module according to any implementation of the first aspect. The digital signal interface unit is configured to: receive a first digital electrical signal from a processing device, convert the first digital electrical signal into the first electrical signal, and send the first electrical signal to the analog equalizer, or is configured to: receive the fourth electrical signal from the analog equalizer, convert the fourth electrical signal into a second digital electrical signal, and send the second digital electrical signal to the processing device.
In this embodiment of this application, when the local device sends a signal to another device, the digital signal interface unit in the local device may convert a digital electrical signal output by the processing device (for example, a central processing unit (CPU) or a graphics processing unit (GPU)) into an analog electrical signal (for example, the first electrical signal), and input the analog electrical signal to the analog equalizer, so that subsequently, equalization processing may be directly performed on the analog electrical signal in an analog domain by using the analog equalizer, to efficiently and quickly obtain and output a high-quality analog electrical signal (for example, the second electrical signal) with less inter-symbol interference, to ensure quality of the signal received by the another device, and greatly reduce a signal transmission latency. Alternatively, when the local device receives a signal sent by the another device, based on a received analog electrical signal (for example, the third electrical signal) sent by the optical/electrical conversion unit, the analog equalizer directly performs equalization processing on the analog electrical signal in the analog domain, to efficiently and quickly obtain and output a high-quality analog electrical signal (for example, the fourth electrical signal) with less inter-symbol interference to the digital signal interface unit, and then the digital signal interface unit may convert the analog electrical signal into a corresponding high-quality digital electrical signal and output the high-quality digital electrical signal to the processing device. Therefore, it is ensured that the processing device may subsequently perform reliable and accurate computing, analysis, or the like based on the received digital electrical signal, and time for the local device to wait for receiving the signal is greatly reduced.
In a possible implementation, the device further includes a high-speed passive component, configured to connect the digital signal interface unit to the analog equalizer. In this embodiment of this application, the digital signal interface unit and the equalizer in this application may be further connected by using the high-speed passive component, to provide a low-loss high-speed transmission channel for the signal, thereby reducing a transmission latency while further reducing inter-symbol interference and ensuring signal quality.
In a possible implementation, the high-speed passive component includes a first high-speed connector, a second high-speed connector, and a high-speed cable, the first high-speed connector and the second high-speed connector are connected through the high-speed cable, the first high-speed connector is connected to the digital signal interface unit, and the second high-speed connector is connected to the analog equalizer. In this embodiment of this application, if there is a long distance between the digital signal interface unit in the device and the analog equalizer (in other words, the optical/electrical module), and a rate of a transmitted signal is high, a severe transmission loss and a large transmission latency are generated when the signal is transmitted in this period. Based on this, the high-speed passive component in this embodiment of this application may include two high-speed connectors and a segment of high-speed cable configured to connect the two high-speed connectors. The two high-speed connectors are respectively connected to the digital signal interface unit and the analog equalizer, and then the low-loss high-speed transmission channel is provided through the high-speed cable in the middle, to ensure that the signal transmission loss and the transmission latency are reduced when the signal is transmitted over a long distance in the device. In this way, it can be ensured that subsequently, the analog equalizer can quickly and effectively compensate for the transmission loss of the electrical signal.
In a possible implementation, the high-speed passive component includes a first high-speed connector, and the first high-speed connector is connected between the digital signal interface unit and the analog equalizer. The device further includes a first hollow-core optical fiber and a hollow-core optical fiber connector. The first hollow-core optical fiber is connected to the optical/electrical conversion unit, and is configured to: send the first optical signal or receive the second optical signal. The hollow-core optical fiber connector is configured to: send the first optical signal to a second hollow-core optical fiber or receive the second optical signal from the second hollow-core optical fiber. In this embodiment of this application, the local device may be connected to the another device through a hollow-core optical fiber (for example, the second hollow-core optical fiber), to reduce the signal transmission latency between the devices. In addition, the high-speed passive component in the local device may include only one high-speed connector configured to be connected between the digital signal interface unit and the analog equalizer. In this way, the analog equalizer (in other words, the optical/electrical module) is located at a position close to the digital signal interface unit. Correspondingly, the optical/electrical conversion unit in the optical/electrical module is located at a position far away from the hollow-core optical fiber between the devices. To be specific, an optical signal output by the optical/electrical conversion unit can be transmitted to the hollow-core optical fiber between the devices only after a long distance. Alternatively, an optical signal output by the hollow-core optical fiber between the devices can be transmitted to the optical/electrical conversion unit only after a long distance. Based on this, the local device may further include a segment of hollow-core optical fiber (for example, the first hollow-core optical fiber) connected to the optical/electrical conversion unit, and a connector configured to connect the hollow-core optical fiber in the device and the hollow-core optical fiber between the devices. High-speed optical signal transmission may be performed through the hollow-core optical fibers inside and outside the device by using the connector.
According to a third aspect, an embodiment of this application provides an active optical cable, including at least two optical/electrical modules according to any implementation of the first aspect and a hollow-core optical fiber, where the at least two optical/electrical modules are connected through the hollow-core optical fiber.
According to a fourth aspect, an embodiment of this application provides a communication system, including a plurality of communication devices, where the plurality of communication devices are connected through the active optical cable according to the third aspect. In a possible implementation, the plurality of communication devices include at least one device according to any implementation of the second aspect.
According to a fifth aspect, an embodiment of this application provides a communication method in which an optical/electrical module is used, including: performing first analog signal equalization processing on a first electrical signal by using an analog equalizer in the optical/electrical module to obtain a second electrical signal, and sending the second electrical signal to an optical/electrical conversion unit, or receiving a third electrical signal from the optical/electrical conversion unit by using the analog equalizer, and performing second analog signal equalization processing on the third electrical signal to obtain a fourth electrical signal; and receiving the second electrical signal from the analog equalizer by using the optical/electrical conversion unit in the optical/electrical module, and converting the second electrical signal into a first optical signal, or converting a second optical signal into the third electrical signal by using the optical/electrical conversion unit, and sending the third electrical signal to the analog equalizer.
According to a sixth aspect, an embodiment of this application provides a computer-readable storage medium. The computer-readable storage medium stores a computer program. When the computer program is executed by a processor, a procedure of the communication method in which an optical/electrical module is used according to the fifth aspect is implemented. There may be one or more processors.
According to a seventh aspect, an embodiment of this application provides a computer program. The computer program includes instructions. When the computer program is executed by a computer, the computer is enabled to perform a procedure of the communication method in which an optical/electrical module is used according to the fifth aspect.
According to an eighth aspect, an embodiment of this application provides a chip. The chip includes a processor and a communication interface. The processor is configured to invoke instructions from the communication interface and run the instructions. When the processor executes the instructions, the chip is enabled to perform a procedure of the communication method in which an optical/electrical module is used according to the fifth aspect.
According to a ninth aspect, an embodiment of this application provides a chip system. The chip system may include the optical/electrical module according to any implementation of the first aspect, and is configured to implement a function in a procedure of the communication method in which an optical/electrical module is used according to the fifth aspect. In a possible design, the chip system further includes a memory. The memory is configured to store program instructions and data that are necessary for the communication method. The chip system may include a chip, or may include a chip and another discrete device.
To describe technical solutions in embodiments of this application more clearly, the following describes the accompanying drawings for describing embodiments of this application or the background.
The following describes embodiments of this application with reference to the accompanying drawings in embodiments of this application. In the specification, claims, and accompanying drawings of this application, the terms “first”, “second”, “third”, “fourth”, “1st”, “2nd”, “3rd”, “4th”, and the like are intended to distinguish between different objects but do not indicate a particular order. In addition, the terms “including”, “having”, and any other variants thereof are intended to cover non-exclusive inclusion. For example, a process, a method, a system, a product, or a device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes an unlisted step or unit, or optionally further includes another inherent step or unit of the process, the method, the product, or the device.
Mentioning an “embodiment” in the specification means that a particular feature, structure, or characteristic described with reference to the embodiment may be included in at least one embodiment of this application. The phrase shown in various locations in the specification may neither necessarily mean a same embodiment, nor mean an independent or optional embodiment exclusive from another embodiment. It is explicitly and implicitly understood by persons skilled in the art that embodiments described in the specification may be combined with another embodiment.
Some terms in this application are first described, to help persons skilled in the art have a better understanding.
(1) High performance computing (HPC) is a computing system and environment that usually use a plurality of processors (as a part of a single server) or a plurality of servers (as a single computing resource operation) in a cluster and a switching network thereof.
To reduce a latency in transmitting data (in other words, a signal) between different servers or switches, reduce computing waiting time, and improve an overall computing capability, an HPC system usually uses a high performance network interconnection, for example, uses a low-latency “infiniband” (IB) switch. “Infiniband” is a computer network communication standard for high performance computing. “Infiniband” has a very high throughput and a very low latency, and is for a data interconnection between computers. Infiniband is also used as a direct or switched interconnection between the server and a storage system and an interconnection between storage systems. A high-speed cable or an optical fiber may be used for data transmission between the infiniband switch and the server or between infiniband switches, to further reduce a transmission latency.
As shown in
(2) An insertion loss is generally a loss of energy or a gain when some devices or branch circuits (a filter, an impedance matcher, an adapter, or the like) are added to a circuit. An insertion loss during transmission of an optical signal between two nodes may be generally divided into three parts. The node A and the node B in
(3) A principle of a hollow-core optical fiber is different from a total reflection principle of a conventional optical fiber waveguide to guide light. A fiber core of the hollow-core optical fiber is air. This brings benefits such as a low latency, ultra-low nonlinearity, and low dispersion. However, the hollow-core optical fiber has a problem of a very large insertion loss at the beginning. To overcome the problem of the large insertion loss of the hollow-core optical fiber, a variety of hollow-core optical fibers based on an anti-resonance principle are proposed in the market. To be specific, based on an anti-resonance mechanism of a resonant cavity in a cladding, light is bound in an air hole that is used as a core.
(4) A clock and data recovery (CDR) is mainly used to keep a signal of a receive end consistent with a signal of a transmit end. When an electrical signal or an optical signal is transmitted to a specific distance, long-distance transmission is usually performed, and a waveform of the electrical signal or the optical signal has distortion to some extent. Therefore, a signal received by the receive end is a pulse signal of different lengths, which cannot meet an actual requirement. In the foregoing case, signal regeneration, re-amplification, re-timing, and the like may be performed by using the CDR, to obtain a signal that meets the requirement. Generally, most of optical/electrical modules that use the CDR are optical/electrical modules with high-rate and long-distance transmission.
As described above, with rapid development of an information society, an amount of data to be transmitted increases, a data rate of a single port is increasingly high, and a mainstream server interface has evolved from 4×10 Gbps to 4×25 Gbps. A higher port rate indicates larger bandwidth, and a larger loss coefficient for transmitting an electrical signal in a medium such as a printed circuit board (PCB) or a cable. Therefore, a series of processing usually needs to be performed on a signal received by the node or a signal to be sent by the node, so that an inevitable loss of the signal in a transmission process is compensated for, to ensure signal quality and ensure that the node can perform reliable and accurate computing and the like based on the received signal.
In conclusion, to facilitate understanding of embodiments of this application, a technical problem specifically to be resolved in this application is further analyzed and proposed. In a conventional technology, to resolve a problem of a severe signal loss generated when a transmission rate is increasingly high, a plurality of technical solutions are included. The following exemplifies the following common solutions.
Optionally, device types of the node A and the node B shown in
As shown in
With reference to a node structure shown in
In this way, to resolve problems of signal attenuation and signal distortion caused during transmission and optical/electrical conversion of the electrical signal or the optical signal, as shown in
Further, as shown in
(1) Latency (that is, a latency needed for signal regeneration, re-timing, and re-amplification after the CDR of the node A receives a signal sent by the digital signal interface unit) in a sending direction of the CDR of the node A and latency (that is, a latency needed for signal regeneration, re-timing, and re-amplification after the CDR of the node B receives a signal sent by the optical-to-electrical conversion unit) in a receiving direction of the CDR of the node B. Optionally, based on different rates, different coding formats, and different design schemes, generally, a sum of the foregoing two latencies ranges from tens of nanoseconds (ns) to hundreds of nanoseconds, and a typical value is 100 ns.
(2) Optical fiber transmission latency of an output from the optical/electrical module of the node A to the optical/electrical module of the node B. For example, if a currently used optical fiber is a solid-core single mode fiber (SMF) or multi-mode fiber (MMF), a transmission latency coefficient of the optical fiber is about 4.8 ns/m. For example, if the optical fiber is 50 m long, a total transmission latency of the optical fiber is 240 ns.
(3) Routing latencies of the electrical signals of the node A and the node B on respective PCBs, for example, a routing latency of an electrical signal output from the digital signal interface unit of the node A to the CDR of the node A or a routing latency of an electrical signal output from the CDR of the node A to the electrical-to-optical conversion unit of the node A. Details are not described herein again. Due to different dielectric constants of PCB materials, a PCB transmission latency coefficient ranges from 5 ns/m to 10 ns/m. However, because a PCB routing length is short, the routing length at each node is usually less than 0.5 m. To be specific, a sum of the routing latencies of the electrical signals of the node A and the node B is usually less than 10 ns. It is clear that compared with the CDR latency and the optical fiber transmission latency, the routing latency of the electrical signal on the PCB is a very small value.
Further, when a port rate continues to increase, for example, increase to 4×50 Gbps, a 4 levels pulse amplitude modulation (PAM4) coding format begins to be used in the industry to replace a non-return-to-zero (NRZ) coding format, to reduce a baud rate of a signal, thereby avoiding an increase that is in a loss coefficient of transmission on media such as the PCB and a cable and that is caused by an increase in signal bandwidth. However, because a multi-level signal is more sensitive to signal distortion and can tolerate less signal attenuation, when the digital signal interface unit is far away from the optical/electrical module, to avoid signal distortion and excessive signal attenuation, another CDR unit needs to be added to a main board PCB.
(1) Latency in a sending direction of a CDR in an optical/electrical module of the node C and latency in a receiving direction of a CDR in an optical/electrical module of the node D. Optionally, based on different rates, different coding formats, and different design schemes, generally, a sum of the foregoing two latencies ranges from tens of nanoseconds to hundreds of nanoseconds, and a typical value is 100 ns.
(2) Latency in a sending direction of the relay CDR of the node C and latency in a receiving direction of the relay CDR of the node D. Optionally, based on different rates, different coding formats, and different design schemes, generally, a sum of the foregoing two latencies ranges from tens of nanoseconds to hundreds of nanoseconds, and a typical value is 100 ns.
(3) Optical fiber transmission latency of an output from the optical/electrical module of the node C to the optical/electrical module of the node D. For example, if a currently used optical fiber is still a solid-core SMF or MMF, a transmission latency coefficient of the optical fiber is 4.8 ns/m. For example, if the optical fiber is 50 m, a total transmission latency of the optical fiber is 240 ns.
(4) Routing latencies of electrical signals of the node C and the node D on respective PCBs. Similarly, a sum of the routing latencies of the electrical signals of the node C and the node D is generally less than 10 ns. It is clear that compared with the CDR latency in the optical/electrical module, the relay CDR latency, and the optical fiber transmission latency, the routing latency of the electrical signal on the PCB is a very small value.
It should be noted that
In conclusion, although the additional CDR can resolve problems caused by losses of the electrical signal and the optical signal due to transmission and optical/electrical conversion to some extent, in a process of regenerating, re-timing, and re-amplifying the received electrical signal by using the CDR, a received high-speed electrical signal needs to be converted into a low-speed electrical signal through serial-to-parallel conversion and digital logic processing needs to be performed, and then the low-speed electrical signal is converted into a high-speed electrical signal through parallel-to-serial conversion. Operations such as the digital logic processing and the serial-to-parallel conversion are complex and time-consuming, and bring a large latency. The link between the node C and the node D in the foregoing figure is used as an example. The optical fiber transmission latency is 240 ns, the CDR latency in the optical/electrical module is 100 ns, the relay CDR latency on a main board is 100 ns, the PCB routing latency is about 10 ns, and a total latency is 450 ns. A sum (200 ns) of the CDR latency in the optical/electrical module and the relay CDR latency is even equivalent to the transmission latency of a 50-meter-long optical fiber, and almost occupies half of the total latency. This greatly increases the transmission latency of the entire link, that is, increases computing waiting time. In this way, an overall computing capability of an HPC cluster is reduced.
Therefore, to resolve a problem that an actual service requirement is not met in a conventional technology, the technical problem to be actually resolved in this application includes the following aspects: Through proper device selection and layout, a signal transmission latency between communication devices is reduced while ensuring signal transmission quality, to reduce computing waiting time and improve an overall computing capability. Optionally, the communication devices include but are not limited to any two devices such as a server, a switch, a storage resource pool, and a random access memory resource pool. For example, the signal transmission latency may be between two servers, between two switches, between a server and a switch, between a server and a random access memory resource pool, between a switch and a storage resource pool, or the like. This is not specifically limited in embodiments of this application.
Each of the plurality of switches, the server array 400, the random access memory resource pool 500, and the storage resource pool 600 may include a digital signal interface unit and an optical/electrical module. In this embodiment of this application, an analog equalizer may be used in each optical/electrical module in the plurality of switches, the server array 400, the random access memory resource pool 500, and the storage resource pool 600 to replace an original CDR. In this way, each node may directly perform analog signal equalization processing on a received high-speed electrical signal (which may be an electrical signal output by the digital signal interface unit of the node to the analog equalizer, or an electrical signal output by an optical/electrical conversion unit of the node to the analog equalizer after conversion of an optical signal output by another node) in an analog domain by using the analog equalizer in the node, to compensate for a loss generated in a transmission process of the received high-speed electrical signal, thereby efficiently and quickly outputting an electrical signal with better quality. This avoids complex and time-consuming processing processes such as digital logic processing and serial-to-parallel conversion while ensuring signal transmission quality, and greatly reduces a signal transmission latency, thereby reducing computing waiting time of each node, and improving an overall computing capability of the HPC cluster.
In an HPC cluster scenario, generally, a baud rate of an electrical signal is greater than a baud rate (Baud/s) of 25 G. For example, if an NRZ coding format is used, a rate of each lane of electrical signal is greater than 25 Gbps, if a PAM4 coding format is used, a rate of each lane of electrical signal is greater than 50 Gbps, if a PAM8 coding format is used, a rate of each lane of high-speed electrical signal is greater than 75 Gbps, and the like. A rate of another coding format is deduced by analogy, and details are not described herein again. As described above, the analog equalizer in this embodiment of this application may be used in processing a high-speed electrical signal (for example, a high-speed electrical signal whose baud rate is greater than a baud rate of 25 G, or even greater than a baud rate of 50 G) at a very high rate.
Further, the foregoing optical fiber may be a solid-core optical fiber, or may be a hollow-core optical fiber. Preferably, the hollow-core optical fiber may be used to replace the solid-core optical fiber, for example, an SMF or an MMF.
First, because a refractive index of a fiber core material used in the solid-core optical fiber is about 1.45, and the hollow-core optical fiber uses air as a transmission medium whose refractive index is about 1, a transmission speed of an optical signal in the hollow-core optical fiber is higher than a transmission speed in the solid-core optical fiber, where the transmission speeds respectively are 300,000 km/s and 207,000 km/s. Latencies needed for transmission of the optical signal through a 1-meter hollow-core optical fiber and a 1-meter solid-core optical fiber respectively are 3.3 ns and 4.8 ns. It is clear that when the optical signal passes through the optical fibers with a same distance, a latency needed by the hollow-core optical fiber is far less than that needed by the solid-core optical fiber, and is generally only 69% of that needed by the solid-core optical fiber.
Second, in the system architecture shown in
It should be noted that the system architecture shown in
As shown in
(1) An example in which the communication device 10 sends a signal to another device is used.
The analog equalizer 103 is configured to: receive a first electrical signal, perform first analog signal equalization processing on the first electrical signal to obtain a second electrical signal, and send the second electrical signal to the optical/electrical conversion unit 104. Optionally, the first electrical signal and the second electrical signal may be analog electrical signals, and inter-symbol interference of the second electrical signal obtained through equalization processing may be less than inter-symbol interference of the first electrical signal.
The optical/electrical conversion unit 104 is configured to: receive the second electrical signal, and convert the second electrical signal into a corresponding first optical signal. Optionally, the first optical signal may be subsequently transmitted to the another device through an optical fiber (for example, a hollow-core optical fiber) connected between the communication device 10 and the another device.
As described above, it should be understood that, in a transmission process before the first electrical signal is input to the analog equalizer 103, a transmission loss (in other words, aberration, where for example, an amplitude, a frequency, and a phase of a signal change, and generally, the loss may mean a decrease in the signal amplitude) is inevitably generated. Therefore, compared with an original first electrical signal (in other words, a first electrical signal at the beginning of transmission), the first electrical signal received by the analog equalizer 103 has signal attenuation and distortion to some extent (where for example, at least one of an amplitude, a frequency, and a phase of the first electrical signal may change, and a typical case is an amplitude decrease and the like), causing severe inter-symbol interference of the first electrical signal received by the analog equalizer 103. It should be noted that the severe inter-symbol interference causes a significant increase in a bit error rate. If no processing is performed, a signal finally received by the another device may be completely incorrect or completely invalid. This severely affects an overall computing capability of the another device and a communication system.
In this way, in this embodiment of this application, efficient and quick analog signal equalization processing may be directly performed on the received first electrical signal in an analog domain by using the analog equalizer 103 added in the optical/electrical module 102, to compensate for the transmission loss generated in the previous transmission process of the first electrical signal, so that the second electrical signal with better signal quality and less signal inter-symbol interference can be output without digital logic processing, serial-to-parallel conversion, and the like. Optionally, the second electrical signal may be as close as possible to the original first electrical signal, even the same as the original first electrical signal, may have less inter-symbol interference than the original first electrical signal, or the like. This is not specifically limited in this embodiment of this application.
In conclusion, when the signal is sent to the another device, the optical/electrical module provided in this embodiment of this application can greatly shorten time consumed for performing signal transmission loss compensation before sending, thereby greatly reducing a transmission latency of transmitting the signal from the communication device 10 to the another device while ensuring signal quality, and reducing computing waiting time of the another device.
(2) An example in which the communication device 10 receives a signal sent by the another device is used.
The optical/electrical conversion unit 104 is configured to: receive a second optical signal, convert the second optical signal into a corresponding third electrical signal, and send the third electrical signal to the analog equalizer 103. Optionally, the second optical signal may be a signal sent by the another device to the optical/electrical conversion unit 104 through the optical fiber.
The analog equalizer 103 is configured to: receive the third electrical signal, and perform second analog signal equalization processing on the third electrical signal to obtain a fourth electrical signal. Optionally, the third electrical signal and the fourth electrical signal may be analog electrical signals, and inter-symbol interference of the fourth electrical signal obtained through equalization processing may be less than inter-symbol interference of the third electrical signal. Optionally, the communication device 10 may subsequently perform a series of computing, analysis, or the like based on the fourth electrical signal.
Optionally, the first electrical signal, the second electrical signal, the third electrical signal, and the fourth electrical signal may be high-speed electrical signals whose baud rate is greater than a baud rate of 25 G, even greater than a baud rate of 50 G, or the like. This is not specifically limited in this embodiment of this application.
As described above, correspondingly, in a transmission process before the third electrical signal is input to the analog equalizer, a transmission loss (in other words, aberration) is inevitably generated. Therefore, the third electrical signal received by the analog equalizer 103 usually has signal attenuation and distortion to some extent, causing severe inter-symbol interference of the third electrical signal received by the analog equalizer 103. Consequently, a signal finally received by the communication device 10 may be completely incorrect or completely invalid. This severely affects an overall computing capability of the communication device 10 and the communication system.
In this way, in this embodiment of this application, efficient and quick analog signal equalization processing may be directly performed on the received third electrical signal in the analog domain by using the analog equalizer 103 added in the optical/electrical module 102, to output the fourth electrical signal with better signal quality and less signal inter-symbol interference. Optionally, the fourth electrical signal may be as close as possible to the third electrical signal originally output by the optical/electrical conversion unit 104, as close as possible to an electrical signal originally output by the another device, even the same as the electrical signal originally output by the another device, may have less inter-symbol interference than the electrical signal originally output by the another device, or the like. This is not specifically limited in this embodiment of this application.
In conclusion, when the signal sent by the another device is received, the optical/electrical module provided in this embodiment of this application can greatly shorten time consumed by the local device (that is, the communication device 10) to perform signal transmission loss compensation before computing, thereby greatly reducing a transmission latency of transmitting the signal from the another device to the communication device 10 while ensuring signal quality, reducing computing waiting time of the communication device 10, and improving the overall computing capability.
Optionally, the communication device 10 may be configured only to send a signal or only to receive a signal. To be specific, the analog equalizer 103 and the optical/electrical conversion unit 104 in the optical/electrical module 102 are configured only to implement the function described in (1) in the foregoing embodiment, or the analog equalizer 103 and the optical/electrical conversion unit 104 are configured only to implement the function described in (2) in the foregoing embodiment. This is not specifically limited in this embodiment of this application.
As shown in
Optionally, refer to the embodiment corresponding to
As shown in
Optionally, the digital signal interface unit 101 and the digital signal interface unit 201 may be any one of a network processing interface unit, a data exchange unit, a storage interface unit, a random access memory interface unit, or the like. This is not specifically limited in this embodiment of this application.
Further, as shown in
With reference to the communication device 10 and the communication device 20 shown in
First, it should be noted that when a signal is transmitted between two communication devices, unflatness characteristics of a transmission parameter of a device and a channel transmission parameter cause signal aberration, resulting in unflatness of a signal amplitude-frequency characteristic, a fluctuation of a group latency characteristic, and the like. Consequently, inter-symbol interference of the signal is extremely severe. That the communication device 10 sends the signal to the communication device 20 is used as an example. Possible signal aberration may roughly include but is not limited to the following:
(1) aberration that may occur during transmission between the digital signal interface unit 101 and the transmit equalizer 103a;
(2) aberration that may occur during transmission between the transmit equalizer 103a and the first optical/electrical converter 105;
(3) aberration that may occur when the first optical/electrical converter 105 converts an electrical signal into an optical signal;
(4) aberration that may occur at a connection between the first optical/electrical converter 105 and the optical fiber 30;
(5) aberration that may occur during transmission of the optical signal in the optical fiber 30;
(6) aberration that may occur at a connection between the optical fiber 30 and the second optical/electrical converter 206;
(7) aberration that may occur when the second optical/electrical converter 206 converts the optical signal into an electrical signal;
(8) aberration that may occur during transmission between the second optical/electrical converter 206 and the receive equalizer 203b; and
(9) aberration that may occur during transmission between the receive equalizer 203b and the digital signal interface unit 201.
Second, functions of each structure in the process are described in detail by using an example in which the communication device 10 sends the signal to the communication device 20. Details are as follows.
The digital signal interface unit 101 receives a first digital electrical signal from a processing device (not shown in
The transmit equalizer 103a receives the first electrical signal, and performs analog signal equalization processing on the first electrical signal in an analog domain, to compensate for aberration (for example, including the foregoing aberration (1)) of the first electrical signal in a previous transmission process, and reduce inter-symbol interference of the first electrical signal, so that a second electrical signal is obtained, and then the second electrical signal is sent to the first optical/electrical converter 105.
Optionally, considering that a large quantity of aberration (for example, at least one of the foregoing distortion (2), (3), (4), (5), (6), (7), and (8)) may exist in a subsequent transmission process of the electrical signal, and that a high-frequency part of the electrical signal is likely to have severe attenuation, therefore, to ensure that an electrical signal received by the receive equalizer 203b in the communication device 20 has no severe inter-symbol interference, the transmit equalizer 103a may further perform pre-equalization processing on the first electrical signal. For example, a low-frequency part of the first electrical signal may be properly attenuated, so that compared with a case in which the pre-equalization processing is not performed, an amplitude difference between a high-frequency part and a low-frequency part of the electrical signal subsequently received by the receive equalizer 203b in the communication device 20 may be reduced. This reduces inter-symbol interference of the electrical signal received by the receive equalizer 203b, and the like. This is not specifically limited in this embodiment of this application.
The first optical/electrical converter 105 receives the second electrical signal, converts the second electrical signal into a corresponding first optical signal, and inputs the first optical signal to the optical fiber 30.
The optical fiber 30 receives the first optical signal, and then sends the first optical signal to the second optical/electrical converter 206 in the communication device 20.
The second optical/electrical converter 206 receives the first optical signal, converts the first optical signal into a corresponding electrical signal (for example, a third electrical signal), and sends the third electrical signal to the receive equalizer 203b. It may be understood that, because structures of the communication device 10 and the communication device 20 are similar, and sending and receiving are symmetrical, the first optical signal received by the communication device 20 is equivalent to the second optical signal received by the communication device 10 in the embodiment in
The receive equalizer 203b receives the third electrical signal, and performs analog signal equalization processing on the third electrical signal in the analog domain, to compensate for aberration (for example, including the foregoing aberration (2), (3), (4), (5), (6), (7), and (8)) of the third electrical signal in a previous transmission process, and reduce inter-symbol interference of the third electrical signal, so that a fourth electrical signal is obtained, and then the fourth electrical signal is sent to the digital signal interface unit 201. Optionally, correspondingly, in consideration of possible aberration in a process in which the signal is subsequently transmitted to the digital signal interface unit 201, therefore, to ensure that inter-symbol interference of an electrical signal received by the digital signal interface unit 201 is still low or even zero, the receive equalizer 203b may further perform pre-equalization processing or the like on the third electrical signal. This is not specifically limited in this embodiment of this application.
The digital signal interface unit 201 receives the fourth electrical signal, converts the fourth electrical signal into a corresponding digital electrical signal (for example, a second digital electrical signal), and sends the second digital electrical signal to a processing device in the communication device 20, so that the processing device in the communication device 20 can perform a series of computing, analysis, or the like based on the second digital electrical signal.
So far, an entire process in which the communication device 10 sends the signal to the communication device 20 is completed. It may be understood that this application aims to directly perform equalization processing on the signal in the analog domain by disposing the analog equalizer in the optical/electrical module, to compensate for aberration generated in the signal transmission process, thereby achieving short time consumption and effectively ensuring quality of the fourth electrical signal or even the second digital electrical signal finally received by the communication device 20. Optionally, through equalization processing performed by the analog equalizer, the fourth electrical signal or the second digital electrical signal finally received by the communication device 20 may be as close as possible to the first electrical signal or the first digital electrical signal initially output by the communication device 10, or even the same as the first electrical signal or the first digital electrical signal, thereby ensuring effective and reliable signal transmission.
It may be understood that, because the structures of the communication device 20 and the communication device 10 are similar, similarly, for a process in which the communication device 20 sends a signal to the communication device 10, refer to the foregoing process in which the communication device 10 sends the signal to the communication device 20. Details are not described herein again.
Refer to Table 1 shown below. It can be learned, with reference to the embodiments described in
(1) In this embodiment of this application, the analog equalizer is used to replace an original CDR. Compared with the original CDR, the analog equalizer has no large latency caused by digital logic processing, serial-to-parallel conversion, and the like, and only a routing latency of an electrical signal in the analog equalizer exists. As an integrated circuit chip, the analog equalizer has a very short internal routing length, and the caused latency is negligible and almost zero, thereby reducing a latency by about 100 ns.
(2) In this embodiment of this application, the hollow-core optical fiber is used to replace an original solid-core optical fiber (an SMF, an MMF, or the like) and is used as a transmission channel between communication devices (in other words, nodes). For example, transmission through an optical fiber whose length is 50 m is used as an example. In this embodiment of this application, a latency is reduced by about 75 ns.
For a specific latency and a ratio, refer to content in the following Table 1. Details are not described herein again.
Optionally,
The communication device 10 is used as an example. Two ends of the high-speed passive component 107 are respectively connected to the digital signal interface unit 101 and the analog equalizer 103 in an optical/electrical module 102, so that a high-speed electrical signal transmission channel with a low latency, a low insertion loss, and low aberration may be provided between the digital signal interface unit 101 and the analog equalizer 103, and a transmission latency of the channel is almost zero. In this way, even if the analog equalizer 103 is deployed at a position far away from the digital signal interface unit, a transmission latency, a transmission loss, and aberration of a high-speed electrical signal (for example, a first electrical signal or a fourth electrical signal) in a transmission process between the digital signal interface unit 101 and the analog equalizer 103 can be reduced. Therefore, compared with the communication system shown in
As shown in (a) in
Optionally, the digital signal interface unit 101 may be included in a packaged integrated circuit chip. As shown in (a) in
Optionally, the high-speed connector 01 may be deployed at a position that is on the PCB and that is close to the digital signal interface unit 101 (in other words, close to the integrated circuit chip). The high-speed connector 01 is connected to the high-speed connector 02 through the high-speed cable 03, so that the high-speed passive component 107 shown in
Optionally, the high-speed connector 02 and the optical/electrical module 102 may be connected on a panel shown in
Optionally, the optical/electrical module 102 is connected to an optical fiber 30, and is configured to: input/output an optical signal, perform corresponding optical/electrical conversion, and the like. Details are not described herein again.
In conclusion, that the communication device 10 sends a signal to the communication device 20 is used as an example. As shown in (a) in
As shown in (b) in
Optionally, the digital signal interface unit 101 may be included in an integrated circuit chip (where the integrated circuit chip may be unpackaged). As shown in (b) in
Optionally, the high-speed connector 01 may be deployed at a position that is on the substrate and that is close to the digital signal interface unit 101 (in other words, close to the integrated circuit chip).
Optionally, for descriptions of (b) in
In conclusion, that the communication device 10 sends a signal to the communication device 20 is still used as an example. As shown in (b) in
As shown in (c) in
Optionally, the digital signal interface unit 101 may be included in a packaged integrated circuit chip. As shown in (c) in
Optionally, the high-speed connector 01 may be deployed at a position that is on the PCB and that is close to the digital signal interface unit 101 (in other words, close to the integrated circuit chip), and is configured to connect the digital signal interface unit 101 to the optical/electrical module 102, and is specifically configured to connect the digital signal interface unit 101 to an analog equalizer 103 in the optical/electrical module 102. Optionally, the high-speed passive component 107 or the high-speed passive component 207 shown in
Optionally, as shown in (c) in
Optionally, as shown in (c) in
In conclusion, that the communication device 10 sends a signal to the communication device 20 is still used as an example. As shown in (c) in
As shown in (d) in
Optionally, the digital signal interface unit 101 may be included in an integrated circuit chip (where the integrated circuit chip may be unpackaged). As shown in (d) in
Optionally, the high-speed connector 01 may be deployed at a position that is on the substrate and that is close to the digital signal interface unit 101 (in other words, close to the integrated circuit chip).
Optionally, for descriptions of (d) in
In conclusion, that the communication device 10 sends a signal to the communication device 20 is still used as an example. As shown in (d) in
Refer to Table 2 shown below. It can be learned, with reference to the embodiments corresponding to
(1) In this embodiment of this application, a high-speed passive component combination is used to replace an original relay CDR, and is configured to connect the digital signal interface unit to the optical/electrical module, thereby reducing a latency by about 100 ns.
(2) In this embodiment of this application, the analog equalizer is used to replace an original CDR, so that complex digital logic processing, serial-to-parallel conversion, and the like are avoided, thereby reducing a latency by about 100 ns.
(3) In this embodiment of this application, the hollow-core optical fiber is used to replace an original solid-core optical fiber (an SMF, an MMF, or the like) and is used as a transmission channel between communication devices (in other words, nodes). For example, transmission through an optical fiber whose length is 50 m is used as an example. In this embodiment of this application, a latency is reduced by about 75 ns.
For a specific latency and a ratio, refer to content in the following Table 2. Details are not described herein again.
Further, as described above, to overcome signal aberration caused by unflatness characteristics of a device and a channel (that is, a channel through which a signal passes in a process of transmission between devices), an equalizer needs to be added in a necessary place (for example, between the digital signal interface unit 101 and the optical/electrical conversion unit 104) to eliminate the signal aberration, to compensate for an unflatness change caused by the device and the channel, thereby reducing the signal aberration. The analog equalizer used in this embodiment of this application is mainly configured to correct an amplitude, a frequency characteristic, a phase frequency characteristic, and the like of a transmitted signal. Optionally, analysis and design may be performed on an amplitude equalizer and a phase equalizer, to obtain the analog equalizer in this embodiment of this application. A design indicator of the analog equalizer may mainly relate to equalization bandwidth, an equalization amount, and the like. This is not specifically limited in this embodiment of this application.
In view of this,
First, a process in which the analog equalizer 103 performs analog signal equalization processing is described in detail by using the transmit equalizer 103a as an example.
An input end of the input amplification circuit 1030 may be connected to a digital signal interface unit 101 (or connected to a high-speed passive component 107), and is configured to: receive a high-speed electrical signal (for example, a first electrical signal) output by the digital signal interface unit 101, amplify the first electrical signal to obtain a first electrical signal-A, and send the first electrical signal-A to the continuous time linear equalizer 1031.
The continuous time linear equalizer 1031 is configured to: receive the first electrical signal-A, compensate for a signal transmission loss of a high-frequency part (in other words, a high-frequency component) of the first electrical signal-A, to reduce inter-symbol interference of the high-frequency part of the first electrical signal-A to obtain a first electrical signal-B, and then send the first electrical signal-B to the low frequency equalizer 1032.
The low frequency equalizer 1032 is configured to: receive the first electrical signal-B, compensate for a signal transmission loss of a low-frequency part (in other words, a low-frequency component) of the first electrical signal-B, to reduce inter-symbol interference of the low-frequency part of the first electrical signal-B to obtain a first electrical signal-C, and then send the first electrical signal-C to the level mismatch compensation circuit 1033.
The level mismatch compensation circuit 1033 may include a decision feedback equalizer (DFE), and is configured to: receive the first electrical signal-C, compensate for a signal transmission loss of a high-frequency part of the first electrical signal-C by using the DFE, to reduce inter-symbol interference of the high-frequency part of the first electrical signal-C to obtain a first electrical signal-D, and then send the first electrical signal-D to the output amplification circuit 1034. Optionally,
An output end of the output amplification circuit 1034 may be connected to a first optical/electrical converter 105, and is configured to: receive and amplify the first electrical signal-D to obtain a second electrical signal, and then send the second electrical signal to the first optical/electrical converter 105. Optionally, the output amplification circuit 1034 may further include a feed forward equalizer (FFE). As described above, considering a loss existing in a subsequent signal transmission process, the FFE may further perform pre-equalization processing on the first electrical signal-D, and properly attenuate a low-frequency part of the first electrical signal-D, to obtain the second electrical signal. As described above, after the pre-equalization processing, it can be ensured that an amplitude difference between a high-frequency part and a low-frequency part of an electrical signal subsequently received by another device becomes smaller, that is, it can be ensured that inter-symbol interference of the electrical signal received by the another device is small.
In conclusion,
Second, because structures of the transmit equalizer 103a and the receive equalizer 103b are similar, a process in which the receive equalizer 103b performs analog signal equalization processing is briefly described below with reference to the structure of the receive equalizer 103b shown in
A high-speed electrical signal (for example, a third electrical signal) output by a second optical/electrical converter 106 is first received and amplified by the input amplification circuit 1035 in the receive equalizer 103b, and then the amplified third electrical signal sequentially passes through the continuous time linear equalizer 1036, the low frequency equalizer 1037, and the level mismatch compensation circuit 1038, to respectively compensate a high-frequency part and a low-frequency part of the third electrical signal, thereby reducing inter-symbol interference of the third electrical signal. Finally, a high-speed electrical signal (for example, a fourth electrical signal) with better quality and less inter-symbol interference is output after the output amplification circuit 1039 performs amplification.
Optionally, for detailed descriptions of the receive equalizer 103b, refer to the descriptions of the transmit equalizer 103a. Details are not described herein again.
It should be understood that the structure shown in
With reference to the analog equalizer 103 shown in
As shown in
As shown in
As shown in
As shown in
As shown in
Further, based on the optical/electrical module described in the foregoing embodiment, an embodiment of this application further provides an active optical cable.
Refer to
Based on the various optical/electrical modules shown in
As shown in
As shown in
As shown in
As shown in
As shown in
Correspondingly, after being multiplexed by the WDM-B, the λb optical signal output by the TX-B of the optical/electrical module B is input to the hollow-core optical fiber 1. Subsequently, the WDM-A of the optical/electrical module A receives the λb optical signal from the hollow-core optical fiber 1, and inputs the λb optical signal obtained through demultiplexing to the RX-A of the optical/electrical module A. Details are not described herein again.
As shown in
As shown in
As shown in
Correspondingly, in the active optical cable (c), optical signals output by the TX-B1, the TX-B2, the TX-B3, and the TX-B4 of the optical/electrical module B are respectively input to the hollow-core optical fiber 5, the hollow-core optical fiber 6, the hollow-core optical fiber 7, and the hollow-core optical fiber 8. Subsequently, the RX-A1, the RX-A2, the RX-A3, and the RX-A4 of the optical/electrical module A respectively receive the optical signals from the hollow-core optical fiber 5, the hollow-core optical fiber 6, the hollow-core optical fiber 7, and the hollow-core optical fiber 8.
It should be noted that, as shown in the active optical cable (c) in
As shown in
As shown in
As shown in
As shown in
Correspondingly, after being multiplexed by the WDM-TX B, the λb1 optical signal, the λb2 optical signal, the λb3 optical signal, and the λb4 optical signal that are respectively output by the TX-B1, the TX-B2, the TX-B3, and the TX-B4 of the optical/electrical module B are input to the hollow-core optical fiber 2. Subsequently, the WDM-RX A of the optical/electrical module A receives a multiplexed optical signal from the hollow-core optical fiber 2, and respectively inputs the λb1 optical signal, the λb2 optical signal, the λb3 optical signal, and the λb4 optical signal that are obtained through demultiplexing to the RX-A1, the RX-A2, the RX-A3, and the RX-A4 of the optical/electrical module A. Details are not described herein again.
It should be noted that, as shown in the active optical cable (d) in
Based on the active optical cable (d) shown in
As shown in
Optionally, as shown in the active optical cable (e) in
In conclusion, embodiments of this application provide an optical/electrical module. According to a method in which an analog equalizer is used in the optical/electrical module to replace an original CDR, equalization processing is directly performed on a received electrical signal in an analog domain, to reduce inter-symbol interference of the signal. It is clear that using the analog equalizer can directly avoid complex and time-consuming processes of operations such as digital logic processing and a plurality of times of serial-to-parallel conversion. In this way, a transmission latency of the signal in the optical/electrical module is greatly reduced while ensuring signal quality, thereby reducing computing waiting time of a device, and improving an overall computing capability.
In addition, in embodiments of this application, according to a method in which a high-speed passive component is used to replace an original relay CDR, in a scenario of transmitting a high-speed electrical signal, a signal transmission loss and a signal transmission latency of the signal between a digital signal interface unit and the optical/electrical module can be further reduced.
In addition, in embodiments of this application, according to a method in which a hollow-core optical fiber is used to replace an original solid-core optical fiber, a transmission latency of the signal in the optical fiber is further reduced. As described above, according to embodiments of this application, a transmission latency of transmitting a signal from one device to another device can be minimized while ensuring signal transmission quality. In short, it can be effectively ensured that a communication device in one communication system can receive a high-quality signal in extremely short time, so that a computing capability of the entire communication system can be greatly improved.
Further, based on the optical/electrical module provided in embodiments of this application, embodiments of this application further provide an active optical cable, where two optical/electrical modules may be directly coupled to two ends of the hollow-core optical fiber and packaged into a whole. In this way, compared with a solution of an original technology in which the optical/electrical module is located inside the communication device, and can be connected to the optical fiber only by using an adapter, causing a large insertion loss, the active optical cable provided in embodiments of this application can well reduce or even avoid an insertion loss between the optical/electrical module and the optical fiber. This is equivalent to that only a loss generated when an optical signal is transmitted inside the optical fiber may be left in an insertion loss of the optical signal. Therefore, signal transmission quality can be further ensured. In addition, in an actual application, only two ends of the active optical cable need to be respectively connected to two communication devices. This is convenient to operate.
Step S301: Perform first analog signal equalization processing on a first electrical signal by using the analog equalizer in the optical/electrical module to obtain a second electrical signal, and send the second electrical signal to the optical/electrical conversion unit, or receive a third electrical signal from the optical/electrical conversion unit by using the analog equalizer, and perform second analog signal equalization processing on the third electrical signal to obtain a fourth electrical signal. Step S302: Receive the second electrical signal from the analog equalizer by using the optical/electrical conversion unit in the optical/electrical module, and convert the second electrical signal into a first optical signal, or convert a second optical signal into the third electrical signal by using the optical/electrical conversion unit, and send the third electrical signal to the analog equalizer.
In some possible implementations, the method may specifically include: receiving the second electrical signal from the analog equalizer by using a first optical/electrical converter in the optical/electrical conversion unit and converting the second electrical signal into the first optical signal; and performing the first analog signal equalization processing on the first electrical signal by using a transmit equalizer in the analog equalizer to obtain the second electrical signal, and sending the second electrical signal to the first optical/electrical converter.
In some possible implementations, the method may specifically include: converting the second optical signal into the third electrical signal by using a second optical/electrical converter in the optical/electrical conversion unit and sending the third electrical signal to the analog equalizer; and receiving the third electrical signal from the second optical/electrical converter by using a receive equalizer in the analog equalizer, and performing the second analog signal equalization processing on the third electrical signal to obtain the fourth electrical signal.
Optionally, for details of the communication method in which the optical/electrical module is used, refer to the descriptions of the embodiments corresponding to
Optionally, each method procedure in the communication method in which the optical/electrical module is used and that is described in this embodiment of this application may be specifically implemented based on software, hardware, or a combination thereof. A hardware implementation may include a logic circuit, an algorithm circuit, an analog circuit, or the like. A software implementation may include program instructions. The program instructions may be considered as a software product, stored in a memory, and may be run by a processor to implement a related function.
An embodiment of this application further provides a computer-readable storage medium, where the computer-readable storage medium may store a program. When the program is executed by a processor, the processor is enabled to perform some or all steps recorded in any one of the foregoing method embodiments.
An embodiment of this application further provides a computer program, where the computer program includes instructions. When the computer program is executed by a multi-core processor, the processor is enabled to perform some or all steps recorded in any one of the foregoing method embodiments.
In the foregoing embodiments, the descriptions of the embodiments have respective focuses. For a part that is not described in detail in an embodiment, refer to related descriptions of another embodiment. It should be noted that, for brief description, the foregoing method embodiments are represented as a series of actions. However, persons skilled in the art should understand that this application is not limited to the described order of the actions, because according to this application, some steps may be performed in other orders or simultaneously. In addition, persons skilled in the art should further understand that embodiments described in this specification all belong to example embodiments, and the involved actions and modules are not necessarily required by this application.
In several embodiments provided in this application, it should be understood that the disclosed apparatus may be implemented in another manner. For example, the described apparatus embodiment is merely an example. For example, division into the units is merely logical function division and may be other division in actual implementation. For example, a plurality of units or components may be combined or integrated into another system, or some features may be ignored or not performed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections may be implemented through some interfaces. The indirect couplings or communication connections between the apparatuses or units may be implemented in electrical or another form.
The foregoing units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one position, or may be distributed on a plurality of network units. Some or all of the units may be selected based on actual requirements to achieve the objectives of the solutions of embodiments.
In addition, functional units in embodiments of this application may be integrated into one processing unit, or each of the units may exist alone physically, or two or more units may be integrated into one unit. The integrated unit may be implemented in a form of hardware, or may be implemented in a form of a software functional unit.
When the integrated unit is implemented in the form of the software functional unit and sold or used as an independent product, the integrated unit may be stored in a computer-readable storage medium. Based on such an understanding, the technical solutions of this application essentially, or the part contributing to the conventional technology, or all or some of the technical solutions may be implemented in a form of a software product. The computer software product is stored in a storage medium and includes several instructions for instructing a computer device (which may be a personal computer, a server, a network device, or the like, and may specifically be a processor in the computer device) to perform all or some of the steps of the methods described in embodiments of this application. The foregoing storage medium may include any medium that can store program code, such as a USB flash drive, a removable hard disk, a magnetic disk, an optical disc, a read-only memory (ROM), a double data rate synchronous dynamic random access memory (DDR), a flash, or a random access memory (RAM).
The foregoing embodiments are merely intended for describing the technical solutions of this application, but not for limiting this application. Although this application is described in detail with reference to the foregoing embodiments, persons of ordinary skill in the art should understand that they may still make modifications to the technical solutions recorded in the foregoing embodiments or make equivalent replacements to some technical features thereof. Such modifications or replacements do not make the essence of the corresponding technical solutions depart from the spirit and the scope of the technical solutions of embodiments of this application.
This application is a continuation of International Application No. PCT/CN2021/107037, filed on Jul. 19, 2021, the disclosure of which is hereby incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2021/107037 | Jul 2021 | US |
| Child | 18416436 | US |
