The present disclosure generally relates to a method of performing computation in a quantum computing system, and more specifically, to a method of optimizing resource for calibrating quantum gate operations to execute a series of quantum gate operations in a quantum computing system that includes a group of trapped ions.
Among physical systems upon which it is proposed to build large-scale quantum computers, is a group of ions (e.g., charged atoms), which are trapped and suspended in vacuum by electromagnetic fields. The ions have internal hyperfine states which are separated by frequencies in the several GHz range and can be used as the computational states of a qubit (referred to as “qubit states”). These hyperfine states can be controlled using radiation provided from a laser, or sometimes referred to herein as the interaction with laser beams. The ions can be cooled to near their motional ground states using such laser interactions. The ions can also be optically pumped to one of the two hyperfine states with high accuracy (preparation of qubits), manipulated between the two hyperfine states (single-qubit gate operations) by laser beams, and their internal hyperfine states detected by fluorescence upon application of a resonant laser beam (read-out of qubits). A pair of ions can be controllably entangled (two-qubit gate operations) by qubit-state dependent force using laser pulses that couple the ions to the collective motional modes of a group of trapped ions, which arise from their Coulombic interaction between the ions. In general, entanglement occurs when pairs or groups of ions (or particles) are generated, interact, or share spatial proximity in ways such that the quantum state of each ion cannot be described independently of the quantum state of the others, even when the ions are separated by a large distance.
Quantum computation can be performed by executing a set of single-qubit gate operations and two-qubit gate operations in such a quantum computing system. Although the methods for applying these basic building blocks of quantum computation have been established, there are control errors that result from m is-calibration of control parameters, such as a frequency or an amplitude of a laser pulse to be applied to a qubit, in hardware in the quantum computing system. These control errors are mainly due to the lack of knowledge about how the ions will interact and the properties of quantum computing hardware within the quantum computing system. Thus, the control parameters in the quantum computing system need to be corrected (i.e., calibrated) to perform reliable and scalable quantum computation. However, calibration typically requires repeated measurements of qubits to collect statistics over a sizable parameter space of the control parameters of the quantum computing system. Thus, calibration can be an expensive and time-consuming task.
Therefore, there is a need for a method of minimizing resource for calibrating control parameters within an acceptable error in quantum computation.
Embodiments of the present disclosure provide a method of performing a quantum computation process. The method includes mapping, by a classical computer, a plurality of logical qubits to a plurality of physical qubits of a quantum processor so that a plurality of quantum circuits are executable using the physical qubits of the quantum processor and a total infidelity of the plurality of quantum circuits is minimized, wherein each of the physical qubits comprise a trapped ion, and each of the plurality of quantum circuits comprises a plurality of single-qubit gates and a plurality of two-qubit gates within the plurality of the logical qubits, calibrating, by a system controller, two-qubit gates within a first plurality of pairs of physical qubits, such that infidelity of the two-qubit gates within the first plurality of pairs of physical qubit is lowered, executing the plurality of quantum circuits on the quantum processor, by applying laser pulses that each cause a single-qubit gate operation and a two-qubit gate operation in each of the plurality of quantum circuits on the plurality of physical qubits, measuring, by the system controller, population of qubit states of the physical qubits in the quantum processor after executing the plurality of quantum circuits on the quantum processor, and outputting, by the classical computer, the measured population of qubit states of the physical qubits as a result of the execution the plurality quantum circuits, wherein the result of the execution the plurality quantum circuits are configured to be displayed on a user interface, stored in a memory of the classical computer, or transferred to another computational device.
Embodiments of the present disclosure also provide a quantum computing system. The quantum computing system includes a quantum processor comprising a plurality of physical qubits, wherein each of the physical qubits comprises a trapped ion, a classical computer configured to map a plurality of logical qubits to the plurality of physical qubits so that a plurality of quantum circuits are executable using the physical qubits and a total infidelity of the plurality of quantum circuits is minimized, wherein each of the plurality of quantum circuits comprises a plurality of single-qubit gates and a plurality of two-qubit gates within the plurality of the logical qubits, and a system controller configured to calibrate two-qubit gates within a first plurality of pairs of physical qubits, such that infidelity of the two-qubit gates within the first plurality of pairs of physical qubit is lowered, executing the plurality of quantum circuits on the quantum processor, by applying laser pulses that each cause a single-qubit gate operation and a two-qubit gate operation in each of the plurality of quantum circuits on the plurality of physical qubits, and measure population of qubit states of the physical qubits in the quantum processor after executing the plurality of quantum circuits on the quantum processor, wherein the classical computer is further configured to output the measured population of qubit states of the physical qubits as a result of the execution the plurality quantum circuits, wherein the result of the execution the plurality quantum circuits are configured to be displayed on a user interface, stored in a memory of the classical computer, or transferred to another computational device.
Embodiments of the present disclosure further provide a quantum computing system comprising non-volatile memory having a number of instructions stored therein. The number of instructions, when executed by one or more processors, causes the quantum computing system to perform operations including mapping, by a classical computer, a plurality of logical qubits to a plurality of physical qubits of a quantum processor so that a plurality of quantum circuits are executable using the physical qubits of the quantum processor and a total infidelity of the plurality of quantum circuits is minimized, wherein each of the physical qubits comprise a trapped ion, and each of the plurality of quantum circuits comprises a plurality of single-qubit gates and a plurality of two-qubit gates within the plurality of the logical qubits, calibrating, by a system controller, two-qubit gates within a first plurality of pairs of physical qubits, such that infidelity of the two-qubit gates within the first plurality of pairs of physical qubit is lowered, executing the plurality of quantum circuits on the quantum processor, by applying laser pulses that each cause a single-qubit gate operation and a two-qubit gate operation in each of the plurality of quantum circuits on the plurality of physical qubits, measuring, by the system controller, population of qubit states of the physical qubits in the quantum processor after executing the plurality of quantum circuits on the quantum processor, and outputting, by the classical computer, the measured population of qubit states of the physical qubits as a result of the execution the plurality quantum circuits, wherein the result of the execution the plurality quantum circuits are configured to be displayed on a user interface, stored in a memory of the classical computer, or transferred to another computational device.
So that the manner in which the above-recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. In the figures and the following description, an orthogonal coordinate system including an X-axis, a Y-axis, and a Z-axis is used. The directions represented by the arrows in the drawing are assumed to be positive directions for convenience. It is contemplated that elements disclosed in some embodiments may be beneficially utilized on other implementations without specific recitation.
Embodiments described herein are generally related to a method of performing a computation in a quantum computing system, and more specifically, to a method of optimizing resources required to perform a series of quantum gate operations in a quantum computing system that includes a group of trapped ions. The method can include a process of calibrating aspects of the quantum gate operations used in the computational process performed by a quantum computing system.
Embodiments of the disclosure include a quantum computing system that is able to perform a quantum computation process by use of a classical computer, a system controller, and a quantum processor. The classical computer performs supporting tasks including selecting a quantum algorithm to be used, computing quantum circuits to run the quantum algorithm, and outputting results of the execution of the quantum circuits by use of a user interface. A software program for performing the tasks is stored in a non-volatile memory within the classical computer. The quantum processor includes trapped ions that are coupled with various hardware, including lasers to manipulate internal hyperfine states (qubit states) of the trapped ions and photomultiplier tubes (PMTs) to read-out the internal hyperfine states (qubit states) of the trapped ions. The system controller receives from the classical computer instructions for controlling the quantum processor, and controls various hardware associated with controlling any and all aspects used to run the instructions for controlling the quantum processor, and transmits a read-out of the quantum processor and thus output of results of the read-out to the classical computer. In some embodiments, the classical computer will then utilize the computational results based on the output of results of the read-out to form a results set that is then provided to a user the form of results displayed on a user interface, stored in a memory and/or transferred to another computational device for solving technical problems.
An imaging objective 108, such as an objective lens with a numerical aperture (NA), for example, of 0.37, collects fluorescence along the Y-axis from the ions and maps each ion onto a multi-channel photo-multiplier tube (PMT) 110 for measurement of individual ions. Non-copropagating Raman laser beams from a laser 112, which are provided along the X-axis, perform operations on the ions. A diffractive beam splitter 114 creates an array of static Raman beams 116 that are individually switched using a multi-channel acousto-optic modulator (AOM) 118 and is configured to selectively act on individual ions. A global Raman laser beam 120 is configured to illuminate all ions at once. In some embodiments, individual Raman laser beams (not shown) each illuminate individual ions. The system controller (also referred to as a “RF controller”) 104 controls the AOM 118 and thus controls laser pulses to be applied to trapped ions in the group 106 of trapped ions. The system controller 104 includes a central processing unit (CPU) 122, a read-only memory (ROM) 124, a random access memory (RAM) 126, a storage unit 128, and the like. The CPU 122 is a processor of the system controller 104. The ROM 124 stores various programs and the RAM 126 is the working memory for various programs and data. The storage unit 128 includes a nonvolatile memory, such as a hard disk drive (HDD) or a flash memory, and stores various programs even if power is turned off. The CPU 122, the ROM 124, the RAM 126, and the storage unit 128 are interconnected via a bus 130. The system controller 104 executes a control program which is stored in the ROM 124 or the storage unit 128 and uses the RAM 126 as a working area. The control program will include software applications that include program code that may be executed by processor in order to perform various functionalities associated with receiving and analyzing data and controlling any and all aspects of the methods and hardware used to create the ion trap quantum computer system 100 discussed herein.
During operation, a sinusoidal voltage V1 (with an amplitude VRF/2) is applied to an opposing pair of the electrodes 202, 204 and a sinusoidal voltage V2 with a phase shift of 180° from the sinusoidal voltage V1 (and the amplitude VRF/2) is applied to the other opposing pair of the electrodes 206, 208 at a driving frequency ωRF, generating a quadrupole potential. In some embodiments, a sinusoidal voltage is only applied to one opposing pair of the electrodes 202, 204, and the other opposing pair 206, 208 is grounded. The quadrupole potential creates an effective confining force in the X-Y plane perpendicular to the Z-axis (also referred to as a “radial direction” or “transverse direction”) for each of the trapped ions, which is proportional to a distance from a saddle point (i.e., a position in the axial direction (Z-direction)) at which the RF electric field vanishes. The motion in the radial direction (i.e., direction in the X-Y plane) of each ion is approximated as a harmonic oscillation (referred to as secular motion) with a restoring force towards the saddle point in the radial direction and can be modeled by spring constants kx, and ky, respectively, as is discussed in greater detail below. In some embodiments, the spring constants in the radial direction are modeled as equal when the quadrupole potential is symmetric in the radial direction. However, undesirably in some cases, the motion of the ions in the radial direction may be distorted due to some asymmetry in the physical trap configuration, a small DC patch potential due to inhomogeneity of a surface of the electrodes, or the like and due to these and other external sources of distortion the ions may lie off-center from the saddle points.
An individual qubit state of each trapped ion may be manipulated by, for example, a mode-locked laser at 355 nanometers (nm) via the excited 2P1/2 level (denoted as |e). As shown in
It should be noted that the particular atomic species used in the discussion provided herein is just one example of atomic species which have stable and well-defined two-level energy structures when ionized and an excited state that is optically accessible, and thus is not intended to limit the possible configurations, specifications, or the like of an ion trap quantum computer according to the present disclosure. For example, other ion species include alkaline earth metal ions (Be+, Ca+, Sr+, Mg+, and Ba+) or transition metal ions (Zn+, Hg+, Cd+).
It should be noted that the particular configuration described above is just one among several possible examples of a trap for confining ions according to the present disclosure and does not limit the possible configurations, specifications, or the like of traps according to the present disclosure. For example, the geometry of the electrodes is not limited to the hyperbolic electrodes described above. In other examples, a trap that generates an effective electric field causing the motion of the ions in the radial direction as harmonic oscillations may be a multi-layer trap in which several electrode layers are stacked and an RF voltage is applied to two diagonally opposite electrodes, or a surface trap in which all electrodes are located in a single plane on a chip. Furthermore, a trap may be divided into multiple segments, adjacent pairs of which may be linked by shuttling one or more ions, or coupled by photon interconnects. A trap may also be an array of individual trapping regions arranged closely to each other on a micro-fabricated ion trap chip. In some embodiments, the quadrupole potential has a spatially varying DC component in addition to the RF component described above.
In an ion trap quantum computer, the motional modes may act as a data bus to mediate entanglement between two qubits and this entanglement is used to perform an XX gate operation. That is, each of the two qubits is entangled with the motional modes, and then the entanglement is transferred to an entanglement between the two qubits by using motional sideband excitations, as described below.
By controlling and/or directing transformations of the combined qubit-motional states as described above, an X)(-gate operation may be performed on two qubits (i-th and j-th qubits). In general, the XX-gate operation (with maximal entanglement) respectively transforms two-qubit states |0i|0j, |0i|1j, |1i|0)j, and |1i|1j as follows:
|0i|0j→|0i|0j−i|1i|1j
|0i|1j→|0i|1j−i|1i|0j
|1i|0j→−i|0i|1j+|1i|0j
|1i|1j→−i|0i|0j+|1i|1j For example, when the two qubits (i-th and j-th qubits) are both initially in the hyperfine ground state |0(denoted as |0i|0j) and subsequently a π/2-pulse on the blue sideband is applied to the i-th qubit, the combined state of the i-th qubit and the motional mode |0i|nphm is transformed into a superposition of |0i|nphm and |1i|nph+1m, and thus the combined state of the two qubits and the motional mode is transformed into a superposition of |0i|0j|nphm and |1|i|0j|nph+1m. When a π/2-pulse on the red sideband is applied to the j-th qubit, the combined state of the j-th qubit and the motional mode |0j|nphm is transformed to a superposition of |0j|nphm and |1j|nph−1m and the combined state 0j|nph+1m is transformed into a superposition of |0j|nph+1m and |1j|nphm.
Thus, applications of a π/2-pulse on the blue sideband on the i-th qubit and a π/2-pulse on the red sideband on the j-th qubit may transform the combined state of the two qubits and the motional mode |0i|0)j|nphm into a superposition of |0i|0j|nphm and |1i1j|nphm, the two qubits now being in an entangled state. For those of ordinary skill in the art, it should be clear that two-qubit states that are entangled with motional mode having a different number of phonon excitations from the initial number of phonon excitations nph (i.e., |1i|0j|nph+1m and |0i|1j|nph−1m) can be removed by a sufficiently complex pulse sequence, and thus the combined state of the two qubits and the motional mode after the XX-gate operation may be considered disentangled as the initial number of phonon excitations nph in the m-th motional mode stays unchanged at the end of the XX-gate operation. Thus, qubit states before and after the XX-gate operation will be described below generally without including the motional modes.
More generally, the combined state of i-th and j-th qubits transformed by the application of pulses on the sidebands for duration τ (referred to as a “gate duration”), having amplitudes Ω(i) and Ω(j) and detuning frequency μ, can be described in terms of an entangling interaction X(i,j)(τ) as follows:
|0i|0j→cos(2X(i,j)(τ))|0i|0j−i sin(2X(i,j)(τ))|1i|1j
|0i|1j→cos(2X(i,j)(τ))|0i|1j−i sin(2X(i,j)(τ))|1i|0j
|1i|0j→−i sin(2X(i,j)(τ))|0i|1nj+cos(2X(i,j)(τ))|1i|0j
|1i|1j→−i sin(2X(i,j)(τ))|0i|0j+cos(2X(i,j)(τ))|1i|1j where,
and ηm(i) is the Lamb-Dicke parameter that quantifies the coupling strength between the i-th ion and the m-th motional mode having the frequency ωm, and M is the number of the motional modes (equal to the number N of ions in the group 106).
The entanglement interaction between two qubits described above can be used to perform an XX-gate operation. The XX-gate operation (XX gate) along with single-qubit gate operations (R gates) forms a set of gates {R, XX} that can be used to build a quantum computer that is configured to perform desired computational processes. Among several known sets of logic gates by which any quantum algorithm can be decomposed, a set of logic gates, commonly denoted as {R, XX}, is native to a quantum computing system of trapped ions described herein. Here, the R gate corresponds to manipulation of individual qubit states of trapped ions, and the XX gate (also referred to as an “entangling gate”) corresponds to manipulation of the entanglement of two trapped ions.
To perform an XX-gate operation between i-th and j-th qubits, pulses that satisfy the condition X(i,j)(τ)=θ(i,j) (0<θ(i,j)≤π/8) (i.e., the entangling interaction X(i,j)(τ) has a desired value θ(i,j), referred to as condition for a non-zero entanglement interaction) are constructed and applied to the i-th and the j-th qubits. The transformations of the combined state of the i-th and the j-th qubits described above corresponds to the XX-gate operation with maximal entanglement when θ(i,j)=π/8. Amplitudes Ω(i)(τ) and Ω(j)(τ) of the pulses to be applied to the i-th and the j-th qubits are control parameters that can be adjusted to ensure a non-zero tunable entanglement of the i-th and the j-th qubits to perform a desired XX gate operation on i-th and j-th qubits.
Quantum computation can be performed in a quantum computing system, such as the ion trap quantum computing system 100, using a set of quantum gate operations including single-qubit gate operations (R gates) and two-qubit gate operations, such as XX-gate operations (XX gates). Although the methods for applying such basic building blocks of quantum computation have been established, there are control errors, which result from mis-calibration of control parameters in hardware in the quantum computing system. These control errors are mainly due to the lack of knowledge about how the ions, and thus qubits, in the quantum computing system will behave during the quantum gate operations. Thus, calibration, the task of learning the control parameters in the quantum computing system and adjusting the control parameters to correct the control errors, is needed to provide scalable and reliable quantum computation results.
The calibration process typically requires repeated measurements of qubits to collect statistics over a sizable parameter space of the control parameters of the quantum computing system. Thus, the calibration process can be an expensive and time-consuming task. If, for example, all gate operations are calibrated, a sequence of calibration steps or processes increases quadratically as the number of qubits in the quantum computing system, and consequently the quality of calibration process may degrade. Therefore, a sequence of calibration steps or processes needs to be optimized within an acceptable error in quantum computation.
In the embodiments described herein, methods for optimizing resource for calibrating quantum gate operations to execute a batch of quantum circuits (i.e., a series of quantum gate operations) on a quantum computing system. In a quantum computing system, such as the ion trap quantum computing system 100, single-qubit gate operations (R gates) can be performed with high accurary with minimal calibration effort, thus only two-qubit gate operations, such as XX-gate operations (XX gates) are calibrated with significant effort.
A quantum processor, such as the group 106 of trapped ions in the ion trap quantum computing system 100, is specified by a fully-connected system graph Gs=(Vs, Es, ∈), in which vertices i ∈Vs represent physical qubits i (i.e., trapped ions) of the quantum processor. Each edge (i,j) ∈Es that connects two vertices i,j ∈Vs for physical qubits i and j represents a two-qubit gate between the physical qubits i and j. Each edge (i,j) ∈Es has an associated infidelity ϵ(i,j) for the two-qubit gate between the physical qubits i and j. The associated infidelity ϵ(i,j) is symmetric with respect to interchaging the physical qubits i and j (i.e., ϵ(i,j)=ϵ(j,i)).
Calibration of two-qubit gates in the ion trap quantum computing system 100 includes selecting a subset S of all edges (i,j) ∈Es and tuning control parameters, associated with hardware in the ion trap quantum computing system 100, to calibrate the edges (i,j) in the subset S. In general, an associated infidelity ϵ(i,j) of an edge (i,j) inside the subset S that has been calibrated is lower than the associated infidelity ϵ(i,j) of an edge (i,j) outside the subset S that has not been calibrated. Calibration runs on the subset S (thus also referred to as a “calibration set”), and thus calibration is optimized if the subset S has the smallest size within an acceptable error.
Quantum computation in the ion trap quantum computing system 100 is performed by executaion of a batch of quantum circuits c. A quantum circuit c ∈is specified by a circuit graph Gc=(Vc, Ec, w), in which vertices k ∈Vc represent logical qubits k. Each edge e=(k,l) ∈Ec that connects two vertices k,l ∈Vc for logical qubits k and l represents a two-qubit gate between the two logical qubits k and l. It is assumed that the number of logical qubits |Vc| is less than or equal to the number of physical qubits |Vs| in the quantum processor 106. Each edge e=(k,l) ∈Ec for logical qubits k and l has an associated weight w(k,l) denoting the number of occurances of the two-qubit gate between the logical qubits k and l in the quantum circuit c ∈. Each logical qubit k is mapped to a physical qubit i and the mapping between the logical qubits and the physical qubits is described below. Each quantum circuit c ∈is mapped to a set of single-qubit gates and two-qubit gates on the physical qubits i, which can be performed on a quantum processor, such as the group of trapped ions in the ion trap quantum computing system 100, by applying appropriate laser pulses to the physical qubits i by a system controller, such as the system controller 104.
Given a quantum circuit c ∈specified by a circuit graph Gc=(Vc,Ec,w) and a quantum processor specified by a system graph Gs=(Vs, Es, ϵ), the logical qubits k are mapped to physical qubits i such that infidelity ε(Gc, Gs) of the quantum circuit c ∈is mimimized. In some embodiments, this mapping relationship between the physical qubits i and logical qubits k is by a bijective map π: Vc→Vs (i.e., π(Gc)=Gs). By this map π, an edge e=(k, l) ∈Ec in the circuit graph Gc is mapped to an edge π(e)=(π(k),n π(l)) ∈Es in the system graph Gs (i.e., π(Ec)=Es). The mapping π is computed such that the infidelity ε(Gc, Gs) of the quantum circuit c ∈excecuted on the system graph Gs is mimimized:
The average infidelity
where || is the number of the quantum circuits c in the batch . In the embodiments described herein, a certain number Γ (referred to as a calibration budget) of two-qubit gates between physical qubits i and j is selected to be calibrated, where |S|≤Γ. That is, a subset S, including |S| two-qubit gates is selected to be calibrated. The subset S is selected such that the average infidelity
where ϵS is an associated infidelity with the two-qubit gates in the subset S that are calibrated.
Computing exactly the subset S that provides the minimized average infidelity
First, it is assumed, for simplicity, all two-qubit gates for edge e ∈ES have an equal associated infidelity ϵ− before calibration and a reduced associated infidelity ϵ+ after calibration, where ϵ+<ϵ−). This assumption is referred to as a binary gate fidelity model hereinafter. Then Equation (1) can be simplified as
Thus, computing the mapping Tr reduces to maximizing the first sum in Equation (4). For a predetermined calibration budget Γ, the first sum in Equation (4) can be maximazied to
Next, maximum common edge subgraph (MCEs) is introduced, since the calibration set S to be computed is to have a maximal overlap with a batch of quantum circuits c in a typical scenario where the circuit graphs G, presumably have more edges e than the calibration budget Γ. The MCEs between two non-weighted graphs (i.e., weight w of edges e is either 0 or 1) consists of a maximum set of common edges as defined below.
Definition A.1 (Maximum Common Edge Subgraph) Maximum common edge subgraph identifies the isomorphic subgraph with the largest number of edges of a set of graphs ∩(G1, G2, . . . , Gn).
For a sequence of graphs {G1, G2, . . . GN}, the maximum common edge subgraph (MCEs) determined by sequentially calculating the pairwise MCEs, i.e., (((G1∩G2) ∩G3) . . . ∩GN), is not the same as the MCEs of the graph sequence as defined in Definition A.1. The brute force method of finding MCEs of n graphs requires maximizing over permutations of vertex-mapping for all graphs. This scales exponentially in the number of graphs n. Therefore, in the embodiments described herein, a MCEs of n graphs is computed by composing pairwise MCEs operations, reducing the complexity to be linear in the number of graphs n instead. Note, however, that the process of pairwise MCEs determination is not associative as shown in
For weighted graphs, in which edges each have a different weight, such as the circuit graph Gc=(Vc,Ec, w), in which edge e ∈Ec has an associated weight w(e), heaviest cumulative subgraph (HCs) is considered to accomodate weight of the edges. Heaviest cumulative subgraph (HCs) is defined as below.
Definition A.2 (Heaviest Cumulative Subgraph) Heaviest cumulative subgraph is a common subgraph of multiple graphs, ∧(G1, G2, . . . , Gn), with a maximum total weight of edges found as:
where {tilde over (e)}i=πi−1(e).
The definition of heaviest cumulative subgraph (HCs) is closely related to the calibration set S. For example, between two graphs G, a complete graph with two vertices, and H, a complete graph with three vertices and edges each having a different weight, the optimal calibration set S for the calibration budget Γ=1 is the HCs between graphs G and H. That is, the mapping of G to H is determined such that the cumulative edge weights is maximized.
In a non-trivial example, however, the definition of heaviest cumulative subgraph (HCs) is insufficient to compute the heaviest cumulative subgraph. Thus, Most Compact Cumulative Supergraph (MCCS) is considered here. To minimize the average infidelity
Definition A.3 (Most Compact Cumulative Supergraph) Most compact cumulative supergraph with respect to calibration budget Γ is the supergraph of a set of graphs, ∨Γ(G1, G2, . . . , Gn), with the largest sum of weights on Γ edges. It can be found by maximizing the total weight of Γ heaviest edges as
where the primed sum is for the first Γ largest elements.
In some embodiments, circuit graphs Gc=(Vc, Ec, w) have less number of edges e ∈Ec than the calibration budget Γ. In this case, the supergraph having the smallest size that include all circuit graphs Gc can be considered. The supergraph has the number of edges smaller or equal to the calibration budget Γ, all edges in the supergraph can be calibrated without considering the edge weights. This supergraph is referred to as minimum common edge supergraph (mCES) and defined as below.
Definition A.4 (Minimum Common Edge Supergraph) Minimum common supergraph identifies the smallest graph that contains all graphs from a set, ∪(G1, G2, . . . , Gn).
As described above, calibration resource can be minimized by finding most compact cumulative supergraph (MCCS) of a set of circuit graphs Gc for a given calibration budget Γ. In the embodiments described herein, two heuristic methods for finding MCCS, a method 800 for computing MCCS by the approximate MCCS algorithm, and a method 900 for computing MCCS by the genetic algorithm known in the art.
B.1 Approximate MCCS Algorithm
B.1.1 General Outline of the Algorithm
In block 802, by the classical computer 102, a batch C of quantum circuits c ∈to be calibrated is received.
In block 804, by the classical computer 102, a set of circuit graphs Gc=(Vc, Ec, w) is computed based on the received batch of quantum circuits c ϵ. In forming the set of circuit graphs Gc, graph isomorphism is taken into account. That is, the set contains circuit graphs Gc that are not isomorphic to one another. In the case of weighted graphs, a modified definition of graph isomorphism is used, where two weighted graphs G=(V1, E1, w1) and H=(V2, E2, w2) are isomorphic if there is a bijective mapping π between the sets of vertices of the two graphs, π: V1→V2, such that the mapping preserves weighted adjacency, i.e., w1(e)=w2(π(e)) ∀e ∈E1. Edges e ∈Ec and associated weights w(e) are saved separately in a dictionary in a non-volatile memory of the classical computer 102.
In block 806, by the classical computer 102, the number of edges e ∈Ec is computed. If every number of edges e ∈Ec for all quantum circuits c ∈is equal to or less than a pre-determined calibration budget Γ, the method 800 proceeds to block 808. If at least one of the number of edges e ∈Ec is more than the pre-determined calibration budget Γ, the method 800 proceeds to block 814.
In block 808, by the classical computer 102, the minimum common edge supergraph (mCES) of the set of circuit graphs Gc=(Vc, Ec, w) is computed.
In block 810, by the classical computer 102, the number of edges in the minimum common edge supergraph (mCES) of the circuit graphs Gc=(Vc, Ec, w) is computed. If the number of edges in the mCES is equal to or less than the pre-determined calibration budget Γ, all edges in the mCES can be calibrated regardless of the associated weights of the edges. Then, the method 800 proceeds to block 812. If the number of edges in the mCES is more than the pre-determined calibration budget Γ, the method 800 proceeds to iterations to compute MCCS M starting in block 814.
In block 812, by the classical computer 102, the computed minimum common edge supergraph (mCES) is output as a computation result.
In block 814, by the classical computer 102, an intial iteration of the approximate and iterative computation of MCCS, M is performed. In block 814, a graph M is initialized to a null graph (i.e., including no circuit graphs Gc), and an ordered list L of the circuit graphs Gc is created. The ordered list L is created by ordering the circuit graphs in the order of the number of their edges, from largest to smallest.
In block 816, by the classical computer 102, mapping Tr that maps the set of circuit graphs Gc to the system graph Gs is computed. First, the mapping π for the first circuit graph Gc (referred to simply as G) in the ordered list L is computed. The mapping π is computed such that an overlap between the circuit graph G and graph M. The computing of the mapping π is described below in more details.
In block 818, by the classical computer 102, the graph G is mapped by the mapping π, and the mapped graph π(G) is merged with the graph M, as described by M=(VM, EM, wM)M=(VM∪Vπ(G), EM∪Eπ(G), wM+wπ(G)).
In block 820, the method 800 returns to block 816 for a subsequent circuit graph Gc in the ordered list L. If all circuit graphs Gc in the ordered list L have been considered, the method 800 proceeds to block 822. The resulting graph M is a cumulative supergraph of all circuit graphs Gc in the ordered list L. Graph M is an approximate MCCS of all circuit graphs Gc.
In block 822, among edges in the cumulative supergraph M, Γ heaviest edges are selected and the remaining edges are removed. This final graph, denoted as MΓ, is an approximate solution that contains the calibration set S as its edges. Once the solution MΓ is identified, a round of optimal mapping for each input circuit to MΓ is made to maximize the overlap between Mr and each input circuit. This step is performed since the mappings used previously in constructing graph M is suboptimal for the maximal overlap problem with MΓ. The method described herein uses the mappings identified at this step as the final mappings for each of the circuig graphs Gc.
In block 824, by the classical computer 102, the computed graph MΓ is output as a computational result.
It should be noted that arranging the circuit graphs Gc as described above may likely lead to an exact solution for the MCCS solution when using the sequential merging approach laid out above.
B.1.2 Algorithms For The Optimal Mapping
In block 806, the mapping Tr is computed such that an overlap between the circuit graph G and a graph M. This may be considered as an extension of the maximum common edge subgraph (MCEs) problem to weighted graphs. The algorithm of finding the most optimal mapping is referred to as a backtracking algorithm, which is similar to the depth-first search (DFS) algorithm known in the art, except the bactracking algorithm does not involve all the possible branches but backtracks earlier based on a predictor function that checks whether the started mapping is worth completing based on the optimization goals. As a basis for the backtracking algorithm, the SplitP algorithm known in the art is used with a modified predictor function. Instead of maximizing the number of common edges of graphs, the cumulative weight on the common subgraph is maximized to achieve a heaviest cumulative subgraph (HCs). An additional criterion is used when there are multiple potential maps. In this scenario, the map is chosen such that incurs the least subgraph transformation cost between π(G) and M incurred. This criterion is helpful to minimize the number of heaviest edges in the final cumulative supergraph M.
Definition B.1 (Subgraph Transformation Cost) Subgraph transformation cost S(G, H) between two weighted graphs G and H is the transformation cost (see below) on the graph formed by the set of their common edges
Definition B.2 (Transformation Cost) Transformation cost T(G, H) between two weighted graphs G and H includes the sum of weights for added/removed edges and change in weight for the common edges.
where wG(e)=0 if e∉G. In general the cost function fc(wG(e),wH(e)) can be an arbitrary distance function on wG(e) and wH(e). In some embodiments, the minimum transformation cost is used since, when applied to a non-weighted case, it reduces the mapping problem to the maximum common edge subgraph (MCEs) problem (minπT(π(G), H)=|G|+|H|−2|G ∩H|), where |G| denotes the number of edges of G.
Specifically, the mapping algorithm that identifies an optimal mapping of vertices of G to M repeatedly calls a search function. The search function looks for a heaviest cumulative subgraph (HCs) between the G and M with a pre-specified number of edges. If found, the function also returns the vertex maps from G to M, used to induce the HCs. By iteratively reducing the aforementioned pre-specified number of edges, starting from the number of edges of the smaller of the two input graphs G and M, the largest possible HCs between G and M can be detemined.
The implementation of the search function is technically involved. Briefly, given the two input graphs G and M and the pre-specified number of edges, the function builds up a mapping using a depth-first search, starting with the empty mapping, and pairing an edge heuristically chosen from G with an appropriate edge from M at each level of the search tree. The function backtracks if a search in one branch has a little chance to beat the best results found so far. The function also backtracks if the calculated bound is less than the pre-specified number of edges. The bound here is calculated as the number of edges that were mapped already plus the maximal number of edges that could be mapped based on their adjacency with respect to the mapped ones.
B.1.3 Beam Search
While the backtrack algorithm used herein can be considered to be a more advanced version of the depth-first search (DFS) algorithm, it still scales poorly with the size of the graphs. To make the approach more scalable, a threshold can set on the predicted improvement while exploring a branch, when compared to the best found so far. Especially, the stronger condition requires the projected cumulative weight of the potential subgraph to exceed the best found, plus the added threshold. Otherwise the potential map is dismissed from further consideration. Multiple branches can be furether explored, while capping the number of potential maps or walkers on the search tree to n, i.e., keeping only n most promising ones.
For a large number of qubits, circuit graphs in the batch may have small heaviest cumulative subgraph (HCs), which would lead to a quick explosion in the size of the merged graph M. This results in a rapid increase in the computational resource required for the optimal mapping search described in the previous section. Thus, the size of M may be limited by keeping the number of edges of M to be below kf. This can be achieved by choosing to keep kΓ heaviest edges, while discarding the rest of the edges, should a determined M at any stage has more than kΓ edges, where k >1.
B.2 Genetic Algorithm
In the method 900 for computing most compact cumulative supergraph (MCCS) that minimizes the infidelity ε(Gc, Gs) shown in Equation (2), the negative of the infidelity ε(Gc, Gs) shown in Equation (2) is consided as in the fitness function in the genetic algorithm. In some embodiments, to calculate this fitness of a candidate graph G for the a system graph Gs, the optimal vertex map for each circuit graph Gc to the candidate graph G is found. It should be noted computing the fintess function is already a challenging task because it requires computation of an optimal mapping from a circuit graph to a system graph. To compute the mapping, backtrack heaviest cumulative subgraph (HCs) and maximum common edge subgraph (mCES) algorithms described above are used. Therefore, the performance of the genetic algorithm is closely tied to the performance of computation of the mapping.
In block 902, by the classical computer 102, a batch C of quantum circuits c ϵto be calibrated is received.
In block 904, by the classical computer 102, a set of circuit graphs Gc=(Vc, Ec, w) is computed based on the received batch of quantum circuits c ϵ.
In block 906, by the classical computer 102, a fitness function which is a negative of the infidelity ε(Gc, Gs) shown in Equation (2) is computed.
In block 908, some of the candidate graphs G are mutated (i.e., some of the candidate graphs G are randomly replaced with some of the circuit graphs Gc that are not in the candidate graphs G). Mutating a graph G=(V, E), where the number of edges e ∈E is equal to the calibration budget Γ, with a mutation rate pm includes pm1E1 new edges from all possible edges in candidate graphs G, and sampling randomly (1−pm)*|E| edges from edges e ∈E in the original graph G.
In block 910, pairs of two candidate graphs G are crossed over. Crossing over two graphs (i.e., parents) G1=(V, E1), G2=(V, E2), two more graphs G3=(V, E3) and G4=(V, E4) are generated where the edges E3 and E4 are produced by sampling from E1 ∪ E2 with the constraint |E3|=|E4|=Γ. If the fitness function of the candidate graph G is less than a pre-determined threshold value, the method 900 returns to block 906. If the fitness function of the candidate graph G exceeds the pre-determined threshold value, the method 900 proceeds to block 912. In another embodiment, a pre-determined number nG of crossovers can be considered, returning to block 906 nG times, where the method 900 proceeds to block 912 after nG iterations.
In block 912, the computed best-fit candidate graph G that contains the calibration set S as its edges and output as a computation result.
In the following, example simulation results for optimized calibration of quantum gates for a given calibration budget F are shown. In the examples disclosed herein, quantum circuits are executed on a quantum processor 106 that includes eleven trapped ions in the ion trap quantum computing system 100. Quantum circuits are executed on 10 to 20 physical qubits.
To demonstrate the quality of methods described herein, example simulation results are compared against the following primitive calibration techniques. A first primitive mapping technique (referred to as a “random approach”) is a completely unoptimized, trivial approach that is to calibrate F random gates, then execute the circuits without any mapping betweem logical qubits and physical qubits. A second primitive mapping technique (referred to as a “naive approach”) is a slightly optimized, but still the naive approach that is to count the number of gates in each circuit and calibrate F most frequently used ones, without any mapping between logical qubits and physical qubits. As described above, in block 822 of the MCCS-based method 800, a round of (re)mapping is used from circuit graphs Gc to the system graphs Gs. Use of this (re)mapping on top of the random or naive approaches are referred to as the respective, and asterisked methods. It should be noted that these asterisked methods rely on the maximum common edge subgraph (MCEs) or heaviest cumulative subgraph (HCs) mapping functions as described herein.
Average fidelities for all methods (using the MCCS algorithm, the genetic algorithm, and the primitive techniques) are estimated assuming that Γ calibrated gates have infidelity ϵ+=1%, while the rest has infidelities ϵ−=10%.
The scalability of the methods described herein has been shown in the examples using artificially generated batches of circuits for different system sizes, each batch consisting of five line-shaped graphs, five star-shaped graphs, five random trees and N randomly selected small-diameter regular graphs, where N is the number of qubits. This particular composition was motivated by the line, star and tree shapes appearing frequently in quantum programs run on a quantum computing system such as the ion trap quantum computing system 100. Small diameter, regular graphs of the form (k,d,n), where k is degree of the graph, d is the diameter of the graph, and n is the number of vertices, were selected as they are tailor made to leverage the all-to-all qubit connectivity available in a quantum computing system such as the ion trap quantum computing system 100. In the examples shown in, the MCCS solutions are computed for batches generated for six different system sizes, ranging from N=10 . . . 20 qubits, and the calibration budget Γ=N, 2N, 3N are considered. The number of calls to the search function, as a measure of the execution time, is shown in
In the embodiments described herein, methods for minimizing calibration resource for a batch of quantum circuits are provided. It has been shown for both non-weighted and weighted graphs, optimizing mapping between logical qubits and physical qubits which are described by the graphs can have a significant impact on the fidelity. In both cases, the methods described herein to compute the mapping provide increase in the average algorithm fidelity from about 70% for unmapped executions, to over 90%. Calibrating the gate-sets using the backtracking algorithm gives a consistently better performance over the fidelity range of interest with high fidelity for both weighted and non-weighted graphs than the naive approach of calibrating the most frequently used gates. In both cases, the genetic algorithm performs well for a large calibration budget Γ>15. It should be noted that, aided by the remapping algorithm described herein, even a random calibration set can give a performance close to the one obtained using the backtracking algorithm or the genetic algorithm. It should also be noted that a random sampling method takes more than orders of magnitude as much time as the backtracking algorithm to reach a target fidelity.
In using the genetic algorithm to find the optimal calibration sequence, the genetic algorithm has been found to outperform the MCCS algorithm in terms of the average fidelity for a large target budget F. However, it should be noted that the genetic algorithm, which rely on stochastic evolution of an ensemble of candidate solution, tend to consume significant time and computational resource. Other neral-network based methods, such as deep learning, may be used to shoren the time. A more efficient fusion with other search methods, such as backtrack or nested candidate approches, may further be used to reduce the computational resource requirement.
The methods described herein may provide benefits in quantum circuit compiling and executing quantum algorithms that may accelerate various numerical optimization problems. Furthremore, the methods described herein may allow a smaller-sized quantum computer to optimize the calibration routine for a larger quantum computer.
It should be noted that the particular example embodiments described above are just some possible examples of application of calibration resource optimization to a quantum computing system according to the present disclosure and do not limit the possible configurations, specifications, or the like of quantum computing systems according to the present disclosure. For example, a quantum processor within a quantum computing system is not limited to a group of trapped ions with all-to-all connectivity described above. For example, a quantum processor may be architectures with a more restrictive connectivity, such as superconducting qubits and modularized topologies, where several strongly-connected modules communicate with a few channels. The graph theoretic technique provided herein can be modified to reduce the routing and shuttling time in such systems with limited connectivity.
While the foregoing is directed to specific embodiments, other and further embodiments may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
This application claims the benefit of the U.S. Provisional Patent Application Ser. No. 63/132,954, filed on Dec. 31, 2020, which is incorporated by reference herein.
This invention was made with Government support under 70NANB16H168 awarded by the National Institute of Standards and Technology. The Government has certain rights in the invention.
Number | Date | Country | |
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63132954 | Dec 2020 | US |