Currently, a number of systems exist for testing various types of semiconductor-based devices. In general, such systems interface with the device-under-test (DUT) and perform various analyses to test the operation, functionality, etc. of the DUT. Typically, the results of these tests are logged to a results file for subsequent analysis to assess the processor design and/or the yield of the fabrication process.
Existing systems for analyzing the results file, however, are limited because of the large size of the file. The results file is typically very large because the test system performs a number of tests for each processor on each wafer in the lot.
Systems, methods, and computer programs for testing a processor design are provided. One embodiment is a method for testing a processor design. Briefly described, one such method comprises: searching a file that contains test results for a lot of wafers at two or more voltage levels; and determining an optimal operational voltage based on which of the two or more voltage levels had the least test failures.
Another embodiment is a system for testing a processor design. Briefly described, one such system comprises: a parser module for searching a file that contains test results for a lot of wafers at two or more voltage levels; a test failure calculation module for determining how many test failures occurred at the two or more voltage levels; and an optimal operational voltage module for determining which of the two or more voltage levels had the least test failures.
A further embodiment is a computer program embodied in a computer-readable medium for testing a processor design. Briefly described, one such computer program comprises: logic configured to search a file that contains test results for a lot of wafers at two or more voltage levels; and logic configured to determine an optimal operational voltage based on which of the two or more voltage levels had the least test failures.
Many aspects of the invention can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating principles in accordance with exemplary embodiments of the present invention. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.
This disclosure relates to various embodiments of systems, methods, and computer programs for testing a processor design. Several embodiments will be described below with reference to
In the exemplary embodiment, the optimal operational voltage identification system is configured to interface with a file that contains results of various tests performed on processor(s) in a collection of wafers (i.e., lot). As known in the art, the various tests may be performed for two or more voltage levels at which the processor is configured to operate (e.g., low, nominal, high, etc.). In this regard, the optimal operational voltage identification system is configured to search the file containing the results of the tests. Based on the results of the tests for each voltage level, the optimal operational voltage identification system determines which of the voltage levels had the least test failures (e.g., in terms of quantity of failures, significance of failures, etc.). In this manner, it should be appreciated that the system identifies the optimal operational voltage level according to the original test results embodied in the test file. It should be further appreciated that this type of information may be useful to processor designers and/or manufacturers to identify problem areas in either the processor design or in the processor fabrication process.
Referring to
Test criteria 118 may comprise a data file or logic that defines and/or controls the test(s) to be performed on processors 112. One of ordinary skill in the art will appreciate that any of a variety of types of tests may be performed on processors 112 and, therefore, test criteria 118 may be configured accordingly. As described in more detail below, various embodiments of test criteria 118 may be configured to perform tests at various voltage levels (e.g., low, nominal, high, etc.) at which processors 112 may operation.
As illustrated in
As known in the art, during operation of processor test system 106, the results of the tests performed on each processor 112, wafer 204, and/or the corresponding aspects of processors 112 or wafer 204 may be logged to test results file 120. Typically, due to the large number of tests being performed and the large number of processors 112, test results file 120 is relatively large. It should be appreciated that test results file 120 may be configured in a variety of ways. For example, test results file 120 may be represented in hexadecimal, binary, or other suitable data formats.
One of ordinary skill in the art will appreciate that optimal operational voltage identification system 100 may be implemented in software, hardware, firmware, or a combination thereof. Accordingly, in one embodiment, optimal operational voltage identification system 100 is implemented in software or firmware that is stored in a memory and that is executed by a suitable instruction execution system. In software embodiments, optimal operational voltage identification system 100 may be written any computer language. In one exemplary embodiment, optimal operational voltage identification system 100 comprises a PERL script.
In hardware embodiments, optimal operational voltage identification system 100 may be implemented with any or a combination of the following technologies, which are all well known in the art: a discrete logic circuit(s) having logic gates for implementing logic functions upon data signals, an application specific integrated circuit (ASIC) having appropriate combinational logic gates, a programmable gate array(s) (PGA), a field programmable gate array (FPGA), etc.
It should be appreciated that the process descriptions or blocks related to
Furthermore, optimal operational voltage identification system 100 may be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. In the context of this document, a “computer-readable medium” can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer-readable medium can be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. More specific examples (a nonexhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic) having one or more wires, a portable computer diskette (magnetic), a random access memory (RAM) (electronic), a read-only memory (ROM) (electronic), an erasable programmable read-only memory (EPROM or Flash memory) (electronic), an optical fiber (optical), and a portable compact disc read-only memory (CDROM) (optical). Note that the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.