Optimized Phase Alignment in Analog-to-Digital Conversion of Video Signals

Abstract

A digital video system (2) is disclosed, in which an analog input video signal is sampled at an optimum sample phase (Pnc), and converted to a digital datastream for display. A phase-locked loop (12) generates a plurality of sample clock phases. One of the sample clock phases (Pnc) is applied to an analog-to-digital converter (10), which digitizes the analog input video signal accordingly. Phase alignment circuitry (20) is provided that includes three sample-and-hold circuits (22b, 22c, 22a) that sample the analog input video signal, in parallel with the analog-to-digital converter (10), at times before, at, and after the current sample clock phase used by the analog-to-digital converter (10). The earlier and later sampled voltages are compared against the current sampled voltages to generate difference voltages that are each compared against a threshold voltage (Vthr). The numbers of times that the difference voltages exceed the threshold voltage over a field or frame is analyzed according to various techniques, to determine whether and in which direction to adjust the position of the current sample clock phase within the pixel period.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a timing diagram of an example of an analog video signal waveform for a pixel.

FIG. 2 is an electrical diagram, in block form, of a display system constructed according to the preferred embodiments of the invention.

FIG. 3 is an electrical diagram, in block form, of circuitry for optimizing the sample phase of the analog input video signal, constructed according to the preferred embodiments of the invention.

FIG. 4 is a timing diagram of an example of an analog video signal waveform for a pixel, illustrating the operation of the preferred embodiments of the invention.

FIG. 5 is an electrical diagram, in schematic and block form, illustrating the construction of comparison circuitry in the optimizing circuitry of FIG. 3, according to the preferred embodiments of the invention.

FIG. 6 is a flow diagram illustrating the operation of a method of optimizing the sample phase of an analog input video signal, according to a first preferred embodiment of the invention.

FIG. 7 is a flow diagram illustrating the operation of a method of optimizing the sample phase of an analog input video signal, as a variation to the first preferred embodiment of the invention.

FIG. 8 is a flow diagram illustrating the operation of a method of optimizing the sample phase of an analog input video signal, according to a second preferred embodiment of the invention.

FIG. 9 is an electrical diagram, in block form, of circuitry for measuring the activity of a region of an image to be displayed, as used in connection with the preferred embodiments of the invention.

FIGS. 10 a through 10c are timing diagrams illustrating the effects of sample frequency error relative to the pixel rate of an analog input video signal.

FIG. 11 illustrates the operation of an aspect of the preferred embodiments of the invention in which sample frequency error is measured.

FIG. 12 is a flow diagram illustrating the operation of measuring sample frequency error in connection with the preferred embodiments of the invention.

Claims

1. A method of determining a sample phase location within periods of an input signal, comprising the steps of: sampling the input signal at a current sample clock phase within a period of the input signal to obtain a current sample value;sampling the input signal at a first sample clock phase prior in time to the current sample clock phase within the period of the input signal to obtain a first sample value;sampling the input signal at a second sample clock phase later in time to the current sample clock phase within the period of the input signal to obtain a second sample value;determining first and second difference voltages corresponding to the difference between the first sample value and the current sample value, and to the difference between the second sample value and the current sample value, respectively;counting a first number corresponding to the number of times the first difference voltage exceeds a threshold voltage over a selected number of repetitions of the sampling and determining steps;counting a second number corresponding to the number of times the second difference voltage exceeds the threshold voltage over the selected number of repetitions of the sampling and determining steps; andadjusting the position of the current sample clock phase within the period of the input signal responsive to the first and second numbers.

2. The method of claim 1, further comprising: generating a plurality of clock phases at a frequency corresponding to the frequency of the input signal;selecting the current clock phase from the plurality of clock phases; andselecting the first and second sample clock phases from the plurality of clock phases;wherein the adjusting step comprises:selecting another one of the plurality of clock phases as the current sample clock phase.

3. The method of claim 2, wherein the adjusting step comprises: selecting an earlier one of the plurality of clock phases responsive to the second number exceeding a limit value and the first number not exceeding the limit value; andselecting a later one of the plurality of clock phases responsive to the first number exceeding a limit value and the second number not exceeding the limit value.

4. The method of claim 1, wherein the input signal corresponds to an analog input video signal.

5. The method of claim 4, further comprising: converting the current sample value to a digital value.

6. The method of claim 4, further comprising: estimating a sample frequency corresponding to a pixel rate of the analog input video signal.

7. The method of claim 6, wherein the adjusting step comprises: selecting an earlier one of the plurality of clock phases responsive to the second number exceeding a limit value and the first number not exceeding the limit value; andselecting a later one of the plurality of clock phases responsive to the first number exceeding a limit value and the second number not exceeding the limit value;and further comprising: responsive to both the first and second numbers exceeding the limit value, increasing the threshold voltage; andthen repeating the sampling, determining, counting, and adjusting steps.

8. The method of claim 6, wherein the adjusting step comprises: selecting an earlier one of the plurality of clock phases responsive to the second number exceeding a limit value and the first number not exceeding the limit value; andselecting a later one of the plurality of clock phases responsive to the first number exceeding a limit value and the second number not exceeding the limit value;and further comprising: responsive to both the first and second numbers exceeding the limit value, increasing the time between the first sample phase and the current sample phase, and between the second sample phase and the current sample phase; andthen repeating the sampling, determining, counting, and adjusting steps.

9. The method of claim 6, wherein the sampling steps are repeated for a number of pixel periods corresponding to a video frame; and further comprising: defining a frame window within a selected horizontal portion of the video frame;performing the counting steps for a selected number of repetitions of the sampling and determining steps corresponding to the frame window;storing the first and second numbers in memory;advancing the frame window to another selected horizontal portion of the video frame in a first direction;repeating the performing and storing steps;then adjusting the sample frequency responsive to either the first or second numbers increasing in value for advanced positions of the frame window in the first direction.

10. The method of claim 6, further comprising: responsive to neither of the first and second numbers exceeding the limit value, decreasing the threshold voltage; andthen repeating the sampling, determining, counting, and adjusting steps.

11. The method of claim 1, further comprising: after the counting steps, storing the first and second numbers in memory in association with the current sample clock phase;advancing the current sample clock phase and the first and second sample clock phases, to a different position in the period of the input signal;then repeating the sampling, determining, counting, and storing steps at the different position;repeating the advancing and repeating steps for a plurality of positions of the current sample clock phase; andanalyzing the first and second numbers for each of the plurality of positions of the current sample clock phase to identify a position at which the first and second numbers are below a limit;wherein the adjusting step adjusts the current sample clock phase to the identified position from the analyzing step.

12. The method of claim 11, further comprising: responsive to the analyzing step not identifying a position at which the first and second numbers are below the limit, increasing the threshold voltage, and then repeating the sampling, determining, counting, and storing steps over each of the plurality of positions of the current sample clock phase.

13. The method of claim 11, further comprising: responsive to the analyzing step identifying a plurality of positions at which the first and second numbers are below the limit, increasing the time between the current sample clock phase and the first sample clock phase, and between the current sample clock phase and the second sample clock phase, and then repeating the sampling, determining, counting, and storing steps over each of the plurality of positions of the current sample clock phase.

14. The method of claim 11, wherein the input signal corresponds to an analog input video signal; and further comprising: converting the current sample value to a digital value.

15. The method of claim 14, further comprising: responsive to a difference between the current sample value and a previous sample value exceeding a threshold value, advancing an activity counter; andresponsive to a count value stored in the activity counter exceeding a selected limit value, identifying at least a portion of a frame of the analog input video signal over which to perform the counting steps.

16. Analog-to-digital conversion circuitry having phase alignment capability, comprising: a phase-locked loop for generating a plurality of clock phases at a frequency;an analog-to-digital converter, for sampling an analog input signal at a current sample clock phase selected from one of the plurality of clock phases, and for converting the sampled analog input signal to a digital value; andphase alignment circuitry, comprising: a current sample circuit, for sampling the analog input signal at the current sample clock phase, to produce a current sample voltage;a first sample circuit, for sampling the analog input signal at a first sample clock phase that is selected from the plurality of clock phases and that occurs earlier in time than the current sample clock phase, to produce a first sample voltage;a second sample circuit, for sampling the analog input signal at a second sample clock phase that is selected from the plurality of clock phases and that occurs later in time than the current sample clock phase, to produce a second sample voltage;a first comparator for comparing a first difference voltage corresponding to a difference between the first sample voltage and the current sample voltage to a threshold voltage;a second comparator for comparing a second difference voltage corresponding to a difference between the second sample voltage and the current sample voltage to the threshold voltage;a first counter, coupled to the first comparator, for maintaining a count corresponding to a number of times that the first comparator detects the first difference voltage exceeding the threshold voltage; anda second counter, coupled to the second comparator, for maintaining a count corresponding to a number of times that the second comparator detects the second difference voltage exceeding the threshold voltage.

17. The circuitry of claim 16, wherein the first difference voltage corresponds to the absolute value of the difference between the first sample voltage and the current sample voltage, and wherein the second difference voltage corresponds to the absolute value of the difference between the second sample voltage and the current sample voltage.

18. A video display system, comprising: a digital graphics display;an analog input for receiving an analog input video signal;a phase-locked loop for generating a plurality of clock phases at a sample frequency;an analog-to-digital converter, for sampling an analog input signal at a current sample clock phase selected from one of the plurality of clock phases, and for converting the sampled analog input signal to a digital value;a graphics controller, for processing the digital values from the analog-to-digital converter;driver circuitry, coupled to the graphics controller and to the digital graphics display, for driving the digital graphics display responsive to the processed digital values from the graphics controller; andphase alignment circuitry, comprising: a current sample circuit, for sampling the analog input signal at the current sample clock phase, to produce a current sample voltage;a first sample circuit, for sampling the analog input signal at a first sample clock phase that is selected from the plurality of clock phases and that occurs earlier in time than the current sample clock phase, to produce a first sample voltage;a second sample circuit, for sampling the analog input signal at a second sample clock phase that is selected from the plurality of clock phases and that occurs later in time than the current sample clock phase, to produce a second sample voltage;a first comparator for comparing a first difference voltage corresponding to a difference between the first sample voltage and the current sample voltage to a threshold voltage;a second comparator for comparing a second difference voltage corresponding to a difference between the second sample voltage and the current sample voltage to the threshold voltage;a first counter, coupled to the first comparator, for maintaining a first count corresponding to a number of times that the first comparator detects the first difference voltage exceeding the threshold voltage; anda second counter, coupled to the second comparator, for maintaining a second count corresponding to a number of times that the second comparator detects the second difference voltage exceeding the threshold voltage; andcontrol circuitry for adjusting the selection of the one of the plurality of clock phases as the current sample clock phase responsive to the first and second counts.

19. The system of claim 18, wherein the control circuitry is comprised of a function executed by the graphics controller.

20. The system of claim 18, wherein the control circuitry is arranged to select an earlier one of the plurality of clock phases as the current sample clock phase responsive to the second number exceeding a limit value and the first number not exceeding the limit value over at least a portion of a frame of the input video signal; and wherein the control circuitry is arranged to select a later one of the plurality of clock phases as the current sample clock phase responsive to the first number exceeding a limit value and the second number not exceeding the limit value over at least a portion of a frame of the input video signal.

21. The system of claim 20, wherein the control circuitry is also arranged to increase the threshold voltage responsive to both the first and second numbers exceeding the limit value over at least a portion of a frame of the input video signal.

22. The system of claim 20, wherein the control circuitry is also arranged to increase the time between the first sample clock phase and the current sample clock phase, and to increase the time between the second sample clock phase and the current sample clock phase, responsive to neither of the first and second numbers exceeding the limit value over at least a portion of a frame of the input video signal.

23. The system of claim 20, wherein each of the first and second counters advances its count when enabled by an enable signal; wherein the control circuitry is also for issuing the enable signal to the first and second counters at times corresponding to a selected frame window within a selected horizontal portion of a video frame communicated by the analog input video signal;wherein the control circuitry comprises a memory;wherein the control circuitry is also arranged to store values of the first and second numbers in the memory in association with a selected frame window position;and wherein the control circuitry is also arranged to adjusting the sample frequency responsive to either the first or second numbers increasing in value for frame window positions advancing in a selected direction across the video frame.

24. The system of claim 20, wherein the control circuitry comprises a memory; wherein the control circuitry is arranged to store, in memory, the first and second numbers in association with each of a plurality of current sample clock phases;and wherein the control circuitry is also arranged to analyze the stored first and second numbers to identify at least one of the plurality of current sample clock phases at which the first and second numbers are below a limit.

25. The system of claim 20, wherein the phase alignment circuitry further comprises: activity measurement circuitry, for generating an indication of pixel activity of a sequence of digital values corresponding to the analog input signal;wherein each of the first and second counters advances its count when enabled by an enable signal;wherein the control circuitry is also for issuing the enable signal to the first and second counters at times corresponding to portions of a video frame communicated by the analog input video signal at which a selected level of pixel activity is indicated by the activity measurement circuitry.