Patent Application
20150200328
The present application relates to an optoelectronic semiconductor body and an optoelectronic semiconductor chip.
In radiation-emitting components such as light-emitting diodes, leakage currents can constitute a significant loss mechanism that limits the efficiency of the components. For InGaAlP-based light-emitting diodes it has been found that this loss mechanism occurs to an increased extent toward short wavelengths and moreover intensifies considerably as the operating temperature increases.
One object is to obtain an improved efficiency of the radiation emission.
This object is achieved by means of an optoelectronic semiconductor body comprising the features of patent claim 1 and by means of a semiconductor chip comprising such a semiconductor body. The dependent further claims relate to configurations and developments.
In accordance with one embodiment, an optoelectronic semiconductor body comprises a semiconductor layer sequence having an active region provided for generating electromagnetic radiation, a first barrier region and a second barrier region. The active region is arranged between the first barrier region and the second barrier region. Expediently, the first barrier region and the second barrier region differ from one another with regard to the conduction type. By way of example, the first barrier region can be embodied as p-conducting and the second barrier region as n-conducting, or vice versa. At least one charge carrier barrier layer is arranged in the first barrier region, said at least one charge carrier barrier layer being tensile-strained.
It has emerged that leakage currents during the operation of the optoelectronic semiconductor body can be efficiently reduced by means of a tensile-strained charge carrier barrier layer. The efficiency of the optoelectronic semiconductor body is thereby increased.
In the case of a tensile-strained layer, a lattice constant of the layer along a main extension plane of the layer is greater than the intrinsic lattice constant of the material of the layer. Semiconductor layers whose lattice constant is less than their intrinsic lattice constant are analogously designated as compressively strained.
In one preferred configuration, a relative lattice mismatch of the charge carrier barrier layer is between 0.2% and 1% inclusive, particularly preferably between 0.3% and 0.7% inclusive. The relative lattice mismatch is the ratio of the difference between the lattice constant g of the layer and the intrinsic lattice constant g0 with respect to the intrinsic lattice constant, that is to say (g−g0)/g0.
It has emerged that such a relative lattice mismatch is particularly suitable for configuring a charge carrier barrier layer such that the latter efficiently reduces leakage currents and at the same time can have a high crystal quality, in particular free of strain-reducing relaxations.
The charge carrier barrier layer can be embodied in particular as an electron barrier in a p-conducting first barrier region. Alternatively or supplementary, however, the charge carrier barrier can also be embodied as a hole barrier in an n-conducting first barrier region or second barrier region.
In one preferred configuration, the active region is based on the compound semiconductor material system AlxInyGa1-x-yP where 0≦x≦1, 0≦y≦1 and x+y≦1. This material system, which is also designated as phosphide semiconductor material hereinafter, is particularly suitable for generating radiation in the yellow to red spectral range.
However, the active region can be based on a different semiconductor material, in particular a different III-V compound semiconductor material. By way of example, nitride semiconductor material (AlxInyGa1-x-yN) is suitable for generating radiation in the ultraviolet through the blue into the green spectral range and arsenide compound semiconductor material (AlxInyGa1-x-yAs) is suitable for the red to infrared spectral range. 0≦x≦1, 0≦y≦1 and x+y≦1 in each case hold true here.
In one preferred configuration here the charge carrier barrier layer has a higher aluminum content than the material adjoining on at least one side of the charge carrier barrier layer, particularly preferably than the material adjoining on both sides of the charge carrier barrier layer.
It is furthermore preferred for the material adjoining the charge carrier barrier layer to be lattice-matched or substantially lattice-matched relative to gallium arsenide. In this connection, substantially lattice-matched is understood to mean that the relative lattice mismatch is at most 0.15% in terms of absolute value.
In a further configuration, the charge carrier barrier layer has an aluminum content x of between 0.52 and 0.7 inclusive. In the case of phosphide semiconductor material which is deposited onto gallium arsenide, the charge carrier barrier layer is therefore tensile-strained relative to gallium arsenide.
In a further configuration, the charge carrier barrier layer has a thickness of between 1 nm and 25 nm inclusive, particularly preferably between 3 nm and 20 nm inclusive.
By virtue of a charge carrier barrier layer in this thickness, in particular in conjunction with the relative lattice mismatch indicated above, a charge carrier barrier may be formed which efficiently reduces leakage currents and the thickness of which is below the critical layer thickness. The critical layer thickness for a semiconductor layer is a material-specific upper limit for the growth of a strained semiconductor layer. A reduction of the strain that decreases the crystal quality in the form of dislocations is typical above the critical layer thickness. The smaller the relative lattice mismatch, the larger, typically, the critical layer thickness.
In one development, the first barrier region has at least one further charge carrier barrier layer. The charge carrier barrier layer and the further charge carrier barrier layer constitute a barrier for the same charge type, for example for electrons in a p-conducting first barrier region.
The charge carrier barrier layer and the further charge carrier barrier layer are preferably at a distance from one another of between 3 nm and 200 nm inclusive. In particular, the first charge carrier barrier layer and the further charge carrier barrier layer can be at a distance from one another of between 50 nm and 200 nm inclusive.
Expediently, the further charge carrier barrier layer is likewise tensile-strained. In particular, the further charge carrier barrier layer can have at least one or more of the features mentioned above in connection with the charge carrier barrier layer.
The semiconductor material between the charge carrier barrier layer and the further charge carrier barrier layer can be embodied as unstrained. Alternatively, an intermediate layer can be arranged between the charge carrier barrier layer and the further charge carrier barrier layer, said intermediate layer being compressively strained.
The strain of the charge carrier barrier layer can be at least partly compensated for by means of the compressively strained intermediate layer. Such strain compensation makes it possible to prevent the total strain of the semiconductor material from leading to the formation of dislocations.
In one preferred development, the further charge carrier barrier layer is further away from the active region than the charge carrier barrier layer and has a higher aluminum content than the charge carrier barrier layer. The further charge carrier barrier layer is therefore more greatly tensile-strained than the charge carrier barrier layer and constitutes a greater charge carrier barrier than the charge carrier barrier layer. The risk of a relaxation and of a reduced barrier effect resulting therefrom is increased on account of the greater strain. In the case of such a relaxation, however, a barrier effect for the charge carriers is still ensured by the upstream charge carrier barrier layer having a lower aluminum content.
The active region preferably has a quantum structure having at least one quantum layer. In this case, the term quantum structure does not imply any restriction with regard to the dimensionality of the quantization and encompasses in particular quantum wells, quantum rods and quantum dots.
The charge carrier barrier layer is preferably at a distance of between 10 nm and 900 nm inclusive, particularly preferably between 100 nm and 600 nm inclusive, from that quantum layer of the quantum structure which is situated closest to the charge carrier barrier layer.
A particularly efficient barrier effect can be obtained by means of a charge carrier barrier layer at this distance from the quantum layer.
An optoelectronic semiconductor chip preferably comprises a semiconductor body having the features described above and a carrier, wherein the semiconductor body is arranged on the carrier.
The carrier can be for example a growth substrate for the semiconductor layer sequence of the semiconductor body. By way of example, gallium arsenide is suitable as a growth substrate for phosphodic compound semiconductor material.
Alternatively, the carrier can differ from a growth substrate for the semiconductor layer sequence. In this case, the carrier is connected to the semiconductor body by means of a cohesive connection. In the case of a cohesive connection, the, preferably prefabricated, connection partners are held together by means of atomic and/or molecular forces. A cohesive connection can be obtained for example by means of a connection means, for instance an adhesive or a solder. In general, the separation of the connection is accompanied by destruction of the connection means, and/or of at least one of the connection partners.
The carrier serves in particular for mechanically stabilizing the semiconductor layer sequence. The growth substrate is no longer required for this purpose and can therefore be removed.
A semiconductor chip in which the growth substrate for the semiconductor layer sequence is removed is also designated as a thin-film semiconductor chip. Preferably, an in particular metallic mirror layer is arranged between the semiconductor body and the carrier. Radiation generated in the active region and emitted in the direction of the carrier can be reflected at the mirror layer and emerge on a radiation exit surface of the semiconductor chip situated opposite the carrier.
Further features, configurations and expediencies will become apparent from the following description of the exemplary embodiments in association with the figures.
In the figures:
Elements that are identical, of identical type or act identically are provided with the same reference signs in the figures.
The figures and the size relationships of the elements illustrated in the figures among one another should not be regarded as to scale. Rather, individual elements and in particular layer thicknesses may be illustrated with an exaggerated size in order to enable better illustration and/or in order to afford a better understanding.
A first exemplary embodiment for a semiconductor chip comprising a semiconductor body 1 is illustrated schematically in
The semiconductor layer sequence 2 extends in a vertical direction, that is to say in a direction running perpendicularly to a main extension plane of the semiconductor layers of the semiconductor layer sequence 2, between a first main surface 23 and a second main surface 24 and forms the semiconductor body 1.
The semiconductor layer sequence 2 comprises an active region 20 provided for generating radiation. The active region 20 has a quantum structure having a plurality of quantum layers 201, wherein a quantum barrier 202 is in each case arranged between adjacent quantum layers. Only three quantum layers are shown for the sake of simplified illustration. However, the number of quantum layers can be varied within wide limits. In particular, the active region can have between one and 200 quantum layers inclusive.
The semiconductor layer sequence 2 furthermore has a first barrier region 21 and a second barrier region 22. The active region 20 is arranged between the first barrier region and the second barrier region. In the description below, the first barrier region 21 is embodied as p-conducting and the second barrier region 22 as n-conducting. The first barrier region 21 extends between the active region and the first main surface 23, and the second barrier region 22 extends between the active region and the second main surface 24. However, the semiconductor body 1 can also be embodied in an inverted fashion with regard to the conduction type.
The semiconductor chip 10 furthermore comprises a first contact 61 and a second contact 62. By applying an electrical voltage between the contacts charge carriers may be injected into the active region 20 from opposite sides and recombine there with emission of radiation.
The first barrier region 21 has a charge carrier barrier layer 3. The charge carrier barrier layer 3 is embodied in a tensile-strained fashion. In contrast thereto, the material of the first barrier region that adjoins both sides of the charge carrier barrier layer is embodied in an unstrained fashion. In the case of a gallium arsenide growth substrate, for example phosphide compound semiconductor material is suitable, in particular phosphide compound semiconductor material having an aluminum content of between 48% and 51% and correspondingly an indium content of between 52% and 49%.
In particular, the material adjoining the charge carrier barrier layer 3 can be free of gallium or substantially free of gallium, that is to say with a gallium content of at most 5%.
In the exemplary embodiment shown, the first barrier region 21 has a main region 212 and a contact region 211. The contact region 211 forms the first main surface 23. The charge carrier barrier layer 3 is arranged within the main region 212.
The contact region 211 can be based on arsenide compound semiconductor material. The contact region 211 can also be embodied in a multilayered fashion. In particular, the material directly adjoining the main surface 23 can consist of p-doped gallium arsenide.
An ohmic contact with respect to the first contact 61 can thus be obtained in a simplified manner. In a departure from this, however, such a contact region composed of arsenide compound semiconductor material can also be dispensed with.
The vertical extent of the main region 212 is preferably at least double the magnitude of the vertical extent of the contact region 211.
The relative lattice mismatch of the tensile-strained charge carrier barrier layer 3 is preferably between 0.2% and 1% inclusive, in particular between 0.3% and 0.7% inclusive.
A thickness of the charge carrier barrier layer is preferably between 1 nm and 5 nm inclusive, particularly preferably between 3 nm and 20 nm inclusive.
Preferably, the relative lattice mismatch of the charge carrier barrier layer 3 and the thickness of the charge carrier barrier layer are coordinated with one another in such a way that the charge carrier barrier layer does not exceed the critical layer thickness. The smaller the relative lattice mismatch, therefore, the larger the thickness of the charge carrier barrier layer can be, and vice versa.
A distance d between that quantum layer 201 of the active region 20 which is situated closest to the barrier region 21 and the charge carrier barrier layer is preferably between 10 nm and 900 nm inclusive, particularly preferably between 100 nm and 600 nm inclusive.
The semiconductor material of the first barrier region 21 need not necessarily be deposited in a continuously p-conductively doped manner. By way of example, a partial region, in particular the charge carrier barrier layer 3, can be grown in a nominally undoped manner. A doping of the layer deposited in a nominally undoped manner can be established by means of a back-diffusion of the subsequently deposited semiconductor material.
The p-type doping of the first barrier region 21 can be effected by means of magnesium and/or carbon, for example. In particular, the main region 212 can be doped with magnesium and the contact region 211 can be doped with carbon. Tellurium or silicon, for example, is suitable for an n-type doping.
The charge carrier barrier layer 3 preferably has a higher aluminum content than the material adjoining both sides of the charge carrier barrier layer. In particular, the aluminum content can be between 0.52 and 0.7 inclusive. The higher the aluminum content, the larger, typically, the band gap EG of the material.
In a p-conducting first barrier region 21, the charge carrier barrier layer 3 is embodied as an electron barrier. The proportion of electrons which traverses the active region without radiative recombination in the active region 20 and passes to the first contact 61 can be reduced by means of the electron barrier.
It has been found that an efficient electron barrier can be formed by the tensile-strained charge carrier barrier layer described, even if the tensile strain can slightly counteract the barrier effect.
In addition, it has been found that the positioning of the charge carrier barrier layer 3 in a region which is heavily doped, for instance with a doping of at least 1*1018 cm−3, constitutes a comparatively great barrier for minority charge carriers, that is to say for electrons in a p-conducting region, and at the same time a comparatively small barrier for the majority charge carriers, that is to say holes in the p-conducting region. The band discontinuities at the transition between the charge carrier barrier layer and the adjoining material of the first barrier region 21 therefore occur predominantly in the conduction band.
Furthermore, a comparatively heavy doping in that material of the first barrier region 21 which adjoins the charge carrier barrier layer 3 has the effect that the depletion zone in the region of the band discontinuities is small and the Fermi level is near the band edge.
In a departure from the configuration described, the first barrier region 21 can also be embodied as n-conducting. In this case, the charge carrier barrier layer 3 formed in the first barrier region is a hole barrier. Moreover, in addition to the charge carrier barrier layer in the first barrier region 21, a charge carrier barrier layer can also be formed in the second barrier region 22. In this case, the semiconductor body can comprise both an electron barrier and a hole barrier.
The second exemplary embodiment illustrated in
The semiconductor layer sequence 2 is cohesively fixed to the carrier 5 by means of a connection layer 71, for example by means of a solder layer or an electrically conductive adhesive layer.
A mirror layer 72 is arranged on the first main surface 23 of the semiconductor layer sequence 2 and reflects radiation generated in the active region 20 and emitted in the direction of the carrier 5. The emission from the semiconductor chip takes place predominantly, preferably to the extent of at least 70%, through the second main surface 24 of the semiconductor body 1 facing away from the carrier 5.
Furthermore, in contrast to the first exemplary embodiment, the second barrier region 22 has a contact region 221 adjoining the second main surface 24. The contact region 221 can be based on arsenide compound semiconductor material. However, such a contact region can also be dispensed with.
A schematic profile of the band gap EG along the deposition direction z, that is to say along the vertical direction, is illustrated schematically in
The charge carrier barrier layer 3 has a higher aluminum content and thus a higher band gap than the semiconductor material adjoining the charge carrier barrier layer 3 on both sides.
The semiconductor material of the first barrier region 21 adjoining the charge carrier barrier layer 3 on both sides has a greater aluminum content and thus a larger band gap than the quantum barriers 202 of the active region 20.
The first barrier region 21 therefore itself already constitutes a charge carrier barrier, wherein the barrier effect is increased more extensively by the tensile-strained charge carrier barrier layer 3. On account of the configuration of the charge carrier barrier layer 3 below the critical layer thickness, an improvement in the barrier effect for electrons in the p-conducting first barrier region 21 may be obtained without a reduction in the material quality on account of relaxations.
In the case of the exemplary embodiment illustrated in
The charge carrier barrier layer 3 and the further charge carrier barrier layers 35 in the exemplary embodiment are embodied in each case such that they are of identical type, in particular with regard to the aluminum content and their strain. The barrier effect is improved by the increase in the number of charge carrier barrier layers.
In contrast to the configuration of identical type, the charge carrier barrier layers in the exemplary embodiment illustrated in
The higher the aluminum content, the greater the extent to which the charge carrier barrier layer 3 and the further charge carrier barrier layers 35 can in each case fulfill the function of an electron barrier. However, there is also an increase in the risk of the critical layer thickness being exceeded during production and the strain thereby being reduced in the form of relaxations. Preferably, the charge carrier barrier layer 3 with the lowest aluminum content is embodied such that the critical layer thickness of the charge carrier barrier layer is not exceeded even in the case of process fluctuations. If the charge carrier barrier layers 35 having a higher aluminum content that are further away from the active region relax, then a charge carrier barrier effect is ensured at least by the charge carrier barrier layer 3 situated closest to the active region.
In the case of the exemplary embodiment illustrated in
Measurement results of the radiation power P for different semiconductor chips are shown in
The measurements were carried out at a temperature of 100° C. Since the radiation power P is also dependent on the emission wavelength A, wavelength-dependent straight lines as upper limits 82 and 92, respectively, lower limits 83 and 93, respectively, and mean values 81 and 91, respectively, are plotted in each case for the measurement values. If the mean values are compared, represented by arrow 95, then an increase in the radiation power of 23% results. In a comparison of the upper limits, represented by arrow 96, the increase is 14%. Even in a comparison of the mean value of the four semiconductor bodies having a charge carrier barrier layer with the upper limit 92 for semiconductor bodies without a charge carrier barrier layer, an increase of 10% still results. The measurements therefore prove that the efficiency of the semiconductor chips can be significantly increased by means of the charge carrier barrier layer 3.
The curves 97 and 98 in each case show the current density for holes and electrons, respectively. The value of the curve 98 for z=0 divided by the current density of 200 A/cm2 taken as a basis in each case represents that proportion of the electrons which traverses the active region without recombination and thus makes no contribution to the radiation emission. If these values are compared, then said proportion can be reduced from 23.3% to 20.9% at a temperature of 100° C. and from 3.8% to 3.2% at a temperature of 20° C. by means of the charge carrier barrier layer 3. Assuming a direct proportionality of the increase in efficiency with respect to the reduced leakage current, therefore, an increase of approximately 3% would result at 100° C. For the actually expected increase in the emitted radiation power, however, the so-called photon recycling factor should also be taken into account. This factor indicates how often a photon is absorbed and re-emitted before it leaves the semiconductor material. Given a decrease in the losses from 23.3% to 20.9% and a typical photon recycling factor of approximately 5, therefore, on the basis of the simulations, an increase in the efficiency by a factor of ((1−0.209)/1−0.233))̂5=1.17, that is to say by approximately 17%, should be expected.
The simulations therefore prove in accord with the measurements illustrated in
This patent application claims the priority of German patent application 10 2012 107 795.9, the disclosure content of which is hereby incorporated by reference.
The invention is not restricted by the description on the basis of the exemplary embodiments. Rather, the invention encompasses any novel feature and also any combination of features, which in particular includes any combination of features in the patent claims, even if this feature or this combination itself is not explicitly specified in the patent claims or exemplary embodiments.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2012 107 795.9 | Aug 2012 | DE | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2013/066656 | 8/8/2013 | WO | 00 |
