Patent Application
20240170611
An optoelectronic semiconductor chip is disclosed. In addition, a manufacturing method for such semiconductor chips and a semiconductor component having such semiconductor chips are disclosed.
Embodiments provide an optoelectronic semiconductor chip that can be assembled efficiently and precisely.
According to at least one embodiment, the semiconductor chip comprises a semiconductor layer sequence having a bottom side. The bottom side may be planar and flat. In particular, the bottom side faces an emission side on which at least a predominant part of the radiation generated in the semiconductor layer sequence is emitted. The bottom side is, for example, a main side, i.e. a largest side, of the semiconductor layer sequence.
The semiconductor layer sequence comprises at least one active zone that is configured to generate or detect radiation during operation of the semiconductor chip. If the semiconductor chip is configured to generate radiation, the generated radiation is preferably incoherent and is in particular visible light such as blue light, green light and/or red light. The semiconductor layer sequence is preferably based on a III-V compound semiconductor material. The semiconductor material is, for example, a nitride compound semiconductor material such as AlnIn1-n-mGamN or a phosphide compound semiconductor material such as AlnIn1-n-mGamP or also an arsenide compound semiconductor material such as AlnIn1-n-mGamAs or such as AlnGamIn1-n-mAskP1-k, where in each case 0≤n≤1, 0≤m≤1 and n+m≤1 as well as 0≤k<1. For example, 0<n≤0.8, 0.4≤m<1 and n+m≤0.95 as well as 0<k≤0.5 applies to at least one layer or to all layers of the semiconductor layer sequence. In this context, the semiconductor layer sequence may comprise dopants as well as additional components. For the sake of simplicity, however, only the essential constituents of the crystal lattice of the semiconductor layer sequence, i.e. Al, As, Ga, In, N or P, are given, even if these may be partially replaced and/or supplemented by small amounts of additional substances.
According to at least one embodiment, the semiconductor chip comprises a bottom coating on the bottom side. The bottom coating may be formed by a single material or is composed of multiple components or layers. Preferably, the bottom coating is at least partially electrically conductive. In the latter case, the bottom coating comprises, for example, a transparent conductive oxide, TCO for short, such as ITO or zinc oxide, or at least one metal such as Al, Ag and/or Au.
According to at least one embodiment, the semiconductor chip comprises an electrode layer on an underside of the bottom coating facing away from the semiconductor layer sequence. The electrode layer may be located directly at the underside. The electrode layer is preferably a metallic layer and comprises, for example, Al, Ag and/or Au. For example for corrosion protection or contact improvement, the electrode layer may be provided with at least one coating, for example TiW or TiWN.
According to at least one embodiment, the bottom coating has a thickness gradient. That is, a thickness of the bottom coating varies across the bottom coating.
According to at least one embodiment, the bottom coating comprises one or more ridge lines. The at least one ridge line is located in particular at a point where the bottom coating is thickest. For example, the ridge line is shaped similar to a ridge.
According to at least one embodiment, the electrode layer extends across the at least one ridge line. That is, the at least one ridge line is not a tear-off line for the electrode layer, but the electrode layer preferably enables an electrically conductive connection across the at least one ridge line.
According to at least one embodiment, an electrical contact side of the electrode layer facing away from the semiconductor layer sequence follows the bottom coating true to shape. In other words, the contact side may have the same shape as the bottom coating when viewed in cross-section. This applies, for example, with a tolerance of at most 50% or 25% or 10% of a maximum thickness of the bottom coating.
According to at least one embodiment, the at least one ridge line defines an electrical and mechanical contact plane of the contact side parallel to the bottom side. In other words, the ridge line followed by the electrode layer true to shape ensures that the semiconductor chip can be mounted in a controlled orientation. In this case, the bottom side is aligned parallel to a carrier mounting side of a carrier on which the semiconductor chip is mounted.
In at least one embodiment, the optoelectronic semiconductor chip comprises a semiconductor layer sequence having a bottom side. A bottom coating is provided on the bottom side. An electrode layer is disposed on a bottom side of the bottom coating facing away from the semiconductor layer sequence. The bottom coating has a thickness gradient and at least one ridge line where the bottom coating is thickest. The electrode layer extends over the at least one ridge line so that a contact side of the electrode layer facing away from the semiconductor layer sequence conforms the bottom coating to the shape. The at least one ridge line defines an electrical and mechanical contact plane of the contact side parallel to the bottom side.
In particular, a contact pad on the underside with, for example, a ring-shaped deposition structure is described in order to be able to establish an improved mechanical and electrical connection. This applies in particular to LED chips, sensor chips and so-called μLED chips, which have small lateral dimensions. The principle described here can be applied to all types of connection of a semiconductor chip to a carrier, but in particular to bonded semiconductor chips.
Thus, the semiconductor chip can be both an emitter and a sensor. In particular, the semiconductor chip is intended for installation in a display. The semiconductor chip can be used especially in applications that benefit from a defined emission direction of the semiconductor chip.
Precisely aligning the emission directions of semiconductor chips, such as LEDs, sensors or μLEDs, relative to each other can be comparatively challenging, especially in cases of directly viewed displays where as identical as possible emission patterns are required for all LEDs or μLEDs, both within an RGB pixel and between pixels. In addition, the special contact pad structure described here is particularly advantageous when an adhesive, such as an electrically non-conductive adhesive, is used to mechanically attach the semiconductor chips in order to achieve high performance of the overall system.
Semiconductor chips with flat contact pads, on the other hand, tend to tilt slightly during bonding. This can be prevented with the contact structure described here, for example by providing the semiconductor chips with a contact edge that is annular in plan view so that an electrical contact can be better defined through a non-conductive, dielectric adhesive. In particular, the contact edge can penetrate the adhesive more easily. At the same time, such a ring structure will allow the orientation of the semiconductor chip to be precisely defined, since a contact surface can be precisely adjusted. In other words, tilting of the semiconductor chip during an assembly can be avoided.
According to at least one embodiment, the bottom coating has exactly one ridge line. Preferably, the ridge line is a closed line. Alternatively, the ridge line may be an open line, i.e., the ridge line may have two ends, or in the case of a branched ridge line, more than two ends.
According to at least one embodiment, the ridge line or at least one of the ridge lines is a circle, seen in plan view on the bottom side. As an alternative to a circle, the relevant ridge line may also be designed as an ellipse, as a rectangle, as a polygon or as an are triangle, as seen in plan view. If there are several ridge lines, these can be arranged concentrically around each other.
According to at least one embodiment, the bottom coating comprises one or more base bodies. The at least one base body is preferably located directly on the bottom side.
According to at least one embodiment, the bottom coating comprises one or more step layers. The at least one step layer is located in particular directly on a valley side of the base body facing away from the semiconductor layer sequence.
According to at least one embodiment, the valley side is free of the step layer in a central region. This means that the step layer then only partially covers the base body, in particular only at an outer edge.
According to at least one embodiment, the step layer runs around the central region, in particular in a closed line. In this case, the at least one ridge line is preferably defined by the at least one step layer. In particular, the ridge line is where the step line ends towards the central region and/or slopes or tapers off towards the central region with a step.
According to at least one embodiment, the ridge line or at least one of the ridge lines bounds the central region. It is possible that the entire central region of the bottom coating is closer to the bottom side of the semiconductor layer sequence than the ridge line. That is, the valley side may be located within a crater-like structure framed by the ridge line. Thus, the corresponding at least one ridge line overhangs the central region in the direction away from the semiconductor layer sequence.
According to at least one embodiment, the central region constitutes at least 5% or at least 10% or at least 20% or at least 40% or at least 70% of the bottom side, as seen in plan view of the bottom side. That is, the ridge line may frame or encircle a comparatively large area. It is additionally possible for the central region to comprise at most 90% or at most 75% of the bottom side.
According to at least one embodiment, the at least one base body is made of an electrically conductive material. In particular, the base body is metallic and made, for example, of Ag or Al or Au. Alternatively, the base body is made of a TCO. Preferably, the base body is made of exactly one material, but can alternatively be composed of several materials.
According to at least one embodiment, the at least one step layer is made of a dielectric material, for example at least one oxide such as aluminum oxide and/or silicon oxide. Alternatively, the step layer is made of an electrically conductive material, such as a TCO, or is a metallic layer. The stepped layer may be composed of a plurality of sub-layers. For example, the step layer is then a mirror layer and/or a barrier layer against moisture penetration.
According to at least one embodiment, the at least one step layer has a constant, uniform layer thickness in areas where it is present. This means that the stepped layer is applied to the base body without any specific variation in thickness.
According to at least one embodiment, the layer thickness of the stepped layer is at least 20 nm or at least 50 nm. Alternatively or additionally, the layer thickness is at most 3 μm or at most 0.5 μm or at most 0.2 μm or at most 100 nm. This means that the stepped layer can be relatively thin.
According to at least one embodiment, the bottom coating has a maximum thickness of at least 50 nm or of at least 100 nm. Alternatively or additionally, the maximum thickness is at most 3 μm or at most 1.0 μm or at most 0.7 μm or at most 0.5 μm or at most 0.3 μm.
According to at least one embodiment, the base body is convexly curved throughout. This means that, viewed in cross-section, the base body can be shaped like a converging lens. A maximum thickness of the base body is preferably present in the central region.
According to at least one embodiment, the bottom coating, as seen in cross-section, is curved only in an edge region and is otherwise oriented parallel or approximately parallel to the bottom side. The stepped layer may be limited to the edge region.
According to at least one embodiment, the electrode layer completely covers the bottom coating. Alternatively, the electrode layer covers the bottom coating only partially.
According to at least one embodiment, the semiconductor chip is a PLED. This means, for example, that an edge length of the bottom side as seen in plan view is at least 1 μm or at least 3 μm and/or at most 0.2 mm or at most 100 μm or at most 30 μm or at most 20 μm or at most 10 μm. For example, the edge length is between 1 μm and 10 μm inclusive.
According to at least one embodiment, the bottom coating has a monotonically or strictly monotonically decreasing thickness, starting from the at least one ridge line, in the direction towards the edges of the bottom side. In this regard, it is possible that the bottom coating extends to the edges or close to the edges, as seen in plan view of the bottom side. Likewise, the bottom coating may extend to at least one side surface of the semiconductor layer sequence, i.e., it may extend beyond the edges. Close to the edges means, for example, that a distance from the bottom coating to the associated edge is at most 2 m or at most 1 μm or at most 500 nm or at most 100 nm.
According to at least one embodiment, the electrode layer has a constant thickness, in particular in the central region. A local thickness is in particular at a specific point of the electrode layer a smallest distance between two opposite main sides of the electrode layer, preferably one of these main sides being the contact side. It is also possible for the thickness of the electrode layer to decrease towards its edges, so that the electrode layer can taper out thinly and have a decreasing thickness at the edges.
According to at least one embodiment, the semiconductor chips are provided for electrical contact on both sides. That is, a first electrical contact is made via the bottom side and a second electrical contact is made via the emission side. Alternatively, the semiconductor chips may be flip chips.
In the case of flip chips, the contact plane can be laid through the highest points of the two electrical contacts on the bottom side, i.e. both ridge lines define planes for themselves which need not coincide with the jointly defined plane, for example because the optoelectronic semiconductor chip is bent through and the two electrical contacts are tilted relative to each other. Thus, the optoelectronic semiconductor chip would then rest, for example, on the ridge lines of the outer sides of the corresponding electrical contacts.
In addition, a method of manufacturing a semiconductor chip as described in connection with one or more of the above embodiments is disclosed. Features of the semiconductor chip are therefore also disclosed for the method and vice versa.
In at least one embodiment, the method is used to produce at least one optoelectronic semiconductor chip and comprises the following steps, in particular in the order indicated:
In addition, a semiconductor component having at least one semiconductor chip as described in connection with one or more of the above embodiments is disclosed. Features of the semiconductor chip are therefore also disclosed for the semiconductor component, and vice versa.
In at least one embodiment, the semiconductor component comprises one or more optoelectronic semiconductor chips as well as a carrier and a connecting means, which is for example a solder or an adhesive. The optoelectronic semiconductor chips are attached to a preferably planar carrier mounting side of the carrier by the connecting means, with the bottom sides preferably oriented parallel to the carrier mounting side. The electrode layers are pressed in the region of the ridge lines by the connecting means up to the carrier mounting side, so that orientations of the bottom sides are defined by the ridge lines. For example, the bottom sides are all oriented parallel to each other due to the ridge lines of the individual semiconductor chips.
According to at least one embodiment, the semiconductor component is a red-green-blue display. For example, the semiconductor component then comprises at least 103 or at least 105 or at least 107 of the optoelectronic semiconductor chips.
In the following, an optoelectronic semiconductor chip described herein, a method described herein and a semiconductor component described herein are explained in more detail with reference to the drawing on the basis of embodiment examples. Identical reference signs indicate identical elements in the individual figures. However, no references to scale are shown, rather individual elements may be shown exaggeratedly large for better understanding.
The drawings show:
It is also illustrated in
The shape of the base body 31 can be adjusted, for example, with a mask layer 5 which overhangs towards the base body 31 and which has a greater thickness than the base body 31. The curved shape of the valley side 34 results, in particular, from shading effects on the mask layer 5 when a material of the base body 31 is applied. The base body 31 is, for example, made of Ag, Al or Au which is vapor-deposited.
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The starting layer 32′ is preferably thin, for example with a thickness of at least 20 nm and/or of at most 100 nm. For example, the starting layer 32′ is made of a dielectric material such as silicon dioxide and/or aluminum oxide.
In
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Removal of the step layer 32 from the central region C results in a thickest portion of the bottom coating 3 along an edge of the exposed central region C. This thickest portion forms a ridge line 33. The step layer 32 ends toward the central region 33 at or near the ridge line 33.
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The electrode layer 4 overmolds the bottom coating 2 true to shape, so that a contact side 40 of the electrode layer 4 facing away from the semiconductor layer sequence 2 has the same shape or basic shape as the bottom side 30 of the bottom coating 3. In this case, the electrode layer 4 is preferably a continuous, uninterrupted layer that overmolds the ridge line 33 without tearing.
At least within the ridge line 33, the electrode layer 4 has a constant layer thickness, for example, whereby the electrode layer 4 can extend with constant thickness over the ridge line 33. It is possible that the electrode layer 4 becomes thinner towards outer edges of the bottom coating 3 and thus tapers off.
The resulting optoelectronic semiconductor chip 1 is in particular a PLED. That is, the semiconductor chip 1 is arranged to generate light and the bottom side 20 has an edge length or an average edge length between 1 μm and 30 μm inclusive. A thickness of the semiconductor layer sequence 2 perpendicular to the bottom side 20 is, for example, between 0.5 μm and 5 μm inclusive, in particular between 1.0 μm and 2.5 μm inclusive.
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The contact plane P is oriented parallel to the bottom side 20, for example with a tolerance of at most 1.5° or of at most 0.5° or of at most 0.2°. The angle A is preferably more than 0°, for example at least 0.3° or at least 1.2° and/or at most 6° or at most 4°. This preferably also applies to all other embodiments.
Optionally, the step layer 32 has a front side 35 which runs at an angle to the valley side 35, for example with an angle B of at least 45° and/or of at most 80°, in particular between 50° and 70° inclusive. That is, the front side 35 is then not oriented perpendicular to the valley side 34. This facilitates over-shaping of the ridge line 33 and the front side 35 by the electrode layer 4, since excessive slopes of the underside 30 can be avoided.
In all other respects, the comments on
In
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The bottom coating 3 can also be circular in shape. A difference in the diameters of the central region C and the edge region E is, for example, at least 5% or at least 10% and/or at most 20% or at most 10% of the shortest edge length L.
Furthermore, it is illustrated in
In all other respects, the comments on
In the example shown in
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In the embodiment example of
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The top views of
In the embodiment shown in
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Optionally, the electrode layer 4 is flattened in the region of the ridge line 33. Such a flattened region of the contact side 40 may also be present in all other embodiments. For example, the flattened region, as seen in cross-section through a center of the bottom side 20, has a width of at least 1% or of at most 5% of the minimum edge length L.
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The semiconductor chips 1 are mounted on a common carrier 81, the carrier 81 having a planar carrier mounting side 80 for this purpose. Conductor tracks and electrical connection areas can be located on the carrier mounting side 80, not shown.
The semiconductor chips 1 are attached to the carrier mounting side 80 by means of a mechanical connecting means 82. The connecting means 82 is, for example, an electrically non-conductive adhesive such as a photoresist. The semiconductor chips 1 are mounted, for example, by pressing them onto the carrier 81 through the connecting means 82. This is facilitated by the relatively sharp edges of the contact sides 40 in the region of the ridge lines 33. In addition, defined contact surfaces are ensured by the ridge lines 33.
By shrinking the connecting means 82 during a curing process, it is additionally possible for the semiconductor chips 1 to be attracted to the carrier 81. The ridge lines 33 ensure that an alignment of the semiconductor chips 1 with defined emission directions is maintained even in the case of such shrinkage or shrinkage.
For example, red-green-blue pixels, also known as RGB pixels, are formed by the semiconductor chips 1. That is, red, green and blue emitting semiconductor chips 1 can be combined with each other. The corresponding emission color comes about, for example, directly by the respective semiconductor layer sequence 2 or by means of a phosphor, not shown.
Optionally, a filler material 83 is located between adjacent semiconductor chips 2. The filler material 83 is, for example, white to ensure high radiation efficiency or black to achieve high contrast. Further cover layers can be applied to all semiconductor chips 1 and to the optional filler material 83, not drawn, for example to protect the semiconductor chips 1 mechanically, electrically and/or chemically.
The semiconductor chips 1 are, for example, chips to be contacted on both sides. That is, the emission sides 25 can be electrically connected by means of electrical connection means 85, such as bonding wires. Alternatively, the semiconductor chips 1 may be designed as flip chips. The same applies to all other embodiments.
The components shown in the figures preferably follow one another in the sequence indicated, in particular directly one after the other, unless otherwise described. Components not touching each other in the figures are preferably spaced apart. Insofar as lines are drawn parallel to one another, the associated surfaces are preferably likewise aligned parallel to one another. Furthermore, the relative positions of the drawn components to each other are correctly reproduced in the figures, unless otherwise specified.
The invention described herein is not limited by the description based on the embodiments. Rather, the invention encompasses any new feature as well as any combination of features, which in particular includes any combination of features in the patent claims, even if this feature or combination itself is not explicitly stated in the patent claims or embodiments.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2021 202 920.5 | Mar 2021 | DE | national |
This patent application is a national phase filing under section 371 of PCT/EP2022/056324, filed Mar. 11, 2022, which claims the priority of German patent application 10 2021 202 920.5, filed Mar. 25, 2021, each of which is incorporated herein by reference in its entirety.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2022/056324 | 3/11/2022 | WO |
