Patent Grant
6946801
1. Field of the Invention
The present invention relates to an organic EL element drive circuit and an organic EL display device using the same and, in particular, the present invention relates to an improvement of an organic EL element drive circuit for a column line (one of anode side drive lines of an organic EL panel), with which, when the organic EL element drive circuit is formed as an IC, freedom of a wiring and a layout thereof is increased, an area of the organic EL element drive circuit can be reduced and power consumption thereof can be reduced, and an organic EL display device using the same organic EL element drive circuit.
2. Description of the Prior Art
It has been known that an organic EL display device, which realizes a high luminance display by spontaneous light emission, is suitable for a display on a small display screen and the organic EL display device has been attracting public attention as the next generation display device to be mounted on a portable telephone set, a PHS, a DVD player or a PDA (Personal Digital Assistants), etc. Known problems of the organic EL display device are that, when it is driven by voltage as in a liquid crystal display device, luminance variation thereof becomes substantial and that, since there is difference in sensitivity between R (red), G (green) and B (blue), a control of luminance of a color display becomes difficult. In view of these problems, an organic EL display device using current drive circuits has been proposed recently. For example, JPH10-112391A discloses a technique with which the luminance variation problem is solved by employing a current drive system.
An organic EL display panel of an organic EL display device for a portable telephone set, a PHS, etc., having 396 (=132×3) terminal pins for column lines and 162 terminal pins for row lines has been proposed. However, there is a tendency that the number of column lines as well as row lines is further increased.
An output stage of a current drive circuit of such organic EL display panel of either the active matrix type or the simple matrix type includes a current source drive circuit, such as an output circuit constructed with a current mirror circuit, for each of the terminal pins. A drive stage thereof includes a parallel-driven type current mirror circuit (reference circuit distribution circuit) having a plurality of output side transistors for each of the terminal pins as disclosed in JP2002-82662 (domestic priority application claiming priorities of JP2001-86967 and JP2001-396219) corresponding to U.S. patent application Ser. No. 10,102,671. In the disclosed drive stage, a plurality of mirror currents are generated correspondingly to the respective terminal pins by a reference current supplied from a reference current generator circuit to thereby drive the output circuits and by supplying them to the respective pins. Alternatively, the mirror currents supplied to the respective terminal pins are amplified by respective k-time current amplifier circuits, where k is an integer equal to or larger than 2, and the output circuits are driven with the amplified currents. The k-time amplifier circuit is disclosed in JP2002-33719, in which D/A converter circuits are provided correspondingly to the respective terminal pins and the D/A converter circuit converts display data corresponding to the column side terminal pins into analog data to generate column side drive currents simultaneously.
In this disclosed circuit construction, a peak current is generated for initially charging an organic EL element having capacitive load characteristics to drive the organic EL element. The peak current may be generated in a circuit portion preceding to the drive stage as a reference current, in a circuit portion succeeding to a D/A converter circuit as disclosed in JP2002-33719 or in a current output stage.
In
The D/A converter circuit 11 includes an N channel input side transistor TNa and an N channel input side transistor TNp mirror-connected to the N channel input side transistor TNa. The D/A converter circuit 11 further includes N channel output side transistors TNb to TNn−1, which are current-mirror connected to the input side transistors TNa and TNp.
Channel width (gate width) ratio of the transistors TNa to TNb is set to 1:9. A source of the transistor TNa is grounded through a resistor Ra and a source of the transistor TNp is grounded through a resistor Rpa and a switch circuit SWpa. For the sake of simplicity of description, a switch SWa provided between the resistor Ra and ground GND, which is shown in FIG. 1 of U.S. patent application Ser. No. 10,360,715, is not shown in FIG. 3.
The channel width (gate width) ratio of 1:9 may be obtained by parallel-connecting 9 of 10 MOS transistors having identical configurations and good pairing characteristics to the remaining one MOS transistor.
The input side transistors TNa and TNp are connected to an input terminal 11a and supplied with the current Ip from the constant current source 12 through the input terminal 11a.
When the current having the value Ip flows in the input side transistor TNa as an operating current, a peak current Ia (=Ipa) corresponding to a display data is generated at an output terminal lib of the D/A converter circuit 11. When the current Ip is branched and flows in the input side transistors TNa and TNp, an input side drive current of the current mirror circuit becomes substantially one-tenth the current Ip and a drive current Ia (=Ipa/10) corresponding to the display data is generated at the output terminal 11b of the D/A converter circuit 11.
Resistors Rb to Rn−1 are provided between sources of the output side transistors TNb to TNn−1 and drains of transistors Trb to Trn−1, respectively. With these resistors, it is possible to improve preciseness of the current pairing characteristics of the D/A converter circuit 11.
Gates of the transistors Trb to Trn−1 are connected to input terminals Do to Dn−1 to which n-bit display data are inputted. Thus, the transistors Trb to Trn−1 are supplied with the display data from the register 16. Sources of the transistors Trb to Trn−1 are grounded.
The current mirror type current output circuit 13 includes a drive level shifter circuit 13a and an output stage current mirror circuit 13b.
The drive level shifter circuit 13a functions to transmit the output of the D/A converter circuit 11 to the output stage current mirror circuit 13b and includes an N channel MOS FET TNv. A gate of the transistor TNv is connected to a bias line Vb and a source of the same transistor is connected to the output terminal 11b of the D/A converter circuit 11. A drain of the transistor TNv is connected to an input terminal 13c of the output stage current mirror circuit 13b.
Therefore, assuming that the output current of the D/A converter circuit 11 is Ia, it is possible to generate a drive current of Ia at the input terminal 13c.
The output stage current mirror circuit 13b includes a current mirror circuit composed of P channel MOS FETs TPu and TPw for correcting a gate drive voltage and P channel MOS FETs TPx and TPy, which are driven by the transistors TPu and TPw. Gate width ratio of the transistor TPx to the transistor TPy of the output stage current mirror circuit 13b is 1:N. Sources of the transistors TPx and TPy are connected to not a power source line +VDD but a power source line +Vcc which is higher than +VDD, for example, about +15V. The transistor TPy is connected to a column side terminal pin 9 and drives the terminal pin 9 by supplying drive current N Ia. An organic El element 8 is connected between the terminal pin 9 and ground GND. Incidentally, Vc in
The input side transistor TNp, the resistor Rpa and the switch circuit SWpa constitute the peak current generator circuit 14 and the switch circuit SWpa is turned OFF for a constant time period tp in an initial stage of driving without a control signal CONT from the control circuit 15 and is turned ON by the control signal CONT after the time period tp lapses.
Since the switch circuit SWpa does not receive the control signal CONT from the control circuit 15 in the initial driving stage, the current Ip flows in the input side transistor TNa. Therefore, a current, which is several times, for example, M times, the current Ip, corresponding to the display data set in the respective input terminals D0 to Dn−1, that is, M×Ip (=Ipa), is generated, so that the peak current Ia=M×Ip is generated at the output terminal 11b of the D/A converter circuit 11. The control signal CONT is generated after the peak current generating period tp and the switch circuit SWpa is turned ON. The current in the input side transistor TNa is branched to the input side transistor TNp. Therefore, a drive current, which is Ip/10, flows in the input side transistor TNa and a drive current 9×Ip/10 flows in the input side transistor TNp according to the gate width ratio 1:9 of these transistors. As a result, the input side drive current of the current mirror circuit becomes substantially 1/10 and the current Ia(=Ipa/10) is generated at the output terminal 11b of the D/A converter circuit 11.
There is a recent tendency that the number of drive pins is increasing due to request of high resolution. Correspondingly to the increase of the drive terminal pins, the number of the output stages of the current drive circuit tends to be increased. Therefore, power consumption is increased correspondingly, so that a reduction of power of the current drive circuit becomes necessary. In order to solve this problem, the current drive circuit constructed with MOS transistors, such as shown in
When the current drive circuit composed of the MOS transistors is used, various currents for operating the circuit, such as bias currents and currents required to correct the base current, etc., are necessary as in the case where a current drive circuit composed of bipolar transistors and a leak current problem occurs. These currents are increased with increase of the number of terminal pins and an influence of these currents on power consumption of the whole circuit becomes large correspondingly, resulting in an obstacle in reducing the power consumption.
Further, in the current drive circuit shown in
An object of the present invention is to provide an organic EL element drive circuit with which the freedom in designing a layout and a wiring of a current drive circuit can be increased, an area occupied thereby can be reduced and power consumption thereof can be reduced, when a plurality of the organic EL element drive circuits are fabricated as an IC.
Another object of the present invention is to provide an organic EL display device utilizing a plurality of organic EL element drive circuits with which the freedom in designing a layout and a wiring of a current drive circuit is increased, an area occupied thereby can be reduced and power consumption thereof can be reduced, when a plurality of the organic EL element drive circuits are fabricated as ICs.
In order to achieve these objects, an organic EL element drive circuit for current-driving any one of organic EL elements of an organic EL display panel by an output current supplied from a current output circuit constructed with a current-mirror circuit through a corresponding terminal pin of the panel, according to the present invention, is featured by comprising a plurality (n) of unit circuits each including a first MOS transistor of a certain channel type and a second MOS transistor of the same channel type and having a source connected to a drain of the first MOS transistor, where n is an integer equal to or larger than 3. Gates of either the first MOS transistors or the second MOS transistors of at least two of the n unit circuits are connected together to form a common gate. One of the two unit circuits constitutes an input side unit circuit of the output stage current mirror circuit, the other of the two unit circuit constitutes an output side circuit of the current mirror type output stage circuit. The common gate is connected to a current drive side terminal of the input side unit circuit through either the first MOS transistor or the second MOS transistor of another unit circuit as a drive side unit circuit.
In an embodiment of the present invention, the unit circuit is constructed by connecting a drain of a P or N channel type first MOS transistor to a source of a second MOS transistor having the same channel type and a plurality of the unit circuits are formed in an IC chip. By selectively wiring these unit circuits on the IC chip, the current mirror circuit of the output stage of the organic EL element drive circuit can be constructed.
The input side unit circuit as well as the output side unit circuit of the output stage current mirror circuit includes two MOS transistors connected in series with each other. Therefore, by turning the MOS transistors of one of the two unit circuits, which are other than the MOS transistors having the common gates, ON and turning the MOS transistors of the unit circuit, which have the common gates and connect the current drive side terminal of the input side unit circuit to the common gates, ON, a general current mirror circuit having a diode-connected input side circuit is realized.
Since, with such circuit construction, the MOS transistor of the output side unit circuit, which are the MOS transistors having no common gate, can be turned OFF in a period during which the drive current from the drive side unit circuit is not outputted, unnecessary current does not flow from the output side unit circuit to other unit circuits connected thereto. Particularly, by constructing each unit circuit with a pair of series-connected P channel type MOS transistors and by turning an upstream one of the MOS transistors, which is the MOS transistor having no common gate, ON to generate the drive current, unnecessary current does not flow in the downstream side transistor during a time in which the upstream side transistor is in OFF state. Further, since the output stage current mirror circuit is driven after at least one of the MOS transistors of the other unit circuit, which connects the common gates to the current drive side terminal of the input side unit circuit, is turned ON, there is substantially no leak current.
Therefore, in the output stage current mirror circuit constructed with the above mentioned identical unit circuits, there is substantially no current such as bias current for drive, current for correcting the base current and leak current, etc., in a period in which the terminal pin is not current-driven.
As a result, the unit circuits are fabricated as an IC, the freedom of layout and wiring is increased. Further, it is possible to realize an organic EL element drive circuit and an organic EL display device capable of reducing an area occupied by the current drive circuits and of reducing power consumption.
Therefore, the D/A converter 4 includes a transistor corresponding to an input side transistor TNa of the D/A converter 11 in
The current-mirror type current output circuit 2 corresponds to the current mirror type current output circuit 13 shown in FIG. 3 and is constructed with a drive circuit 2a and an output stage current mirror circuit 2b. The drive circuit 2a is provided as a unit circuit 5a including a P channel MOS transistor Tr1 and a P channel MOS transistor Tr2 connected in series with the transistor Tr1. The output stage current mirror circuit 2b includes an input side unit circuit 5b having a circuit construction identical to that of the unit circuit 5a and an output side unit circuit 5c.
By constituting the output stage current mirror circuit 2 with the unit circuits 5a and 5b and the output side unit circuit 5c, the reduction of power consumption and the freedom of the layout and wiring design are realized. Incidentally, back gates of the transistors Tr1 and Tr2 of the unit circuits 5a and 5b are connected to a common power source line Vcc.
Describing the drive circuit 2a first, the unit circuit 5a constituting the drive circuit 2a is constructed with the P channel MOS transistors Tr1 and Tr2 as mentioned above. That is, a drain of the transistor Tr1 is connected to a source of the transistor Tr2 and the drain of the transistor Tr2 is connected to the output terminal 4b of the D/A converter 4 through a switch circuit 6. Gates of the transistors Tr1 and Tr2 are connected to a control terminal Go supplied with a control signal So from a control circuit 15 through a control line 7a.
The input side unit circuit 5b of the output stage current mirror circuit 2b is constructed with the P channel MOS transistors Tr1 and Tr2 as mentioned above. A source of the transistor Tr1 of the input side unit circuit 5b is connected to the power source line +Vcc and a drain of the transistor Tr2 thereof is connected to the drain of the transistor Tr1 of the unit circuit 5a of the drive circuit 2a and driven by a drive current outputted from the drive circuit 2a.
A gate of the transistor Tr1 of the input side unit circuit 5b is grounded. Therefore, the transistor Tr1 of the unit circuit 5b is normally in ON state with a predetermined impedance. Although, in this embodiment, the gate of the transistor Tr1 is grounded, the gate thereof may be connected to a bias line for biasing the transistor to ON state with a predetermined ON impedance.
With using the transistor Tr1 of the unit circuit 5b, which has the predetermined ON impedance, the input side unit circuit 5b can be constructed by using a unit circuit, which is identical to the output side unit circuit 5c of the output stage current mirror circuit 2b. Therefore, the operation level thereof can be matched with that of the output side unit circuit 5c.
The output side unit circuit 5c of the output stage current mirror circuit 2b can be constructed with a plurality (p) of parallel-connected unit circuits each being identical to the input side unit circuit 5b, where p is an integer equal to or larger than 2. Sources of p transistors Tr1 of the output side unit circuit are connected to the power source line +Vcc and drains of p transistors Tr2 thereof are connected to a terminal pin 9. Gates of the p transistors Tr1 are commonly connected to a control terminal G1 to which a control signal S1 is supplied from the control circuit 15. In this case, it may be possible to form p unit circuits by connecting the drains of the parallel-connected p transistors Tr1 to the sources of the parallel-connected p transistors Tr2, respectively. The gate of the transistor Tr2 of the input side unit circuit 5b of the output stage current mirror circuit 2b and the gates of the transistors Tr2 of the output side unit circuit 5c thereof are commonly connected to a gate connecting line 7b and a capacitor C is provided between the gate connecting line 7b and the power source line +Vcc. Further, the source of the transistor Tr1 of the unit circuit 5a of the drive circuit 2a is connected to the gate connecting line 7b, so that the gate of the transistor Tr1 of the unit circuit 5a constituting the drive circuit 2a and the gates of the transistors Tr2 of the output stage current mirror circuit 2b are driven by a voltage across the capacitor C.
The source of the transistor Tr1 of the unit circuit 5a of the drive circuit 2a is connected to the gate connecting line 7b and the drain thereof is connected to the drain of the transistor Tr2 of the input side unit circuit 5b of the output stage current mirror circuit 2b. Therefore, when the transistor Tr1 of the drive circuit 2a is turned ON, the transistor Tr2 of the input side unit circuit 5b is diode-connected, so that the input side unit circuit 5b and the output side unit circuit 5c operate as a current mirror circuit.
The peak current generator circuit 3 includes a plurality (n) of parallel-connected unit circuits each including transistors Tr1 and Tr2, where n is an integer larger than p. In the peak current generator circuit 3, sources of the n transistors Tr1 are connected to the power source line +Vcc and drains of the n transistors Tr2 are connected to the terminal pin 9. Gates of the n transistors Tr1 are commonly connected to a control terminal G2 to which a control signal S2 is supplied from the control circuit 15. In this case, it may be also possible to constitute the peak current generator circuit 3 by connecting drains of the parallel-connected p transistors Tr1 to sources of parallel-connected p transistors Tr2, respectively.
A terminal G4 of the organic EL element drive circuit receives a low (L) level reset signal RS from the control circuit 15. The switch 6 is turned OFF by the L level reset signal RS supplied thereto through a control line 7c. The L level reset signal is also supplied to the control line 7a through a buffer amplifier 6a to turn the transistor Tr1 of the unit circuit 5a constituting the drive circuit 2a ON. Therefore, the capacitor C is discharged through the transistor Tr1 thus turned ON and the transistors Tr1 and Tr2 of the input side unit circuit 5b, which are in ON states, to thereby the voltage of the capacitor C is reset.
The transistor Tr1 of the unit circuit 5a of the drive circuit 2a can be turned ON by turning the switch circuit 6 OFF with the reset signal RS supplied to the terminal G4 and simultaneously setting the control line 7a to L level.
Now, an operation of the current mirror type current output circuit 2 will be described with reference to FIG. 2. It is assumed here that L levels of the control signals So to S2 and the reset signal RS are significant and it is assumed that a drive voltage for current mirror operation is temporarily stored in the capacitor C and an actual current outputting operation is performed according to a generation timing of the control signals S1 and S2.
Display data is set in the D/A converter 4, first, and then set in the register 16, shown in
In this case, the transistors Tr2 of the input side unit circuit 5b and the output side unit circuit 5c become ON by the voltage of the capacitor C. However, the control signals S1 and S2 supplied to the respective control terminals G1 and G2 are H level and the gates of the transistors Tr1 of the output side unit circuit 5c and the peak current generator circuit 3 become H level. Therefore, these transistors Tr1 are kept OFF. As a result, no current is supplied to the terminal pin 9.
Thereafter, when the control signal S1 becomes L level at a time when the control line Go becomes H level as shown in FIG. 2(c), the transistors Tr1 of the output side unit circuit 5c become ON and a current is supplied to the terminal pin 9 through the transistors Tr2 of the output side unit circuit 5c, which are ON according to the voltage of the capacitor C. When the control signal S2 becomes L level as shown in FIG. 2(d), the transistors Tr1 of the peak current generator circuit 3 become ON and a further current is supplied to the terminal pin 9 through the transistors Tr2 of the peak current generator circuit 3, which are kept in ON state by the voltage of the capacitor C.
As a result, a drive current having a peak such as shown in FIG. 2(e) is generated in the terminal pin 9 during the period in which the control signals S1 and S2 are in L level and the organic EL element 8 is current-driven thereby. In this case, ineffective current does not flow in the output side unit circuit 5c of the output stage current mirror circuit 2b so long as the transistors Tr1 thereof are in OFF states. Further, since the transistors Tr1 and Tr2 of the unit circuit 5a of the drive circuit 2a, which are turned ON by the control signal So, function to allow a drive current for charging the capacitor C to flow, substantially no drive current such as leak current flows when these transistors are OFF.
The timing of the control signal S2 with respect to the control signal S1 is not limited to the described timing. It may be any, provided that the peak current for initially charging the organic EL element 8 having the capacitive characteristics can be generated.
The reset signal RS shown in FIG. 2(f) is generated with such a timing that the voltage of the capacitor C is reset before a drive of a next column line is started.
Although the control signals So to S2 and the reset signal RS have been described as L level significant, they can be H level significant when these signals are supplied through inverters.
Although the peak current generator circuit 3 is constructed as the unit circuit 5d including the transistors Tr1 and the transistors Tr2, it is not always necessary to construct the peak current-generator circuit 3 with the unit circuit. Further, the peak current generator circuit 3 is not always provided in parallel to the output stage current mirror circuit. The D/A converter 4 may be replaced by the D/A converter 11 including the peak current generator circuit 14, which is shown in FIG. 3.
Further, although the capacitor C is provided to temporarily store the drive current of the current mirror output circuit and then the drive current is outputted to the terminal pin according to the control signal, the capacitor C may be removed to directly output the terminal pin drive current. In such case, since the output side unit circuit 5c includes the transistors Tr1 and the transistors Tr2, it is possible to output the drive current when the upstream side transistor Tr1 is turned ON. Therefore, ineffective current does not flow in the output side unit circuit 5c of the output stage current mirror circuit 2b so long as the transistors Tr1 thereof are in OFF states. In this case, the transistors Tr1 and Tr2 of the unit circuit 5a of the drive circuit 2a are turned ON simultaneously therewith. However, since the drive current is outputted at this ON timing and then the transistors Tr1 and Tr2 are turned OFF, substantially no ineffective drive current such as leak current flows.
Although the organic EL element drive circuit and the organic EL display device according to the described embodiment is constructed with the P channel MOS FETs mainly, the P channel transistors may be replaced by N channel transistors. In such case, the power source voltage should be negative and the upstream side transistors should be provided on the downstream side.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2002-120128 | Apr 2002 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 6147665 | Friedman | Nov 2000 | A |
| 6586888 | Kitahara et al. | Jul 2003 | B2 |
| Number | Date | Country |
|---|---|---|
| 10-112391 | Apr 1998 | JP |
| 2003-234655 | Aug 2003 | JP |
| Number | Date | Country | |
|---|---|---|---|
| 20030197473 A1 | Oct 2003 | US |
