Patent Application
20080001863
These and other objects of the invention will be apparent from the following detailed description of the embodiments of the present invention with reference to the accompanying drawings, in which:
Hereinafter, a flat display panel and a fabricating method thereof according to the present invention will be described with reference to the accompanying drawings.
Referring to
A plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn are crossed to be vertical to each other. A pixel that includes the organic light emitting diode OLED is formed at a crossing part thereof. An equivalent circuit in
The refresh voltage generator 120 is applied with a power voltage to generate a refresh voltage for removing a gate discharge voltage of the driving transistor D_TR1, thereby supplying it to the data driver 140. Herein, the refresh voltage generator 120 supplies a refresh voltage of 0V or a refresh voltage of negative polarity. This is because only DC voltage of positive polarity is supplied to a gate electrode of the driving transistor D_TR1, a refresh voltage of 0V or a refresh voltage of negative polarity is supplied to the driving transistor D_TR1 to remove a gate discharge voltage of the driving transistor D_TR1. On the other hand, in the present invention, the refresh voltage generator 120 generates a refresh voltage. However, its application is not limited to this. For example, the timing controller 130 may generate a refresh voltage to supply it to the data driver 140.
The timing controller 130 is inputted with a video data from a system such as a TV set or a computer monitor, etc., to supply a digital data to the data driver 140 and, at the same time control a driving of the data.
Further, the timing controller 130 generates a data driving control signal DDC, a refresh control signal RCS, a gate driving control signal GDC, and a mask signal MKS using a horizontal/vertical synchronizing signals H and V from a system in accordance with a clock signal CLK from a system. The data driving control signal DDC and the refresh control signal RCS are supplied to the data driver 140. The gate driving control signal GDC and the mask signal MKS are supplied to the gate driver 150. Herein, the data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, and a source output enable signal SOE, etc. The gate driving control signal GDC includes a gate start pulse GSP and a gate output enable signal GOE, etc. Specially, the refresh control signal RCS controls a supply timing of a refresh voltage of the data driver 140. The mask signal MKS controls a horizontal period of a scanning pulse.
The data driver 140 converts a digital data which is inputted from the timing controller 130 into an analog data voltage in response to a data driving control signal DDC which is supplied from the timing controller 130 to supply it to pixels of the display panel 110. Herein, the data driver 140 converts a digital data which is supplied via the timing controller 130 into an analog data voltage on the basis of a gamma reference voltage which is supplied from a gamma reference voltage generator (not shown) to supply it to the data lines DL1 to DLm. Herein, an analog data voltage is realized as a gray scale at the organic light emitting diode OLED of the display panel 110.
The data driver 140 supplies a data at a current frame, and then supplies a refresh voltage to pixels which are selected among the pixels of the display panel 110 for a current frame in accordance with a refresh control signal RCS from the timing controller 130.
Referring to
The gate driver 150 sequentially supplies a scanning pulse for supplying a data to the gate lines GL1 to GLn for a current frame, and then sequentially supplies a scanning pulse for refreshing to the gate lines GL5 to GLn for a current frame in response to a gate driving control signal GDC and a gate shift clock GSC which are supplied from the timing controller 130 as shown in
On the other hand, in the present invention, the gate driver 150 selects a pixel to be supplied with a data by supplying a scanning pulse for a half horizontal period and, at the same time selects a pixel to be supplied with a refresh voltage by supplying a scanning pulse for a half horizontal period in accordance with a mask signal MKS. However, a period of a scanning pulse is not limited to this. For another example, the gate driver 150 may select a pixel to be supplied with a data by supplying a scanning pulse for a two thirds horizontal period and, at the same time may select a pixel to be supplied with a refresh voltage by supplying a scanning pulse for a one third horizontal period in accordance with a mask signal MKS.
Furthermore, in the present invention, a scanning pulse for refreshing is supplied to only gate lines GL5 to GLn. However, its application is not limited to this. For another example, a scanning pulse for refreshing may be sequentially supplied to all gate lines GL1 to GLn.
As described above, the present invention supplies a data voltage, and then supplies a refresh voltage for one frame to remove a gate discharge voltage of the driving transistor. As a result, the present invention can prevent a degradation of the driving transistor and remove a residual image of a screen.
Although the present invention has been explained by the embodiments shown in the drawings described above, it should be understood to the ordinary skilled person in the art that the invention is not limited to the embodiments, but rather that various changes or modifications thereof are possible without departing from the spirit of the invention. Accordingly, the scope of the invention shall be determined only by the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| P2006-060760 | Jun 2006 | KR | national |
