Patent Application
20130127692
This application claims the benefit of Korean Patent Application No. 10-2011-0121137 filed on Nov. 18, 2011, which is incorporated by reference herein in its entirety.
1. Technical Field
This document relates to an organic light emitting diode display device capable of compensating the threshold voltage of a driving TFT.
2. Description of the Related Art
The demand for various types of display devices for displaying an image is increasing. Various flat panel displays, such as a liquid crystal display, a plasma display panel, and an organic light emitting diode (OLED) display, have been recently used. Out of the various types of flat panel displays, the OLED display has excellent characteristics including a low voltage drive, a thin profile, a wide viewing angle, and a fast response time. Especially, an active matrix type OLED display for displaying an image on a plurality of pixels, which are arranged in a matrix form, has been widely used.
A display panel of the active matrix type OLED display comprises a plurality of pixels arranged in a matrix form. Each of the pixels comprises a scan thin film transistor (TFT) for supplying a data voltage of a data line in response to a scan signal of a scan line and a driving TFT for adjusting the amount of current supplied to an organic light emitting diode in accordance with a data voltage supplied to a gate electrode. The drain-source current Ids of the driving TFT supplied to the organic light emitting diode can be represented by Equation 1:
I
ds
=k′·(Vgs−Vth)2 [Equation 1]
where k′ represents a proportionality coefficient determined by the structure and physical properties of the driving TFT, Vgs represents the gate-source voltage of the driving TFT, and Vth represents the threshold voltage of the driving TFT.
The threshold voltage Vth of the driving TFT of each of the pixels may have a different value due to a shift in the threshold voltage Vth caused by degradation of the driving TFT. In this case, the drain-source current Ids of the driving TFT depends upon the threshold voltage Vth of the driving TFT. Hence, the current Ids supplied to the organic light emitting diode differs from pixel to pixel even if the same data voltage is supplied to each of the pixels. Accordingly, there arises the problem that the luminance of light emitted from the organic light emitting diode of each of the pixels differs even if the same data voltage is supplied to each of the pixels. To solve this problem, various types of pixel structures for compensating the threshold voltage Vth of the driving TFT have been proposed.
Referring to
The present invention has been made in an effort to provide an organic light emitting diode display device capable of sensing the threshold voltage of a driving TFT even when the threshold voltage of the driving TFT is shifted to a negative voltage.
An organic light emitting diode display device according to the present invention comprises: a display panel having a data line, a scan line, and an emission line formed thereon and a plurality of pixels arranged in a matrix form, each of the pixels comprising: a driving TFT comprising a gate electrode coupled to a first node, a source electrode coupled to a second node, and a drain electrode coupled to a high-potential voltage source supplying a high-potential voltage; an organic light emitting diode comprising an anode coupled to the second node and a cathode coupled to a low-potential voltage source supplying a low-potential voltage; a first TFT that is turned on in response to a scan signal having a first logic level voltage of the first scan line to connect the first node to the data line; a second TFT that is turned in response to an emission signal having the first logic level voltage of the emission line to connect the second node to the third node; a first capacitor coupled between the first node and the third node; and a second capacitor coupled between the third node and a reference voltage source supplying a reference voltage.
The features and advantages described in this summary and the following detailed description are not intended to be limiting. Many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specification and claims.
The invention will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Like reference numerals designate like elements throughout the specification. In the following description, if it is decided that the detailed description of known function or configuration related to the invention makes the subject matter of the invention unclear, the detailed description is omitted.
A pixel of an organic light emitting diode display device according to an embodiment of the present invention can internally compensate the threshold voltage of a driving TFT and externally compensate the threshold voltage and electron mobility of the driving TFT and the threshold voltage of an organic light emitting diode. Internal compensation refers to sensing and compensating the threshold voltage of the driving TFT in real time within the pixel. External compensation refers to sensing the drain-source current of the driving TFT and the current of the organic light emitting diode, using the sensed current to compensate digital video data to be supplied to the pixel, and then supplying the compensated digital video data to the pixel. Particularly, the external compensation allows for real-time compensation of the threshold voltage and electron mobility of driving TFTs of pixels coupled to a scan line and the threshold voltage of organic light emitting diodes of the pixels, by sensing the drain-source current of the driving TFTs of the pixels coupled to the scan line or the current of the organic light emitting diodes of the pixels every frame period.
The driving TFT DT adjusts the amount of drain-source current Ids to differ according to the level of a voltage applied to a gate electrode. The gate electrode of the driving TFT DT is coupled to a first node N1, a source electrode thereof is coupled to a second node N2, and a drain electrode thereof is coupled to a high-potential voltage source supplying a high-potential voltage VDD.
An anode of the organic light emitting diode is coupled to the second node N2, a cathode thereof is coupled to a low-potential voltage source supplying a low-potential voltage VSS. The organic light emitting diode OLED emits light depending on the drain-source current Ids of the driving TFT DT.
The control circuit comprises first to third TFTs T1, T2, and T3. The first TFT T1 is turned on in response to an mth scan signal SCANm having a gate high voltage VGH supplied from an mth (m is a natural number) scan line SLm for coupling the first node N1 and an nth data line DLn to supply a data voltage Dn to node N1. A gate electrode of the first TFT T1 is coupled to the mth scan line SLm, a source electrode thereof is coupled to the first node N1, and a drain electrode thereof is coupled to the nth data line DLn.
The second TFT T2 is turned on in response to an emission signal EM having the gate high voltage VGH supplied from an emission line EML for coupling the second node N2 and the third node N3. A gate electrode of the second TFT T2 is coupled to the emission line EML, a source electrode thereof is coupled to the third node N3, and a drain electrode thereof is coupled to the second node N2.
The third TFT T3 is turned on in response to a sensing signal SEN having the gate high voltage VGH supplied from a sensing line SENL for coupling the second node N2 and an (n+1)th reference voltage line RLn+1. The (n+1)th reference voltage line RLn+1 is coupled to a reference voltage source supplying a reference voltage REF. A gate electrode of the third TFT T3 is coupled to the sensing line SENL, a source electrode thereof is coupled to the (n+1)th reference voltage line RLn+1, and a drain electrode thereof is coupled to the second node N2.
The first capacitor C1 is coupled between the first node N1 and the third node N3, and is charged to store a differential voltage between the first node N1 and the third node N3. The second capacitor C2 is coupled between the nth reference voltage line RLN and the third node N3, and is charged to store a differential voltage between the nth reference voltage line RLn and the third node N3.
The first node N1 is a contact point at which the gate electrode of the driving TFT DT, the source electrode of the first TFT T1, and one electrode of the first capacitor C1 are coupled. The second node N2 is a contact point at which the source electrode of the driving TFT DT, the drain electrode of the second TFT T2, the drain electrode of the third TFT T3, and the anode of the organic light emitting diode are coupled. The third node N3 is a contact point at which the source electrode of the second TFT T2, the other electrode of the first capacitor C1, and one electrode of the second capacitor C2 are coupled. The other electrode of the second capacitor C2 is coupled to the nth reference voltage line RLn.
Semiconductor layers of the first to third TFTs T1, T2, and T3 and the driving TFT DT have been described as being formed of an oxide semiconductor. However, the present invention is not limited thereto, but the semiconductor layers of the first to third TFTs T1, T2, and T3 and the driving TFT DT may be formed of either a-Si or Poly-Si. Also, embodiments of the present invention are described with respect to examples in which the first to third TFTs T1, T2, and T3 and the driving TFT DT are implemented as N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).
After consideration of the characteristics of the driving TFT DT and the characteristics of the organic light emitting diode OLED, the high-potential voltage source is set to supply a high-potential voltage VDD swinging among a high level VDD_H, a middle level VDD_M, and a low level VDD_L, and the low-potential voltage source is set to supply a DC low-potential voltage VSS. The reference voltage REF may be set to a predetermined DC voltage. For example, a high-potential voltage VDD_H of high level may be set to 20 V, the high-potential voltage VDD_L of low level may be set to approximately −7 V, the low-potential voltage VSS may be set to 0 V, and the reference voltage REF may be set to approximately 0 V.
An organic light emitting diode display according to the present invention further comprises a reference voltage switching circuit REF SW to externally compensate the threshold voltage Vth and electron mobility of the driving TFT DT and the threshold voltage of the organic light emitting diode OLED. The reference voltage switching circuit REF SW comprises first and second switches S1 and S2, an inverter Inv, and a current sensing circuit ADC. It should be noted that, although the first and second switches S1 and S2 have been described as being implemented as N-type MOSFETs, the present invention is not limited thereto. The reference voltage switching circuit REF SW causes the reference voltage lines RLn and RLn+1 to be coupled to the reference voltage source during second to fifth periods for internal compensation, and causes the reference voltage lines RLn and RLn+1 to be coupled to the current sensing circuit ADC during a first period for sensing current for external compensation.
The first switch S1 of each reference voltage switching circuit REF SW is turned on in response to a switching control signal SC having a gate high voltage VGH supplied from a switching control line SCL being true. The first switch S1, when on, couples the reference voltage lines RLn to the reference voltage source supplying a reference voltage REF. A gate electrode of the first switch S1 is coupled to the switching control line SCL, a source electrode thereof is coupled to the reference voltage source, and a drain electrode thereof is coupled to the reference voltage lines RLn.
The second switch S2 of each reference voltage switching circuit REF SW is turned on in response to the complement of the gate high voltage VGH of the switching control signal SC supplied from the switching control line SCL being true when inverted by an inverter Inv. In other words, the second switch S2 turns on in response to a gate low voltage VGL of the switching control signal SC. The second switch S2, when on, couples the reference voltage lines RLn to the current sensing circuit ADC. A gate electrode of the second switch S2 is coupled to the inverter, a source electrode thereof is coupled to the current sensing circuit ADC, and a drain electrode thereof is coupled to the reference voltage lines RLn.
The inverter Inv inverts the switching control signal SC supplied from the switching control line SCL to generate a complement of the switching control signal SC. The inverter Inv is coupled between the switching control line SCL and the gate electrode of the second switch S2.
The current sensing circuit ADC is coupled to the reference voltage lines RLn and RLn+1 during the first period to sense the current flowing through the reference voltage lines RLn and RLn+1. The current sensing circuit ADC converts sensed current into digital data, and outputs the converted digital data to a timing controller 40.
Referring to
The high-potential voltage VDD, the scan signals SCANm and SCANm+1, the emission signal EM, the sensing signal SEN, and the switching control signal SC are generated every frame period. One frame period comprises a first vertical blank interval VBI1, an active interval, and a second vertical blank interval VBI2. The active interval refers to an interval for supplying an effective data voltage DATA to the display panel 10, the first vertical blank interval VBI1 refers to a blank interval before the active interval, and the second vertical interval VBI2 refers to a blank interval after the active interval. The data voltage DATA is generated every horizontal period 1H during the active interval. One horizontal period 1H refers to one line scanning period in which data is written in pixels of one horizontal line in the display panel 10.
The data voltage DATA is generated during the active interval in synchronization with the scan signals SCANm and SCANm+1. It should be noted that
Firstly, the data voltage DATA, high-potential voltage VDD, scan signals SCANm and SCANm+1, emission signal EM, sensing signal SEN, and switching control signal SC which are input into the display panel 10 during the first vertical blank interval VBI1 will be described. The first vertical blank interval VBI1 may be divided into first to third periods t1, t2, and t3. The data voltage DATA is generated at a preset voltage Vpre during the first to third periods t1, t2, and t3. The high-potential voltage VDD is generated at a high level VDD_H during the first and third periods t1 and t3 and at a low level VDD_L during the second period t2. The emission signal EM is generated at a gate low voltage VGL during the first period t1 and at a gate high voltage VGH during the second and third periods t2 and t3. The sensing signal SEN is generated at the gate high voltage VGH during the first period t1 and at the gate low voltage VGL during the second and third periods t2 and t3. The switching control signal SC is generated at the gate low voltage VGL during the first period t1 and at the gate high voltage VGH during the second and third periods t2 and t3. Meanwhile, in the description, a first logic level voltage is exampled as the gate high voltage VGH, and a second logic level voltage may is exampled as the gate low voltage VGL.
The organic light emitting diode display device of the present invention externally compensates the threshold voltage and electron mobility of driving TFTs of pixels coupled to one scan line or the threshold voltage of organic light emitting diodes of the pixels every frame period.
Secondly, the data voltage DATA, high-potential voltage VDD, scan signals SCANm and SCaNm+1, emission signal EM, sensing signal SEN, and switching control signal SC which are input into the display panel 10 during the active interval will be described. The active interval is an interval in which data voltages are written (e.g., sequentially) into pixels P of the display panel 10. The active interval may be defined as a fourth period t4. The data voltage DATA is generated every horizontal period 1H during the fourth period t4. The high-potential voltage VDD is generated at a middle level VDD_M during the fourth period t4. The reason why the high-potential voltage VDD is generated at the middle level VDD_M during the fourth period t4 is to prevent an organic light emitting diode OLED from emitting light by the turning-on of a driving TFT DT. As a result, light emission of the organic light emitting diode OLED can be prevented by generating the high-potential voltage VDD at the middle level VDD_M during the fourth period t4, thereby achieving a higher contrast ratio.
The scan signals SCANm and SCANm+1 are generated at the gate high voltage VGH in synchronization with the data voltage DATA during the fourth period t4. That is, the mth scan signal SCANm is generated at the gate high voltage VGH during a period for synchronization with an mth data voltage Dm and at the gate low voltage VGL during the remaining period. The (m+1)th scan signal SCANm+1 is generated at the gate high voltage during a period for synchronization with an (m+1)th data voltage Dm+1 and at the gate low voltage VGL during the remaining period. The emission signal EM is generated at the gate low voltage VGL during the fourth period t4. The switching control signal SC is generated at the gate high voltage VGH during the fourth period t4.
Thirdly, the data voltage DATA, high-potential voltage VDD, scan signals SCANm and SCANm+1, emission signal EM, sensing signal SEN, and switching control signal SC which are input into the display panel 10 during the second vertical blank interval VBI2 will be described. The second vertical blank interval VBI2 corresponds to a fifth period t5. The data voltage DATA is generated at the preset voltage Vpre during the fifth period t5. The high-potential voltage VDD is generated at the high level VDD_H during the fifth period t5. The scan signals SCANm and SCANm+1 are generated at the gate low voltage VGL during the fifth period t5. The emission signal EM is generated at the gate high voltage VGH during an A part t5-A of the fifth period t5 and at the gate low voltage VGL during a B part t5-B of the fifth period t5. The sensing signal SEN is generated at the gate low voltage VGL during the fifth period t5. The switching control signal SC is generated at the gate high voltage VGH during the fifth period t5.
Firstly, during the first period t1, the mth scan signal SCANm having the gate high voltage VGH is supplied through the mth scan line SLm, and the emission signal EM having the gate low voltage VGL is supplied through the emission line EML. During the first period t1, the sensing signal SEN having the gate high voltage VGH is supplied through the sensing line SENL, and the switching control signal SC having the gate low voltage VGL is supplied through the switching control line SCL. Also, during the first period t1, the data voltage DATA of the preset voltage Vpre is supplied through the nth data line DLn, and the high-potential voltage VDD_H of high level is supplied from the high-potential voltage source.
The first switch S1 is turned off in response to the switching control signal SC having the gate low voltage VGL. The second switch S2 is turned on in response to the inverter Inv inverting the gate low voltage VGL of the switching control signal SC to couple the current sensing circuit ADC to the (n+1)th reference voltage line RLn+1. By the turning-off of the first switch S1 and the turning-on of the second switch S2, the (n+1)th reference voltage line RLn+1 is disconnected from the reference voltage source, and connected to the current sensing circuit ADC.
The first TFT T1 is turned on in response to the mth scan signal SCANm having the gate high voltage VGH to connect the first node N1 to the nth data line DLn. The second TFT T2 is turned off in response to the emission signal EM having the gate low voltage VGL. The third TFT T3 is turned on response to the sensing signal SEN having the gate high voltage VGH to connect the second node N2 to the (n+1)th reference voltage line RLn+1.
During the first period t1, the preset voltage Vpre of the nth data line DLn is supplied to the first node N1 by the turning-on of the first TFT T1. In the case of sensing the drain-source current Ids of the driving TFT DT, the preset voltage Vpre applied during the first period t1 needs to be a voltage enough to turn on the driving TFT DT. That is, the preset voltage Vpre is applied such that a voltage difference Vgs between the preset voltage Vpre, which is the voltage of the gate electrode of the driving TFT DT, and the high-potential voltage VDD, which is the voltage of the source electrode thereof, is greater than a threshold voltage Vth. In this case, as shown in
Moreover, in the case of sensing the current Ioled of the organic light emitting diode OLED, the preset voltage Vpre applied during the first period t1 should be set at a level to turn off the driving TFT DT. That is, the preset voltage Vpre is applied at a level such that a voltage difference Vgs between the preset voltage Vpre, which is the voltage of the gate electrode of the driving TFT DT, and the high-potential voltage VDD, which is the voltage of the source electrode thereof, is less than a threshold voltage Vth. In this case, as shown in
Secondly, during the second period t2, the mth scan signal SCANm having the gate high voltage VGH is supplied through the mth scan line SLm, and the emission signal EM having the gate high voltage VGH is supplied through the emission line EML. During the second period t2, the sensing signal SEN having the gate low voltage VGL is supplied through the sensing line SENL, and the switching control signal SC having the gate high voltage VGH is supplied through the switching control line SCL. Also, during the second period t2, the data voltage DATA of the preset voltage Vpre is supplied through the nth data line DLn, and the high-potential voltage VDD_L of low level is supplied from the low-potential voltage source.
The first switch S1 is turned on in response to the switching control signal SC having the gate high voltage VGH to connect the reference voltage source to the (n+1)th reference voltage line RLn+1. The second switch S2 is turned off in response to an inverted signal of the switching control signal SC. By the turning-on of the first switch S1 and the turning-off of the second switch S2, the (n+1)th reference voltage RLn+1 is uncoupled from the current sensing circuit ADC and coupled to the reference voltage source.
The first TFT T1 is turned on in response to the mth scan signal SCANm having the gate high voltage VGH to couple the first node N1 to the nth data line DLn. The second TFT T2 is turned on in response to the emission signal EM having the gate high voltage VGH to connect the second node N2 to the third node N3. The third TFT T3 is turned off in response to the sensing signal SEN having the gate low voltage VGL.
During the second period t2, the preset voltage Vpre of the nth data line DLn is supplied to the first node N1 by the turning-on of the first TFT T1. Because the high-potential voltage VDD_L of low level is supplied from the high-potential voltage source during the second period t2, the drain electrode of the driving TFT DT coupled to the high-potential voltage source functions as a source electrode, and the source electrode of the driving TFT DT coupled to the second node N2 functions as a drain electrode. Accordingly, the voltage difference Vgs between the gate and source electrodes of the driving TFT is greater than the threshold voltage Vth during the period t2, thereby turning on the driving TFT DT. By the turning-on of the driving TFT DT is turned on, the second node N2 is discharged to the high-potential voltage VDD_L of low level. Moreover, by the turning-on of the third TFT T3, the third node N3 coupled to the second node N2 is also discharged to the high-potential voltage VDD_L of low level.
Thirdly, the mth scan signal SCANm having the gate high voltage VGH is supplied through the mth scan line SLm during the A part t3-A of the third period t3, and the mth scan signal SCANm having the gate low voltage VGL is supplied through the mth scan line SLm during the B part t3-B of the third period t3. Also, during the third period t3, the emission signal EM having the gate high voltage VGH is supplied through the emission line EML, the sensing signal SEN having the gate low voltage VGL is supplied through the sensing line SENL, and the switching control signal SC having the gate high voltage VGH is supplied through the switching control line SCL. Also, during the third period t3, the data voltage DATA of the preset voltage Vpre is supplied through the nth data line DLn, and the high-potential voltage VDD_H of high level is supplied from the high-potential voltage source.
The first switch S1 is turned on in response to the switching control signal SC having the gate high voltage VGH to couple the reference voltage source to the (n+1)th reference voltage line RLn+1. The second switch S2 is turned off in response to the inverted signal of the switching control signal SC. By the turning-on of the first switch S1 and the turning-off of the second switch S2, the (n+1)th reference voltage line RLn+1 is uncoupled from the current sensing circuit ADC and coupled to the reference voltage source.
The first TFT T1 is turned on in response to the mth scan signal SCANm having the gate high voltage VGH during the A part t3-A of the third period t3, and turned off in response to the mth scan signal SCANm having the gate low voltage VGL during the B part t3-B of the third period t3. The second TFT T2 is turned on in response to the emission signal EM having the gate high voltage VGH to connect the second node N2 to the third node N3. The third TFT T3 is turned off in response to the sensing signal SEN having the gate low voltage VGL.
The high-potential voltage VDD_H of high level is supplied from the high-potential voltage source during the third period t3. Because the voltage difference Vgs between the gate and source electrodes of the driving TFT DT is greater than the threshold voltage Vth, the driving TFT DT forms a current path until the voltage difference Vgs between the gate and source electrodes reaches the threshold voltage Vth. Accordingly, the voltage of the second node N2 rises up to a differential voltage Vpre-Vth between the preset voltage Vpre and the threshold voltage Vth of the driving TFT DT. Moreover, as the third node N3 is coupled to the second node N2 by the turning-on of the third TFT T3, the voltage of the third node N3 rises up to the differential voltage Vpre-Vth between the preset voltage Vpre and the threshold voltage Vth of the driving TFT DT.
The B part t3-B of the third period t3 may be defined as a floating period of the first node N1. As the first node N1 floats during the B part t3-B of the third period t3, a change in the voltage of the second node N2 may be applied to the first node N1 by a parasitic capacitance existing between the gate electrode and source electrode of the driving TFT DT. Due to this, the voltage of the first node N1 is increased, thereby enhancing the sensing speed of the threshold voltage Vth of the driving TFT DT.
Consequently, the second node N2 and the third node N3 sense the threshold voltage Vth of the driving TFT DT during the third period t3. That is, the third period t3 may be appropriately set to approximately two or more horizontal periods by a preliminary test. A detailed description thereof will be described later with reference to
Fourthly, during the fourth period t4, the mth scan signal SCANm having the gate high voltage VGH to be synchronized with the mth data voltage Dm is supplied through the mth scan line SLM, and the emission signal EM having the gate low voltage VGL is supplied thorough the emission line EML. During the fourth period t4, the sensing signal SEN having the gate low voltage VGL is supplied through the sensing line SENL, and the switching control signal SC having the gate high voltage VGH is supplied through the switching control line SCL. Also, during the fourth period t4, the data voltage DATA comprising the first to kth data voltages D1 to Dk is supplied through the nth data line DLn, and the high-potential voltage VDD_M of middle level is supplied from the high-potential voltage source.
The first switch S1 is turned on in response to the switching control signal SC having the gate high voltage VGH to couple the reference voltage source to the (n+1)th reference voltage line RLn+1. The second switch S2 is turned off in response to the inverted signal of the switching control signal SC. By the turning-on of the first switch S1 and the turning-off of the second switch S2, the (n+1)th reference voltage line RLn+1 is decoupled from the current sensing circuit ADC and coupled to the reference voltage source.
The first TFT T1 is turned on in response to the mth scan signal SCANm having the gate high voltage VGH during a period for synchronization with the mth data voltage Dm in the fourth period t4. The second TFT T2 is turned off in response to the emission signal EM having the gate low voltage VGL. The third TFT T3 is turned off in response to the sensing signal SEN having the gate low voltage VGL.
By the turning-on of the first TFT T1, the first node N1 is charged with the data voltage DATA. The third TFT T3 is turned off by the emission signal EM having the gate low voltage VGL. By the turning-off of the third TFT T3, the second node N2 is decoupled from the third node N3, and the third node N3 floats. As the third node N3 floats during t4, a change in the voltage of the first node N1 is applied to the third node N3 by the first capacitor C1.
That is, ‘Vpre-DATA, the change in the voltage of the first node N1, is applied to the third node N3. However, the third node N3 is coupled between the first and second capacitors C1 and C2 coupled in series. Hence, the voltage change is applied in the ratio of C′ as shown in Equation 2:
where CA1 represents the capacitance of the first capacitor C1, and CA2 represents the capacitance of the second capacitor C2. As a consequence, ‘C’(Vpre-DATA)' is applied to the third node N3, and therefore the voltage of the third node N3 is changed to ‘Vpre-Vth-C’(Vpre-DATA)'.
Fifthly, the mth scan signal SCANm having the gate low voltage VGL is supplied through the mth scan line SLm during the fifth period t5. Also, the emission signal EM having the gate high voltage VGH is supplied through the emission line EML during the A part t5-A of the fifth period t5, and the emission signal EM having the gate low voltage VGL is supplied through the emission line EML during the B part t5-B of the fifth period t5. Also, during the fifth period t5, the sensing signal having the gate low voltage VGL is supplied through the sensing line SENL, and the switching control signal SC having the gate high voltage VGH is supplied through the switching control line SCL. Also, during the fifth period t5, the data voltage DATA of the preset voltage Vpre is supplied through the nth data line DLn, and the high-potential voltage VDD_H of high level is supplied from the high-potential voltage source.
The first switch S1 is turned on in response to the switching control signal SC having the gate high voltage VGH to couple the reference voltage source to the (n+1)th reference voltage line RLn+1. The second switch S2 is turned off in response to the inverted signal of the switching control signal SC. By the turning-on of the first switch S1 and the turning-off of the second switch S2, the (n+1)th reference voltage line RLN+1 is decoupled from the current sensing circuit ADC and coupled to the reference voltage source.
The first TFT T1 is turned off in response to the mth scan signal SCANm having the gate low voltage VGL. The second TFT T2 is turned on in response to the emission signal EM having the gate high voltage VGH during the A part t5-A of the fifth period t5 to couple the second node N2 to the third node N3, and turned off in response to the emission signal EM having the gate low voltage VGL during the B part t5-B of the fifth period t5. The third TFT T3 is turned off in response to the sensing signal SEN having the gate low voltage VGL.
As the second node N2 is coupled to the third node N3 by the turning-on of the second TFT T2 during the A part t5-A of the fifth period t5, the voltage of the third node N3 rises up to the voltage Voled_anode of the second node N2. As the first node N1 floats during the fifth period t5 by the turning-off of the first TFT T1, a change in the voltage of the third node N3 is applied to the first node N1 by the first capacitor C1. That is, ‘Vpre-Vth-C′(Vpre-DATA)-Voled_anode’, the change in the voltage of the third node N3, is applied to the first node N1. Accordingly, the voltage of the first node N1 is changed to ‘DATA-{Vrep-Vth-C′(Vrep-DATA)-Voled_anode}’.
The drain-source current Ids of the driving TFT DT supplied to the organic light emitting diode OLED is represented by Equation 3:
I
ds
=k′·(Vgs−Vth)2 [Equation 3]
where k′ represents a proportionality coefficient determined by the structure and physical properties of the driving TFT, depending on the electron mobility of the driving TFT DT, channel width, channel length, etc. Vgs represents the voltage difference between the gate and source electrodes of the driving TFT, and Vth represents the threshold voltage of the driving TFT DT. ‘Vgs-Vth’ during the A part t5-A of the fifth period t5 is as shown in Equation 4:
Vgs−Vth=[DATA−{Vpre−Vth−C′(Vpre−DATA)−Voled anode}−Voled anode]−Vth [Equation 4]
To sum up Equation 4, the drain-source current Ids of the driving TFT DT is derived as in Equation 5:
I
ds
=k′[(1+C′)·(DATA−Vpre)]2 [Equation 5]
As a consequence, as shown in Equation 5, the drain-source current Ids of the driving TFT DT supplied to the organic light emitting diode OLED during t5 does not depend upon the threshold voltage Vth of the driving TFT DT. That is, the present invention makes it possible to compensate the threshold voltage of the driving TFT DT.
Overall, in the pixel P according to the first embodiment of the present invention, the high-potential voltage VDD is supplied at a low level VDD_L during an initialization period (t1) to initialize the second node N2 coupled to the source electrode of the driving TFT DT to the high-potential voltage VDD_L of low level. The high-potential voltage VDD_L of low level is set to a voltage lower than the differential voltage between the preset voltage Vpre and the threshold voltage Vth of the driving TFT DT. As a result, the pixel P according to the first embodiment of the present invention allows the voltage difference Vgs between the gate and source electrodes of the driving TFT DT to be larger than the threshold voltage Vth during the threshold voltage sensing period (t2), even if the threshold voltage Vth of the driving TFT DT is shifted to a negative voltage. Due to this, the driving TFT DT forms a current path until the voltage difference Vgs between the gate and source electrodes reaches the threshold voltage Vth. Accordingly, the voltage of the second node N2 rises up to a differential voltage REF1-Vth between a reference voltage REF and the threshold voltage Vth of the driving TFT DT. Therefore, even if the threshold voltage Vth of the driving TFT DT is shifted to a negative voltage, the second node N2 can sense the threshold voltage Vth. A negative shift refers to shifting the threshold voltage Vth of the driving TFT DT to a voltage lower than 0 V when the driving TFT DT is implemented as an N-type MOSFET.
Due to degradation of the driving TFT, the threshold voltage Vth of the driving TFT DT may be shifted by −2.0 V to +2.0 V from the reference value for each pixel P. Accordingly, the organic light emitting diode display devices may allow the organic light emitting diode OLED to emit light, without depending on the threshold voltage Vth, by sensing the threshold voltage with of the driving TFT DT of each pixel P and compensating the threshold voltage Vth. However, if the accuracy of sensing the threshold voltage Vth of the driving TFT DT is low, the threshold voltage Vth sensed during the threshold voltage sensing period (t3) and an actual threshold voltage of the driving TFT DT are different. Thus, ‘Vth’ is not omitted from Equation 4. For this reason, an error occurs in the drain-source current Ids of the driving TFT DT supplied to the organic light emitting diode OLED.
The floating period (B part t3-B of the third period) of the first node N1 allows for improved sensing speed of the threshold voltage Vth of the driving TFT DT. Accordingly, in the first embodiment of the present invention, if the floating period (B part t3-B of the third period) of the first node N1 is set to three horizontal periods 3H, as shown in
The signals input into the pixel P according to the second embodiment of the present invention are similar to the signals input into the pixel P according to the first embodiment of the present invention described in conjunction with
The high-potential voltage VDD is generated at the high-potential voltage VDD_H of high level during the first to third periods t1 to t3 and the fifth period t5 and at the high-potential voltage VDD_M of middle level during the fourth period t4. The reason why the high-potential voltage VDD is generated at the middle level VDD_M during the fourth period t4 is to prevent an organic light emitting diode OLED from emitting light by the turning-on of a driving TFT DT. As a result, light emission of the organic light emitting diode OLED can be reduced by generating the high-potential voltage VDD at the middle level VDD_M during the fourth period t4, thereby achieving a higher contrast ratio. Also, the sensing signal SEN is generated at the gate high voltage VGH during the first and second periods t1 and t2 and at the gate low voltage VGL during the third to fifth periods t3, t4, and t5.
Hereinafter, an operation of the pixel P during the first to fifth periods t1 to t5 will be described in detail with reference to
During the second period t2, the mth scan signal SCANm having the gate high voltage VGH is supplied through the mth scan line SLm, and the emission signal EM having the gate low voltage VGL is supplied through the emission line EML. During the second period t2, the sensing signal SEN having the gate high voltage VGH is supplied through the sensing line SENL, and the switching control signal SC having the gate low voltage VGL is supplied through the switching control line SCL. Also, during the second period t2, the data voltage DATA of the preset voltage Vpre is supplied through the nth data line DLn, and the high-potential voltage VDD_H of high level is supplied from the high-potential voltage source.
The first switch S1 is turned on in response to the switching control signal SC having the gate high voltage VGH to couple the reference voltage source to the (n+1)th reference voltage line RLn+1. The second switch S2 is turned off in response to an inverted signal of the switching control signal SC. By the turning-on of the first switch S1 and the turning-off of the second switch S2, the (n+1)th reference voltage line RLn+1 is decoupled from the current sensing circuit ADC and coupled to the reference voltage source.
The first TFT T1 is turned on in response to the mth scan signal SCANm having the gate high voltage VGH to couple the first node N1 to the nth data line DLn. The second TFT T2 is turned on in response to the emission signal EM having the gate high voltage VGH to couple the second node N2 to the third node N3. The third TFT T3 is turned on response to the sensing signal SEN having the gate high voltage VGH to couple the (n+1)th reference voltage line RLn+1 to the second node N2.
As the second node N2 is coupled to the (n+1)th reference voltage line RLn+1, which is coupled to the reference voltage source during the second period t2, the second node N2 is discharged to the reference voltage REF. Also, the second node N2 is coupled to the third node N3 by the turning-on of the second TFT T2, the third node N3 is discharged to the reference voltage REF. It should be noted that the ‘reference voltage REF’ described in
The structure and operating method of the pixel P according to the second embodiment of the present invention are substantially identical to those of the pixel P according to the first embodiment of the present invention described with reference to
The third capacitor C3 is coupled between the first node 1 and the high-potential voltage source, and stores a differential voltage between the first node N1 and the high-potential voltage source. The third capacitor C3 prevents a change in the voltage of the second node N2 from being applied to the first node N1 by a parasitic capacitance of the driving TFT DT. This prevents an increase in the voltage of the first node N1, thereby enhancing grayscale representation capability. That is to say, a higher contrast ratio can be achieved.
The structure and operating method of the pixel P according to the third embodiment of the present invention are substantially identical to those of the pixel P according to the first embodiment of the present invention described with reference to
Each data voltage switching circuit DATA SW comprises first and second switches S1 and S2, an inverter Inv, a current sensing circuit ADC, and a source drive IC S-IC. It should be noted that, although the first and second switches S1 and S2 have been described as being implemented as N-type MOSFETs, the present invention is not limited thereto. For example, the first and second switches S1 and S2 may be implemented as P-type MOSFETs. The data voltage switching circuit DATA SW causes the data lines DLn to be coupled to the source drive IC S-IC during second to fifth periods for internal compensation, and causes the data lines DLn to be coupled to the current sensing circuit ADC during a first period for sensing current for external compensation.
The first switch S1 is turned on in response to a switching control signal SC having a gate high voltage VGH supplied from a switching control line SCL to couple the data lines DLn to the source drive IC S-IC supplying a data voltage DATA. A gate electrode of the first switch S1 is coupled to the switching control line SCL, a source electrode thereof is coupled to the data lines DLn, and a drain electrode thereof is coupled to the source drive IC S-IC.
The second switch S2 is turned on in response to the gate low voltage VGL of the switching control signal SC supplied from the switching control line SCL when inverted by inverter Inv to couple the data lines DLn to the current sensing circuit ADC. A gate electrode of the second switch S2 is coupled to the inverter, a source electrode thereof is coupled to the current sensing circuit ADC, and a drain electrode thereof is coupled to the data lines DLn.
The inverter Inv inverts the switching control signal SC supplied from the switching control line SCL. The inverter Inv is coupled between the switching control line SCL and the gate electrode of the second switch S2.
The current sensing circuit ADC is coupled to the data voltage lines DLn and DLn+1 during the first period to sense the current flowing through the data lines DLn and DLn+1. The current sensing circuit ADC converts sensed current into digital data, and outputs the converted digital data to a timing controller 40. The reference voltage source is coupled to the other electrode of the second capacitor C2.
Data lines DL and scan lines SL crossing each other are formed on the display panel 10. Emission lines EML and sensing lines SENL are formed in parallel with the scan lines SL on the display panel 10. Switching control lines SCL may be formed in parallel with the scan lines SL on the display panel 10. Also, pixels P are arranged in a matrix form on the display panel 10. Each of the pixels P of the display panel 10 is as described in conjunction with
The data driver 20 comprises a plurality of source drive ICs. The source drive ICs receive digital video data RGB' from the timing controller 40, the digital video data RGB' comprising a compensated threshold voltage Vth and electron mobility of a driving TFT DT and a compensated threshold voltage of an organic light emitting diode OLED. The source drive ICs convert the compensated digital video data RGB' into a gamma compensation voltage in response to a source timing control signal DCS from the timing controller 40 to generate a data voltage and supply the data voltage to the data lines DL of the display panel 10 in synchronization with a scan signal SCAN.
The scan driver 30 comprises a scan signal output part, an emission signal output part, a sensing signal output part, and a switching control signal output part. The scan signal output part sequentially outputs scan signals SCAN to the first scan lines SL1 of the display panel 10. The emission signal output part sequentially outputs an emission signal EM to the emission lines EML of the display panel 10. The sensing signal output part outputs a sensing signal SEN to the sensing lines SENL of the display panel 10. The switching control signal output part sequentially outputs a switching control signal SC to the switching control lines SCL of the display panel 10. Detailed descriptions of the scan signals SCAN, the emission signal EM, the sensing signal SEN, and the switching control signal SC are described in detail in conjunction with
The timing controller 40 receives digital video data RGB from the host system 50 through a low voltage differential signaling (LVDS) interface, a transition minimized differential signaling (TMDS) interface, etc. The timing controller 40 may comprise an external compensator for externally compensating the threshold voltage Vth and electron mobility of the driving TFT and the threshold voltage Vth of the organic light emitting diode OLED. The external compensator 40 applies compensated data, which is calculated using an external compensation method, to the digital video data RGB input from the host system 50, and outputs compensated digital video data RGB' to the data driver 20.
The timing controller 40 receives timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock, and generates timing control signals for controlling operation timings of the data driver 20 and scan driver 30 based on the timing signals from the host system 50. The timing control signals comprise a scan timing control signal for controlling the operation timing of the scan driver 30 and a data timing control signal for controlling the operation timing of the data driver 20. The timing controller 40 outputs the scan timing control signal to the scan driver 30, and outputs the data timing control signal to the data driver 20.
The display panel 10 may further comprise a power supply unit (not shown). The power supply unit supplies a high-potential voltage VDD, a low-potential voltage VSS, and a reference voltage REF to the display panel 10, among other voltage signals and levels described herein. For example, the power supply unit supplies a gate high voltage VGH and a gate low voltage VGL to the scan driver 30.
Firstly, the drain-source current Ids of the driving TFT DT of each of the pixels P and the current Ioled of the organic light emitting diode OLED thereof are sensed by using a current sensing circuit ADC coupled to the second reference voltage line RL2 of each of the pixels P of the display panel 10. The sensing of the drain-source current Ids of the driving TFT DT using the current sensing circuit ADC has been described in detail in conjunction with
Secondly, the compensation data calculator 41a calculates external compensation data by using the digital data input from the current sensing circuit ADC. The compensation data calculator 41a can calculate external compensation data, which comprises a compensated threshold voltage Vth and electron mobility of the driving TFT DT and a compensated threshold voltage Vth of the organic light emitting diode, based on the input digital data by using a well-known external compensation calculation method (S2).
Thirdly, the compensated digital video data output part 41b receives digital video data RGB from the host system 50, and receives the external compensation data from the compensation data calculator 41a. The compensated digital video data output part 41b applies the external compensation data to the input digital video data RGB to generate compensated digital video data RGB'. The compensation digital video data output part 41b outputs the compensated digital video data RGB' to the data driver 20 (S3).
As discussed above, a gate node of a driving TFT is initialized to a preset voltage during an initialization period, and a source node of the driving TFT is initialized to a high-potential voltage of low level. The high-potential voltage of low level is set to a voltage lower than a differential voltage between the preset voltage and the threshold voltage of the driving TFT. As a result, the voltage difference between the gate and source of the driving TFT is allowed to be larger than the threshold voltage during a threshold voltage sensing period, even if the threshold voltage of the driving TFT is shifted to a negative voltage. Therefore, the threshold voltage can be sensed by using the source node of the driving TFT.
Moreover, the drain-source current of the driving TFT and the current of the organic light emitting diode may be sensed by using reference voltage lines. As a result, the sensed current may be compensated for by an external compensation method. Therefore, the electron mobility of the driving TFT and the threshold voltage of the organic light emitting diode, as well as the threshold voltage of the driving TFT, can be compensated.
Furthermore, a period for sensing the threshold voltage of the driving TFT comprises a period for allowing the gate node of the driving TFT to float. As a result, sensing speed of the threshold voltage of the driving TFT is enhanced by using the period for allowing the gate node of the driving TFT to float.
In addition, a capacitor is coupled between the high-potential voltage source and the gate node of the driving TFT. As a result, an increase in the voltage of the gate node of the driving TFT is prevented during the period in which the gate node of the driving TFT floats, thereby enhancing black grayscale representation capability. Due to this, the present invention offers a higher contrast ratio.
Additionally, the threshold voltage of the driving TFT is sensed during two or more horizontal periods. As a result, the threshold voltage of the driving TFT may be accurately sensed even when a large area, high-resolution organic light emitting diode display device is driven at high speed, such as at a frame frequency of 240 Hz or more.
Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2011-0121137 | Nov 2011 | KR | national |
