The present application relates to the field of display technologies, and especially relates to an organic light emitting diode (OLED) display panel and a method of manufacturing the same, and a display terminal.
Among flat panel display technologies, organic light emitting diode (OLED) display devices have many advantages such as lightweight and thinness, active light emission, fast response speed, large viewing angle, wide color gamut, high brightness and low power consumption.
For existing OLED display panels in prior art, in order to increase transmittances of the OLED display panels of top emission, the thickness of a metal cathode is thin, and thus a square resistance of the metal cathode is large, and a voltage drop (IR-drop) is serious. As a result, the OLED display panels have obvious uneven brightness phenomenon, which seriously affects display effects of the OLED display devices.
An object of the present application is to provide an organic light emitting diode (OLED) display panel and a method of manufacturing the same, and a display terminal, so as to solve a technical problem that the OLED display panel has a poor display effect caused by a large impedance of a cathode of which the thickness is thin.
In order to achieve the object mentioned above, the present application provides an organic light emitting diode (OLED) display panel. The OLED display panel includes an array substrate, a protective layer, an anode, a light emitting functional layer, and a cathode. The array substrate includes a first auxiliary electrode, a second auxiliary electrode, a third auxiliary electrode, and interlayer insulating layers. The interlayer insulating layers are disposed between the first auxiliary electrode and the second auxiliary electrode, and between the second auxiliary electrode and the third auxiliary electrode. The second auxiliary electrode is disposed on the first auxiliary electrode, and the third auxiliary electrode is disposed on the second auxiliary electrode. The third auxiliary electrode is connected to the first auxiliary electrode and the second auxiliary electrode. The protective layer is disposed on the third auxiliary electrode, and is provided with an undercut opening. The undercut opening is configured to expose a portion of the third auxiliary electrode. The anode is disposed on the protective layer. The light emitting functional layer is disposed on the anode. The cathode is disposed on the light emitting functional layer, and the cathode extends into the undercut opening and is connected to the third auxiliary electrode.
Further, the third auxiliary electrode is connected to the first auxiliary electrode by at least one first conductive hole. The third auxiliary electrode is connected to the second auxiliary electrode by at least one second conductive hole.
Further, the third auxiliary electrode is connected to the first auxiliary electrode by two first conductive holes. One of the two first conductive holes is connected to one side of the first auxiliary electrode, and another one of the two first conductive holes is connected to another side of the first auxiliary electrode. The second auxiliary electrode is disposed between the two first conductive holes.
Further, the third auxiliary electrode is connected to the second auxiliary electrode by two second conductive holes.
Further, the array substrate further includes a light shielding layer, a gate, and a source-drain electrode. The light shielding layer is disposed in a same layer as the first auxiliary electrode. The gate is disposed in a same layer as the second auxiliary electrode. The source-drain electrode is disposed in a same layer as the third auxiliary electrode.
Further, the OLED display panel further includes a substrate layer, a buffer layer, an active layer, a first gate insulating layer, a second gate insulating layer, and a dielectric layer. The light shielding layer and the first auxiliary electrode are disposed on the substrate layer. The buffer layer is disposed on the substrate layer and covers the light shielding layer and the first auxiliary electrode. The active layer is disposed on the buffer layer. An orthographic projection of the active layer on the substrate layer falls within an orthographic projection of the light shielding layer on the substrate layer. The first gate insulating layer is correspondingly disposed on the active layer. The second gate insulating layer is correspondingly disposed on the buffer layer. The gate is correspondingly disposed on the first gate insulating layer, and the second auxiliary electrode is correspondingly disposed on the second gate insulating layer. An orthographic projection of the second auxiliary electrode on the substrate layer at least partially overlaps with an orthographic projection of the first auxiliary electrode on the substrate layer. The dielectric layer covers the gate and the second auxiliary electrode, and extends onto the buffer layer. The source-drain electrode is disposed on the dielectric layer and is connected to the active layer. The third auxiliary electrode is disposed on the dielectric layer, and is connected to the first auxiliary electrode and the second auxiliary electrode. An orthographic projection of the third auxiliary electrode on the substrate layer at least partially overlaps with an orthographic projection of the first auxiliary electrode on the substrate layer. The interlayer insulating layers includes the buffer layer, the dielectric layer, and the protective layer.
Further, the protective layer includes a passivation layer and a planarization layer. The passivation layer is disposed on the third auxiliary electrode, and is provided with a first through hole. The planarization layer is disposed on the passivation layer, and is provided with a second through hole. The second through hole is communicated with the first through hole. An orthographic projection of the second through hole on the array substrate completely falls within an orthographic projection of the first through hole on the array substrate, so that the undercut opening is defined between the planarization layer and the passivation layer.
Further, the OLED display panel further includes a pixel defining layer. The pixel defining layer is disposed on the protective layer, and is provided with a third through hole and a pixel opening. The third through hole is communicated with the second through hole, and the pixel opening is configured to expose the anode. The light emitting functional layer is disposed on the anode and the pixel defining layer. The cathode is disposed on the light emitting functional layer and extends into the third through hole and the undercut opening, and the cathode is connected to the third auxiliary electrode.
In order to achieve the object mentioned above, the present application further provides a method of manufacturing an organic light emitting diode (OLED) display panel. The method includes following steps: forming an array substrate; forming a protective layer disposed on a third auxiliary electrode and extending to the array substrate; performing a hole-digging treatment on the protective layer, so that the protective layer is provided with an undercut opening exposing a portion of the third auxiliary electrode; forming an anode disposed on the protective layer; forming a light emitting functional layer disposed on the anode; and forming a cathode disposed on the light emitting functional layer, the cathode extends into the undercut opening and is connected to the third auxiliary electrode. The forming of the array substrate includes following steps: forming a first metal layer; patterning the first metal layer to form a first auxiliary electrode; forming a second metal layer on the first metal layer; patterning the second metal layer to form a second auxiliary electrode; forming a third metal layer on the second metal layer; patterning the third metal layer to form the third auxiliary electrode. Interlayer insulating layers are disposed between the first auxiliary electrode and the second auxiliary electrode, and between the second auxiliary electrode and the third auxiliary electrode. The third auxiliary electrode is connected to the first auxiliary electrode and the second auxiliary electrode.
Further, the step of forming the protective layer includes: forming a passivation layer on the third auxiliary electrode; and forming a planarization layer disposed on the passivation layer. The step of performing the hole-digging treatment on the protective layer includes: performing the hole-digging treatment on the planarization layer and the passivation layer, so that the passivation layer is provided with a first through hole, and the planarization layer is provided with a second through hole communicate with the first through hole; and
Further, in the step of patterning the first metal layer to form a first auxiliary electrode, the first metal layer is patterned to form a light shielding layer disposed in a same layer as the first auxiliary electrode. In the step of patterning the second metal layer to form a second auxiliary electrode, the second metal layer is patterned to form a gate disposed in a same layer as the second auxiliary electrode. In the step of patterning the third metal layer to form a third auxiliary electrode, the third metal layer is patterned to form a source-drain electrode disposed in a same layer as the third auxiliary electrode.
In order to achieve the object mentioned above, the present application further provides a display terminal including a terminal body and any one of embodiments of the OLED display panel mentioned above. The terminal body is connected to the OLED display panel.
In terms of beneficial effects of the present application, the OLED display panel and the method of manufacturing the same, and the display terminal are provided. The array substrate includes the first auxiliary electrode, the second auxiliary electrode, and the third auxiliary electrode that are insulated from each other. The third auxiliary electrode is connected to the first auxiliary electrode and the second auxiliary electrode to form a cathode overlapping structure. The protective layer is provided with the undercut opening configured to expose a portion of the third auxiliary electrode. The cathode is connected to the cathode overlapping structure to define a cathode overlapping region, so that an impedance of the cathode is reduced, thereby reducing a voltage drop (IR Drop). Therefore, display brightness of each region of the OLED display panel is consistent, thereby further improving display uniformity of the OLED display panel.
The technical solutions and other beneficial effects of the present application are obvious by detailed description of specific implementations of the present application in combination with accompanying drawings.
Elements in the accompanying drawings are designed by reference numerals listed below.
The technical solutions in the embodiments of the present application are clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the embodiments described are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative works should be deemed as falling within the claims of the present application.
In the present disclosure, a structure in which a first feature is “on” or “beneath” a second feature may include an embodiment in which the first feature directly contacts the second feature, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature does not directly contact the second feature, unless otherwise specified. Furthermore, a first feature “on,” “above,” or “on top of” a second feature may include an embodiment in which the first feature is right “on,” “above,” or “on top of” the second feature, and may also include an embodiment in which the first feature is not right “on,” “above,” or “on top of” the second feature, or just means that the first feature has a sea level elevation larger than the sea level elevation of the second feature. While first feature “beneath,” “below,” or “on bottom of” a second feature may include an embodiment in which the first feature is right “beneath,” “below,” or “on bottom of” the second feature, and may also include an embodiment in which the first feature is not right “beneath,” “below,” or “on bottom of” the second feature, or just means that the first feature has a sea level elevation smaller than the sea level elevation of the second feature.
As shown in
The array substrate 1 includes a substrate layer 11, a first metal layer 12, a buffer layer 13, an active layer 14, a gate insulating layer 15, a second metal layer 16, a dielectric layer 17, and a third metal layer 18.
The substrate layer 11 may be a flexible substrate. A material of the substrate layer 11 can be polyimide (PI) or polydimethylsiloxane (PDMS), which is not specifically limited here.
The first metal layer 12 is disposed on an upper surface of the substrate layer 11. The first metal layer 12 includes a light shielding layer 122 and a first auxiliary electrode 121 which are formed by patterning processes. The light-shielding layer 122 and the first auxiliary electrode 121 are disposed in a same layer.
The buffer layer 13 covers the first auxiliary electrode 121 and the light shielding layer 122, and extends to the upper surface of the substrate layer 11.
A semiconductor layer includes an active layer 14 and a first storage capacitor electrode 144. The active layer 14 and the first storage capacitor electrode 144 are both disposed on an upper surface of the buffer layer 13. An orthographic projection of the active layer 14 on the substrate layer 11 falls within an orthographic projection of the light shielding layer 122 on the substrate layer 11. The active layer 14 includes a channel region 141, a source contact region 142 and a drain contact region 143 disposed at two sides of the channel region 141. The active layer 14 is spaced apart from the first storage capacitor electrode 144. The light shielding layer 122 is disposed correspondingly to the first storage capacitor electrode 144 to form a first storage capacitor.
In this embodiment, the source contact region 142 and the drain contact region 143 of the active layer 14, and the first storage capacitor electrode 144 are all ion-doped regions, and have conductor characteristics. The channel region 141 is a non-doped region, and has semiconductor characteristics. In an embodiment, a material of the active layer 14 may be oxide semiconductor material, such as indium zinc oxide (IZO), gallium indium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), and indium gallium zinc tin oxide (IGZTO). In another embodiment, a material of the active layer 14 may also be amorphous silicon, monocrystalline silicon, low temperature polysilicon, etc.
The gate insulating layer 15 includes a first gate insulating layer 151 and a second gate insulating layer 152 disposed in different layers. The first gate insulating layer 151 is correspondingly disposed on an upper surface of the active layer 14. The second gate insulating layer 152 is correspondingly disposed on the upper surface of the buffer layer 13.
The second metal layer 16 is disposed on an upper surface of the gate insulating layer 15. The second metal layer 16 includes a gate 161 and a second auxiliary electrode 162 which are formed by patterning processes. The gate 161 and the second auxiliary electrode 162 are formed in a same process step. That is, the gate 161 and the second auxiliary electrode 162 are disposed in a same layer. Specifically, the gate 161 is correspondingly disposed on an upper surface of the first gate insulating layer 151, and the second auxiliary electrode 162 is correspondingly disposed on an upper surface of the second gate insulating layer 152. An orthographic projection of the second auxiliary electrode 162 on the substrate layer 11 at least partially overlaps with an orthographic projection of the first auxiliary electrode 121 on the substrate layer 11.
The dielectric layer 17 is disposed on the second metal layer 16. The dielectric layer 17 covers the gate 161 and the second auxiliary electrode 162, and extends to the upper surface of the buffer layer 13.
The third metal layer 18 is disposed on an upper surface of the dielectric layer 17. The third metal layer 18 includes a source-drain electrode, a third auxiliary electrode 183, and a second storage capacitor electrode 184 which are formed by patterning process. The source-drain electrode, the third auxiliary electrode 183, and the second storage capacitor electrode 184 are disposed in a same layer. Specifically, the source-drain electrode is disposed on the dielectric layer 17, and is connected to the active layer 14. The third auxiliary electrode 183 is disposed on the dielectric layer 17, and is connected to the first auxiliary electrode 121 and the second auxiliary electrode 162. An orthographic projection of the third auxiliary electrode 183 on the substrate layer 11 at least partially overlaps with an orthographic projection of the first auxiliary electrode 121 on the substrate layer 11. In this embodiment, the source-drain electrode includes a source electrode 181 and a drain electrode 182. The source electrode 181 is connected to one side of the active layer 14, and the drain electrode 182 is connected to another side of the active layer 14. The source electrode 181 is connected to the active layer 14 by one third conductive hole 73. The drain electrode 182 is connected to the active layer 14 by another third conductive hole 73, and is connected to the light shielding layer 122 by a fourth conductive hole 74, so that an electrical performance of a transistor is improved, and a current of channel is more stable. The light shielding layer 122 is disposed correspondingly to the first storage capacitor electrode 144. The first storage capacitor electrode 144 is disposed correspondingly to the second storage capacitor electrode 184 to form a second storage capacitor.
In this embodiment, materials of the first metal layer 12, the second metal layer 16, and the third metal layer 18 may be individually selected from one or more material including metals, alloys and metal nitrides. For example, metals such as aluminum (Al), silver (Ag), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), and neodymium (Nd), or alloys or nitrides of the aforesaid metals, which may be used alone or in combination.
The protective layer 2 is disposed on the third metal layer 18. The protective layer 2 covers the source-drain electrodes 182 and the third auxiliary electrode 183, and extends to an upper surface of the dielectric layer 17. Specifically, the protective layer 2 includes a passivation layer 21 and a planarization layer 22. The passivation layer 21 is disposed on the third auxiliary electrode 183. The passivation layer 21 is provided with a first through hole 91. The planarization layer 22 is disposed on the passivation layer 21. The planarization layer 22 is provided with a second through hole 92. The second through hole 92 is communicated with the first through hole 91. A portion of the planarization layer 22 extends into the first through hole 91, so that an undercut opening 10 is defined between the planarization layer 22 and the passivation layer 21. The undercut opening 10 is configured to expose a portion of the third auxiliary electrode 183. In this embodiment, the diameter of a bottom portion of the second through hole 92 is less than the diameter of a top portion of the first through hole 91, such an arrangement ensure that an orthographic projection of the second through hole 92 on the array substrate 1 completely falls into an orthographic projection of the first through hole 91 on the array substrate 1, so that the undercut opening 10 is defined between the planarization layer 22 and the passivation layer 21. Preferably, the diameter of an orthographic projection of the second through hole 92 on the substrate layer 11 is less than the diameter of an orthographic projection of the first through hole 91 on the substrate layer 11, such an arrangement further ensure that at least a portion of the planarization layer 22 can extend into the first through hole 91, so that the undercut opening 10 is defined between the planarization layer 22 and the passivation layer 21.
In this embodiment, materials of the buffer layer 13, the gate insulating layer 15, the dielectric layer 17, and the protective layer 2 may be selected from one or more materials including silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiOxNy). It should be noted that the buffer layer 13, the dielectric layer 17, and the protective layer 2 in combination constitute interlayer insulating layers between the first auxiliary electrode 121 and the second auxiliary electrode 162, and between the second auxiliary electrode 162 and the third auxiliary electrode 183.
The anode 3 is disposed on the protective layer 2, and is connected to the source-drain electrode. A material of the anode 3 may be a transparent conductive metal oxide, such as indium tin oxide (ITO).
The pixel defining layer 5 is disposed on the protective layer 2. Specifically, the pixel defining layer 5 is provided with a third through hole 93 and a pixel opening 96. The third through hole 93 is communicated with the second through hole 92. The pixel opening 96 is configured to expose the anode 3.
The light emitting functional layer 4 is disposed on the anode 3 and the pixel defining layer 5, and is disconnected at the undercut opening 10. That is, a portion of the light emitting functional layer 4 may be connected to the third auxiliary electrode 183 disposed at the undercut opening 10, and other portions of the light emitting functional layer 4 may not be connected to the third auxiliary electrode 183 disposed at the undercut opening 10. That is, the undercut opening 10 may disconnect some of the film layers thereon. In this embodiment, as shown in
As shown in
In this embodiment, the third auxiliary electrode 183 is connected to the first auxiliary electrode 121 by at least one first conductive hole 71. The third auxiliary electrode 183 is connected to the second auxiliary electrode 162 by at least one second conductive hole 72. Each first conductive hole 71 goes through the dielectric layer 17 and the buffer layer 13, and is connected to the first auxiliary electrode 121. Each second conductive hole 72 goes through the dielectric layer 17, and is connected to the second auxiliary electrode 162.
The third auxiliary electrode 183 is connected to the first auxiliary electrode 121 by the first conductive hole 71. The third auxiliary electrode 183 is connected to the second auxiliary electrode 162 by the second conductive hole 72. With such an arrangement, the third auxiliary electrode 183 is connected to the second auxiliary electrode 162 and the first auxiliary electrode 121 to form a cathode overlapping structure. The cathode overlapping structure can reduce an impedance of the cathode 6 thereby improving a display uniformity of the OLED display panel.
As shown in
In the step of forming the first auxiliary electrode 121, the first metal layer 12 is patterned to form a light shielding layer 122. The light shielding layer 122 and the first auxiliary electrode 121 are disposed in a same layer. In the step of forming the second auxiliary electrode 162, the second metal layer 16 is patterned to form a gate 161. The gate 161 and the second auxiliary electrode 162 are disposed in a same layer. In the step of forming the third auxiliary electrode 183, the third metal layer 18 is patterned to form the source-drain electrode, and the source-drain electrode and the third auxiliary electrode 183 are disposed in a same layer.
Specifically, as shown in
In this embodiment, the source contact region 142 and the drain contact region 143 of the active layer 14, and the first storage capacitor electrode 144 are all ion-doped regions, and have conductor characteristics. The channel region 141 is a non-doped region, and has semiconductor characteristics. In an embodiment, a material of the active layer 14 may be oxide semiconductor material, such as indium zinc oxide (IZO), gallium indium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), or indium gallium zinc tin oxide (IGZTO). In another embodiment, a material of the active layer 14 may also be amorphous silicon, monocrystalline silicon, low temperature polysilicon, etc.
As shown in
As shown in
In other embodiments, the steps S4) and S32) can be exchanged, as long as the undercut opening 10 can be defined between the planarization layer 22 and the passivation layer 21, and the anode 3 is formed on the protective layer 2.
As shown in
An embodiment of the present application further provides a display terminal, the display terminal includes a terminal body and the OLED display panel mentioned above. The terminal body is connected to the OLED display panel.
This embodiment provides an organic light emitting diode (OLED) display panel and a method of manufacturing the same, and a display terminal. This embodiment includes all technical solutions of the embodiment 1, and differences include that, in this embodiment, the second auxiliary electrode 162 is disposed between two first conductive holes 71, and the third auxiliary electrode 183 is connected to the second auxiliary electrode 162 through two second conductive holes 72.
As shown in
As shown in
Therefore, in the OLED display panel provided in this embodiment, the first auxiliary electrode 121, the second auxiliary electrode 162, and the third auxiliary electrode 183 are disposed on the array substrate 1 and are insulated from each other. The third auxiliary electrode 183 is connected to the first auxiliary electrode 121 and the second auxiliary electrode 162 to form the cathode overlapping structure including a parallel connected structure. Furthermore, the protective layer 2 is provided with the undercut opening 10, the undercut opening 10 is configured to expose a portion of the third auxiliary electrode 183. The cathode is connected to the cathode overlapping structure to define a cathode overlapping region, so that the impedance of the cathode 6 is reduced and the voltage drop (IR Drop) is reduced, thereby further improving display uniformity of the OLED display panel.
This embodiment further provides a method of manufacturing an organic light emitting diode (OLED) display panel, this embodiment includes all technical solutions of the method of manufacturing the OLED display panel of embodiment 1, and differences include that, in this embodiment, in a case that hole digging treatments are performed on the dielectric layer 17, two first conductive holes 71 and two second conductive holes 72 are formed. Therefore, the third auxiliary electrode 183 is connected to the first auxiliary electrode 121 through two first conductive holes 71, and the third auxiliary electrode 183 is connected to the second auxiliary electrode 162 by two second conductive holes 72. One of the two first conductive holes 71 is connected to one side of the first auxiliary electrode 21, and another one of the two first conductive holes 71 is connected to another side of the first auxiliary electrode 121. The second auxiliary electrode 162 is disposed between the two first conductive holes 71. Each conductive holes 72 is connected to the second auxiliary electrode 162. With such arrangements, the third auxiliary electrode 183 is connected in parallel with the second auxiliary electrode 162 and the first auxiliary electrode 121 to form a cathode overlapping structure. Thus, an impedance of the cathode 6 is further reduced, so that a voltage drop (IR Drop) is reduced, thereby improving a display uniformity of the OLED display panel. In this embodiment, the second auxiliary electrode 162 is disposed between the two first conductive holes 71, such an arrangement can save a space occupied by conductive holes inside the array substrate 1. In other embodiments, the two second conductive holes 72 can be disposed on a left side or a right side of the gate insulating layer 15, as long as the third auxiliary electrode 183 can form a parallel circuit with the second auxiliary electrode 162 and the first auxiliary electrode 121.
The OLED display panel and the method of manufacturing the same and the display terminal provided in the embodiments of the present application are described in detail above. Specific implementations are used to illustrate principles and implementations of the present application. The descriptions of the above-mentioned embodiments are only used to help understand the technical solutions and core ideas of the present application. Those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or equivalently replace some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.
Number | Date | Country | Kind |
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202211363356.2 | Nov 2022 | CN | national |