Patent Application
20160063921
This relates generally to electronic devices with displays and, more particularly, to display driver circuitry for displays such as organic-light-emitting diode displays.
Electronic devices often include displays. For example, cellular telephones and portable computers include displays for presenting information to users.
Displays such as organic light-emitting diode displays have an array of display pixels based on light-emitting diodes. In this type of display, each display pixel includes a light-emitting diode and thin-film transistors for controlling application of a signal to the light-emitting diode to produce light.
Threshold voltage variations in the thin-film transistors can cause undesired visible display artifacts. For example, threshold voltage hysteresis can cause white pixels to be displayed differently depending on context. The white pixels in a frame may, as an example, be displayed accurately if they were preceded by a frame of white pixels, but may be displayed inaccurately (i.e., they may have a gray appearance) if they were preceded by a frame of black pixels. This type of history-dependent behavior of the light output of the display pixels in a display causes the display to exhibit a low response time. To address the issues associated with threshold voltage variations, displays such as organic light-emitting diode displays are provided with threshold voltage compensation circuitry. Such circuitry may not, however, adequately address all threshold voltage variations, may not satisfactorily improve response times, and may have a design that is difficult to implement.
It would therefore be desirable to be able to provide a display with improved threshold voltage compensation circuitry.
An electronic device may include a display having an array of display pixels. The display pixels may be organic light-emitting diode display pixels. Each display pixel may have an organic light-emitting diode that emits light and a drive transistor that controls the application of current to the organic light-emitting diode. The drive transistor has an associated threshold voltage.
Each display pixel may have control transistors for threshold voltage compensation and diode capacitance compensation operations. During compensation operations, the control transistors are controlled so as to compensate the drive transistor for variations in the threshold voltage of the drive transistor and to compensate for variations in the parasitic capacitance associated with the organic light-emitting diode. This ensures that the output of the light-emitting diode will be responsive to the size of the data signal loaded into the display pixel and independent of threshold voltage and its capacitance.
With one arrangement, each display pixel has six n-type transistor and a single capacitor. One of the six n-type transistors serves as the drive transistor for the display pixel and may be compensated using the remaining five of the n-type transistors and the capacitor. In this arrangement, each row of display pixels may be controlled using two scan control lines and two emission control lines. With another arrangement, each row of row of display pixel may be controlled using only one scan control line, one emission control line associated with that row, and another emission control line routed from an immediately preceding row.
A display in an electronic device may be provided with driver circuitry for displaying images on an array of display pixels. An illustrative display is shown in
Display driver circuitry such as display driver integrated circuit 16 may be coupled to conductive paths such as metal traces on substrate 24 using solder or conductive adhesive. Display driver integrated circuit 16 (sometimes referred to as a timing controller chip) may contain communications circuitry for communicating with system control circuitry over path 25. Path 25 may be formed from traces on a flexible printed circuit or other cable. The system control circuitry may be located on a main logic board in an electronic device such as a cellular telephone, computer, television, set-top box, media player, portable electronic device, or other electronic equipment in which display 14 is being used. During operation, the system control circuitry may supply display driver integrated circuit 16 with information on images to be displayed on display 14 via path 25. To display the images on display pixels 22, display driver integrated circuit 16 may supply clock signals and other control signals to display driver circuitry such as row driver circuitry 18 and column driver circuitry 20. Row driver circuitry 18 and/or column driver circuitry 20 may be formed from one or more integrated circuits and/or one or more thin-film transistor circuits on substrate 24.
Row driver circuitry 18 may be located on the left and right edges of display 14, on only a single edge of display 14, or elsewhere in display 14. During operation, row driver circuitry 18 may provide row control signals on horizontal lines 28 (sometimes referred to as row lines or “scan” lines). Row driver circuitry 18 may therefore sometimes be referred to as scan line driver circuitry. Row driver circuitry 18 may also be used to provide other row control signals, if desired.
Column driver circuitry 20 may be used to provide data signals D from display driver integrated circuit 16 onto a plurality of corresponding vertical lines 26. Column driver circuitry 20 may sometimes be referred to as data line driver circuitry or source driver circuitry. Vertical lines 26 are sometimes referred to as data lines. During compensation operations, column driver circuitry 20 may use paths such as vertical lines 26 to supply a reference voltage. During programming operations, display data is loaded into display pixels 22 using lines 26.
Each data line 26 is associated with a respective column of display pixels 22. Sets of horizontal signal lines 28 run horizontally through display 14. Power supply paths and other lines may also supply signals to pixels 22. Each set of horizontal signal lines 28 is associated with a respective row of display pixels 22. The number of horizontal signal lines in each row may be determined by the number of transistors in the display pixels 22 that are being controlled independently by the horizontal signal lines. Display pixels of different configurations may be operated by different numbers of control lines, data lines, power supply lines, etc.
Row driver circuitry 18 may assert control signals on the row lines 28 in display 14. For example, driver circuitry 18 may receive clock signals and other control signals from display driver integrated circuit 16 and may, in response to the received signals, assert control signals in each row of display pixels 22. Rows of display pixels 22 may be processed in sequence, with processing for each frame of image data starting at the top of the array of display pixels and ending at the bottom of the array (as an example). While the scan lines in a row are being asserted, the control signals and data signals that are provided to column driver circuitry 20 by circuitry 16 direct circuitry 20 to demultiplex and drive associated data signals D onto data lines 26 so that the display pixels in the row will be programmed with the display data appearing on the data lines D. The display pixels can then display the loaded display data.
Column driver circuitry 20 may output data line signals that contain grayscale information for multiple color channels, such as red, green, and blue channels. Demultiplexing circuitry 54 may demultiplex this data line signal into respective R, G, and B data line signals on respective data lines 48. As shown in the example of
Optional loading circuits 66 may be implemented using one or more discrete components (e.g., capacitors, inductors, and resistors) that are interposed within lines 54 or may be implemented in a distributed fashion using some or all of the structures that form lines 54. Optional loading circuits 66 and/or circuitry in column driver circuitry 20 (e.g., circuit 58) may be used to control the shape of the demultiplexing control signals R, G, and B. Signal shaping techniques such as these may be used to smooth display control signal pulses such as the demultiplexer control signal pulses and thereby reduce harmonic signal production and radio-frequency interference.
In an organic light-emitting diode display such as display 14, each display pixel contains a respective organic light-emitting diode for emitting light. A drive transistor controls the amount of light output from the organic light-emitting diode. Control circuitry in the display pixel is configured to perform threshold voltage compensation operations so that the strength of the output signal from the organic light-emitting diode is proportional to the size of the data signal loaded into the display pixel while being independent of the threshold voltage of the drive transistor.
The current state of the art display pixel having threshold voltage compensation capabilities includes four thin-film transistors and an organic light-emitting diode having an associated capacitance COLED. The four transistors are controlled by two scan control signals and a single emission control signal. The resulting output signal produced by this type of display pixel may be independent of the threshold voltage of the drive transistor but may still be sensitive to the capacitance COLED of the light-emitting diode, which can cause the brightness of the display to vary over time. Other issues associated with such type of display pixels include reduced maximum brightness of the display, high power consumption, and lateral leakage between neighboring pixels. It may therefore be desirable to provide improved display pixels that address these issues.
A schematic diagram of an illustrative organic light-emitting diode display pixel 22 in display 14 in accordance with an embodiment of the present invention is shown in
As shown in
Terminal 308 is used to supply an initialization voltage Vini (e.g., a negative voltage such as −1 V or −2 V or other suitable voltage) to assist in turning off diode 304 when diode 304 is not in use. Control signals from display driver circuitry such as row driver circuitry 18 of
In the example of
Transistor T3, capacitor C1, and transistor T6 may be coupled in series between the first source-drain terminal of drive transistor T2 and power supply terminal 308. Transistor T3 may have a first source-drain terminal that is coupled to the first source-drain terminal of transistor T2, a gate terminal that receives the second scan control signal SCAN2, and a second source-drain terminal that is coupled to the gate of transistor T2. Storage capacitor C1 may have a first terminal that is coupled to the gate of transistor T2 and a second terminal that is coupled to the source terminal of transistor T5. Transistor T6 may have a drain terminal that is coupled to the source terminal of transistor T5 (and to the p-type terminal of diode 304), a gate terminal that receives the second scan control signal SCAN2, and a source terminal that receives voltage Vini via terminal 308. Transistor T1 may have a drain terminal that is coupled to the second source-drain terminal of drive transistor T2, a gate terminal that receives first scan control signal SCAN1, and a source terminal that receives data line signal DL via terminal 310. Connected in this way, signal EM1 may be asserted to enable transistor T4; signal EM2 may be asserted to activate transistor T5; signal SCAN1 may be asserted to turn on transistor T1; and signal SCAN2 may be asserted to switch into use transistors T3 and T6.
Each display pixel such as display pixel 22 of
During reset (e.g., from time t1 to t2), control signal SCAN2 is driven high to turn on transistors T3 and T6, control signal EM2 is driven low to turn off transistor T5, control signal SCAN1 remains low to keep transistor T1 in the off state, and control signal EM1 remains high to keep transistor T4 in the on state. During this time, the demultiplexing control signals R, G, and B may all be asserted to pass a maximum reference voltage level onto the corresponding data lines RDL, GDL, and BDL (see,
Under these conditions, transistor T4 will pull the first source-drain terminal of drive transistor T2 up to power supply voltage ELVDD. Transistor T3 will also pull the gate terminal of transistor T2 up to ELVDD. This in turn enables transistor T2 to pull its second source-drain terminal up to at least (ELVDD−Vth2), where Vth2 represents the threshold voltage of drive transistor T2. Transistor T5 is off, so organic light-emitting diode 304 is isolated from drive transistor T2 and does not emit light 306. To ensure that organic light-emitting diode 304 is turned off and does not emit light, initialization voltage Vini (sometimes referred to as a “suspension” voltage) is applied to the p-type terminal (or anode) of diode 304 to reverse bias diode 304. This reverse bias may be applied to diode 304 during the reset phase and the data loading and compensation phase.
After reset operations are complete, the data input and threshold voltage compensation operations are performed. During this time (e.g., from time t2 to t3), control signal SCAN1 may be driven high to turn on transistor T1, control signal EM1 may be driven low to turn off transistor T4 (while signal SCAN2 remains high and while signal EM2 remains low). At time t2, the demultiplexing control signals may be sequentially asserted to load red data signals, green data signals, and blue data signals into respective display pixels 22 via transistor T1. Under these conditions, transistor T1 will drive the second source-drain terminal of transistor T2 to data signal level Vdata while the first source-drain terminal and the gate terminal of transistor T2 are both pulled down to (Vdata+Vth2).
After data input and threshold voltage compensation operations, emission operations are performed. During emission operations, control signal SCAN2 is driven low to turn off transistors T3 and T6, control signal EM2 is driven high to turn on transistor T5, control signal SCANT is driven low to turn off transistor T1, and control signal EM1 is driven back high to activate transistor T4. With transistor T6 turned off, the p-type terminal of diode 304 is isolated from voltage Vini. With transistor T1 turned off, data terminal 310 is isolated from the drive transistor. Because transistors T4, T2, and T5 are all turned on, a current IOLED may flow from power supply terminal 300 via these series connected transistors and diode 304 to power supply terminal 304, thereby causing diode 304 to produce a corresponding amount of light 306. This may result in a voltage drop VOLED across diode 306.
Under these conditions, the first source-drain terminal of drive transistor T2 may be driven to ELVDD, and the source terminal of transistor T5 may be held at (VOLED+ELVSS), which will also pull the second source-drain terminal of transistor T2 down to (VOLED+ELVSS). At time 3, the voltage at the p-type terminal of diode 304 may therefore change from Vini to (VOLED+ELVSS), which results in a net voltage change of (VOLED+ELVSS−Vini). Since the voltage across capacitor C1 cannot change instantaneously, this voltage change at the second terminal of capacitor C1 will cause the first terminal of capacitor C1 to change from (Vdata+Vth2) to [(Vdata+Vth2)+(VOLED+ELVSS−Vini)]. Since the first terminal of capacitor C1 is shorted to the gate terminal of drive transistor T2, the gate terminal of transistor T2 will therefore exhibit a voltage level of [(Vdata+Vth2)+(VOLED+ELVSS−Vini)] during emission.
With these voltages established at the various terminals of drive transistor T2, the drive current IOLED that flows through transistor T2 is given by IOLED=k*(VGS−Vth2)2. Substituting VGS with the difference between the voltage at the gate terminal of transistor T2 (which is equal to [(Vdata+Vth2)+(VOLED+ELVSS−Vini)], as described above) and the voltage at the second source-drain terminal of transistor T2 (which is equal to [ELVSS−VOLED], as described above), we obtain IOLED=k*[Vdata−Vini]2. As this equation demonstrates, the magnitude of drive current IOLED is proportional to the magnitude of data signal Vdata and is independent of threshold voltage Vth2 and VOLED (i.e., compensation operations have been successfully performed, so that light emission is neither affected by Vth variations nor by variations associated with diode 304). In other words, operating display pixel 22 in the way shown in
Simulations have been performed to evaluate the operation of the circuit of
Another suitable arrangement of a display pixel 22 that can be used in display 14 of
As shown in
Terminal 508 is used to supply an initialization voltage Vini (e.g., a negative voltage such as −1 V or −2 V or other suitable voltage) to assist in turning off diode 504 when diode 504 is not in use. Control signals from display driver circuitry such as row driver circuitry 18 of
In the example of
Transistor T3 may have a first source-drain terminal that is coupled to the first source-drain terminal of transistor T2, a gate terminal that receives scan control signal SCAN, and a second source-drain terminal that is coupled to the gate of transistor T2. Storage capacitor C1 may have a first terminal that is coupled to the gate of transistor T2 and a second terminal that is coupled to the source terminal of transistor T5. Transistor T6 may have a drain terminal that is coupled to the source terminal of transistor T5 (and to the anode of diode 504), a gate terminal that receives the scan control signal SCAN, and a source terminal that receives voltage Vini via terminal 508. Transistor T1 may have a drain terminal that is coupled to the second source-drain terminal of drive transistor T2, a gate terminal that receives scan control signal SCAN, and a source terminal that receives data line signal DL via terminal 510. Connected in this way, signal EM[n] may be asserted to enable transistor T4; signal EM[n−1] may be asserted to activate transistor T5; and signal SCAN may be asserted to turn on transistor T1, T3, and T6 simultaneously.
Each display pixel such as display pixel 22 of
During reset (e.g., from time t1 to t2), control signal SCAN is driven high to turn on transistors T1, T3 and T6, control signal EM[n−1] remains low to keep transistor T5 in the off state, and control signal EM[n] remains high to keep transistor T4 in the on state. During this time, the demultiplexing control signals R, G, and B may all be asserted to pass a maximum reference voltage level onto the corresponding data lines RDL, GDL, and BDL (see,
Transistor T5 is off, so organic light-emitting diode 504 is isolated from drive transistor T2 and does not emit light 506. To ensure that organic light-emitting diode 504 is turned off and does not emit light, initialization voltage Vini is applied to the anode of diode 504 to reverse bias diode 504. This reverse bias may be applied to diode 504 during the reset phase and the data loading and compensation phase.
After reset operations are complete, the data input and threshold voltage compensation operations are performed. During this time (e.g., from time t2 to t3), control signal SCAN may remain high to keep transistors T1, T3, and T6 in the on state, control signal EM[n−1] may remain low to keep transistor T5 in the off state, whereas control signal EM[n] may be driven low to deactivate transistor T4. At time t2, the demultiplexing control signals may be sequentially asserted to load red data signals, green data signals, and blue data signals into respective display pixels 22 via transistor T1. Under these conditions, transistor T1 will drive the second source-drain terminal of transistor T2 to data signal level Vdata while the first source-drain terminal and the gate terminal of transistor T2 are both pulled down to (Vdata+Vth2).
After data input and threshold voltage compensation operations, data may be held during a holding phase from time t3 to t5. In particular, control signal SCAN may be driven low at time t3 to turn off transistors T1, T3, and T6, and control signal EM[n−1] may be driven high at time t4 to turn on transistor T5.
At the end of the holding phase, emission operations are performed. During emission operations, control signal EM[n] may be driven high (i.e., at time t5) to turn on transistor T4. With transistor T6 turned off, the anode of diode 504 is isolated from voltage Vini. With transistor T1 turned off, data terminal 510 is isolated from the drive transistor T2. Because transistors T4, T2, and T5 are all turned on, a current IOLED may flow from power supply terminal 500 via these series connected transistors and diode 504 to power supply terminal 504, thereby causing diode 504 to produce a corresponding amount of light 506. Similar to the pixel arrangement of
Simulations have been performed to evaluate the operation of the circuit of
The foregoing is merely illustrative and various modifications can be made by those skilled in the art without departing from the scope and spirit of the described embodiments. The foregoing embodiments may be implemented individually or in any combination.
