Patent Grant
10223969
This application claims the benefit of Korea Patent Application No. 10-2015-0138251 filed on Sep. 30, 2015, the entire contents of which is incorporated herein by reference for all purposes as if fully set forth herein.
Field of Technology
The present disclosure relates to an organic light emitting diode (OLED) display.
Discussion of the Related Art
A flat panel display (FPD) is widely used for a desktop monitor, a laptop, a personal distal assistant (PDA), and any other mobile computer or mobile phone terminal, because the FPD is effective in achieving miniaturization and lightness. The FPD includes a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), and an organic light emitting diode (OLED) display.
The OLED display has a fast response speed and a wide viewing angle, and is able to produce brightness with high luminous efficiency. Generally, an OLED display uses a scan transistor, which is turned on by a scan signal, to apply a data voltage to a gate electrode of a driving transistor, and enables an OLED to emit light using the data voltage supplied the driving transistor. In addition, the OLED display uses an emission control signal to perform switching of the driving transistor and a high-potential voltage input terminal.
Driving circuits generating a scan signal and an emission control signal may be formed in a bezel area of a display panel by using a gate in panel (GIP) scheme. Recently, methods for reducing the bezel area have been studied to satisfy user demands. However, it is difficult to reduce the size of the bezel area because of a GIP circuit.
An organic light emitting diode (OLED) display according to the present disclosure includes a plurality of pixels respectively arranged along n number of horizontal lines in a first direction where (n indicates is a natural number), each of the plurality of pixels and comprising a first scan transistor connected to a gate electrode of a driving transistor, a second scan transistor connected to a source first electrode of the driving transistor, and an emission control transistor connected to a drain second electrode of the driving transistor; n number of first scan signal stages that output first scan signals sequentially to the first scan transistors arranged along the n number of lines; and
number of emission control signal stages that output emission control signals that have a same phase, a same emission control signal outputted to emission control transistors of two adjacent lines.
In another embodiment an organic light emitting diode (OLED) display comprises: a first row of pixels and a second row of pixels that is adjacent to the first row of pixels, each pixel comprising an OLED, a driving transistor connected to the OLED, and an emission control transistor connected to the driving transistor; and an emission control stage connected to both the first row of pixels and the second row of pixels, the emission control stage outputting an emission control signal to a gate electrode of each emission control transistor included in both the first row of pixels and the second row of pixels.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:
Hereinafter, the embodiments disclosed in the present specification will be described in detail with reference to the accompanying drawings, and the same or similar elements are denoted by the same reference numerals even though they are depicted in different drawings and redundant descriptions thereof will be omitted.
Referring to
The display panel 100 includes a display portion 100A in which the pixels P are arranged to display an image, and a non-display portion 100B in which a shift register 140 is arranged and which does not display an image.
A plurality of pixels P is included, and an image is displayed based on gray scales displayed by the pixels P. The pixels P are arranged along the first horizontal line HL1 to a n-the horizontal line HL[n].
Each of the pixels P is connected to an initialization line INL and a data lines which are arranged along a column line, and connected to a first scan line SL1, a second scan line SL2, and an emission control signal line EML which are arranged along a horizontal line HL. In addition, each of the pixels P includes an OLED, a driving transistor DT, a first scan transistor ST1, a second scan transistor ST2, an emission control transistor ET, a storage capacitor Cst, and a sub-capacitor Csub. Each of the transistors DT, ST1, ST2, and ET may be implemented as a thin film transistor (TFT) including a polycrystalline semiconductor layer according to one embodiment. However, aspects of the present disclosure are not limited thereto, and the semiconductor layer of the TFT may be formed of an amorphous silicon semiconductor or an oxide semiconductor.
The timing controller 110 is configured to control operation timing of the data driver 120, the gate driver. To this end, the timing controller 110 realigns externally received digital video data RGB to fit the resolution of the display panel 100, and supplies the realigned digital video data RGB to the data driver 120. In addition, the timing controller 110 generates a control signal DDC for controlling operation timing of the data driver 120, and a gate control signal GDC for controlling operation timing of the gate driver, based on timing signals such as a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a dot clock signal DCLK, and a data enable signal DE.
The data driver 120 is configured to drive data lines DL. To this end, the data driver 120 converts digital video data RGB received from the timing controller 110 into an analog data voltage based on the data control signal DDC, and supplies the analog data voltage to the data lines DL. In addition, the data driver 120 supplies an initialization voltage Vini to the pixels P through an initialization line INL.
The gate driver includes a level shifter 130 and a shift register 140. The level shifter 130 is formed as an integrated circuit (IC) on a printed circuit board (PCB) (now shown) connected to the display panel 100. The shift register 140 is formed on the non-display portion 100B of the display panel 100 by using a gate in panel (GIP) scheme.
The level shifter 130 performs level shifting of the clock signals CLK and a start signal VST under the control of the timing control, and supplies the level-shifted clock signals CLK and the level-shifted start signal VST. The shift register 140 is formed as a combination of multiple TFTs in the non-display portion 100B of the display panel 100 by using the GIP scheme. The shift register 140 is comprised of stages which shift scan signals and output the shifted scan signal in response to the clock signals CLK and the start signal VST. The stages included in the shift register 140 output first scan signals SCAN1, second scan signals SCAN2, and emission control signal EM.
Referring to
The OLED emits light by a driving current supplied from the driving transistor DT. Multiple organic compound layers are formed between an anode electrode and a cathode electrode of the OLED. The organic compound layers include hole injection layers (HIL), hole transport layers (HTL), emission layers (EML), electron transport layers (ETL), and electron injection layers (EIL). The anode electrode of the OLED is connected to a source electrode of the driving transistor DT, and the cathode electrode of the OLED is connected to GVSS.
The driving transistor DT uses its gate-source voltage to control a driving current which is to be applied to the OLED. To this end, the driving transistor DT includes a gate electrode connected to an input terminal of a data voltage Vdata, a drain voltage connected to an input terminal of a driving voltage VDD, and a source electrode connected to a low-potential driving voltage VSS.
In response to a first scan signal, the first scan transistor ST1 applies a reference voltage Vref or a data voltage Vdata, which is received from the data line DL, to the gate electrode of the driving transistor DT. To this end, the first scan transistor ST1 includes a gate electrode connected to the first scan line SL1, a drain electrode connected to the data line DL, and a source electrode connected to a first node n1.
In response to a second scan signal SCAN2, the second scan transistor ST2 provides an initialization voltage Vini, which is received from the initialization line INL, to a second node n2. To this end, the second scan transistor ST2 includes a gate electrode connected to the second scan line SL2, a drain electrode connected to the initialization line INL, and a source electrode connected to the second node n2.
In response to an emission control signal, the emission control transistor ET controls a current path between the input terminal of the driving voltage VDD and the driving transistor DT. To this end, the emission control transistor ET includes a gate electrode connected to the emission control signal line EML, a drain electrode connected to the input terminal of the driving voltage VDD, and a source electrode connected to the driving transistor DT.
The storage capacitor Cst maintains the data voltage Vdata, which is received from the data line DL, for one frame, so that the driving transistor DT can maintain a constant voltage. To this end, the storage capacitor Cst is connected to the gate electrode and the source electrode of the driving transistor DT.
The sub-capacitor Csub is connected in series to the storage capacitor Cst at the second node n2 so as to adjust efficiency of the driving voltage Vdata.
Operation of the pixel P in the above-described structure is described in the following.
In the drawings, one horizontal period H indicates a scanning period of pixels arranged along one horizontal line HL. The scanning period includes a sampling period and a data writing period.
Operation of each pixel P according to an embodiment of the present disclosure includes: an initialization period Ti for initializing the first node n1 and the second node n2 to a specific voltage; a sampling period Ts for detecting a threshold voltage of the driving transistor DT; a data writing period Tw for writing a data voltage; and an emission period Te for emitting light by compensating for a driving current applied to an OLED, regardless of a threshold voltage.
Referring to
When the second scan signal SCAN2 is at a turn-on voltage level, the second scan transistor ST2 applies an initialization voltage Vini, which is received from the initialization line INL, to the second node n2. As a result, a source voltage Vs of the driving transistor DT acts as the initialization voltage Vini. When the first scan signal SCAN1 is at the turn-on voltage level, the first scan transistor ST1 applies a reference voltage Vref, which is received from the data line DL, to the first node n1. As a result, a gate voltage Vg of the driving transistor DT acts as the reference voltage Vref.
The initialization voltage Vini is applied to the second node n2 in the initialization period T2 in an effort to initialize a concerned pixel to a specific level. In this case, the initialization voltage Vini is set to be smaller than an operation voltage of the OLED to prevent the OLED from emitting light.
Referring to
In response to the first scan signal SCAN1, the first scan transistor ST1 applies the reference voltage Vref, which is received from the data line DL, to the first node n1. In response to the emission control signal EM, the emission control transistor ET applies a driving voltage VDD to the driving transistor DT.
When the second node n2 is floating as a result of the second scan transistor ST2 being turned off, a voltage of the second node n2 gradually increases due to a current flowing from the drain electrode of the driving transistor DT to the source electrode thereof. In this case, the first node n1 remains at the reference voltage Vref, so the second node n2 is saturated with a voltage which corresponds to difference between the reference voltage Vref and the threshold voltage Vth of the driving transistor DT. That is, in the sampling period Ts, a gate-source potential difference of the driving transistor DT is equal to that of the threshold voltage Vth.
Referring to
In response to the first scan signal SCAN1, the first scan transistor ST1 supplies a data voltage Vdata, which is received from the data line DL, to the first node n1. At this point, a voltage of the second node n2 in a floating state rises or falls because coupling effects occur due to the ratio of capacitance between the storage capacitor Cst to a sub-capacitor C1.
Referring to
In the emission period Te, the data voltage Vdata stored in the storage capacitor Cst is supplied to the OLED, so the OLED emits light with brightness which is in proportion to the data voltage Vdata. At this point, current flows in the driving transistor DT by the voltages of the first and second nodes n1 and n2 determined in the data writing period Tw, so a desired current is supplied to the OLED. As a result, the OLED is able to control brightness using the data voltage Vdata.
Referring to
The j-th first scan signal stage SCAN1D[j] generates a j-th first scan signal SCAN1[j], and applies the j-th first scan signal SCAN1 to a j-th first scan line SL1[j].
The j-th second scan signal stage SCAN2D[j] generates a j-th second scan signal SCAN2[j], and applies the j-th second scan signal SCAN2[j] to a j-th second scan line SL2[j].
The (j+1)-th first scan signal stage SCAN1D[j+1] generates a (j+1)-th first scan signal SCAN1[j+1], and applies the (j+1)-th first scan signal SCAN1[j+1] to a (j+1)-th first scan line SL1[j+1].
The (j+1)-th second scan signal stage SCAN2D[j+1] generates a (j+1)-th second scan signal SCAN2[j+1], and applies the (j+1)-th second scan signal SCAN2[j+1] to a (j+1)-th second scan line SL2[j+1].
The j-th emission control signal stage EMD[j] generates a j-th emission control signal EM[j], and applies the j-th emission control signal EM[j] to a j-th emission control signal line EML[j] connected to pixels Pj arranged along the j-th horizontal line and a (j+1)-th emission control signal line EML[j+1] connected to pixels P[j+1] arranged along the (j+1)-th horizontal line. The j-th emission control signal stage EMD[j] is used as a clock signal for controlling operation timing of each transistor by receiving a j-th first scan signal SCAN1, a j-th second scan signal SCAN2, and a (j+1)-th first scan signal SCAN1.
Pixels arranged along a pair of two adjacent horizontal lines are driven by the same emission control signal, so it is possible to drive pixels arranged along n number of horizontal lines with n/2 number of emission control signal stages. That is, it is possible to reduce the entire area of the shift register 140, and thus, reduce a bezel area of the non-display portion 100B.
Referring to
Similarly, instead of the first emission clock ECLK1, the third emission clock ECLK3, and the fifth emission clock ECLK5, the j-th emission control signal stage EMD[j] receives a j-th emission clock ECLKj, a (j+2)-th emission clock ECLK[j+2], and a (j+4)-th emission clock ECLK[j+4].
The emission clock ECLK comprises seven phases, and each clock signal is continuous. Thus, for a clock signal having (j+k) which is greater than 7 (k indicates a natural number satisfying the condition of 1<k<7), a clock signal with an ordinal number obtained by subtracting 7 from (j+k) is used. For example, a (j+4)-th gate clock GCLK[j+4] in the fifth emission control signal stage corresponds to a second gate clock GCLK2.
The first transistor T1 includes a first electrode connected to an input terminal of the high-potential voltage GVDD, a second electrode connected to a first electrode of a second transistor T2, and a gate electrode connected to an input terminal of the first emission clock ECLK1. The second transistor T2 includes the first electrode connected to the second electrode of the first transistor T1, a second electrode connected to a Q node (Q), and a gate electrode connected to an input terminal of the start signal EMVST. When the emission clock ECLK1 and the start signal EMVST are synchronized, the first and second transistors T1 and T2 are all turned on, and accordingly, the Q node (Q) is charged to the high-potential voltage GVDD provided through the first and second transistors T1 and T2.
A first low-potential trigger transistor T5 include a first electrode connected to an output terminal of the first instance of the first scan signal SCAN1[1], a second electrode connected to a QB node (QB), and a gate electrode connected to the input terminal of the fifth emission clock ECLK5. Accordingly, when the fifth emission clock ECLK5 and the first instance of the first scan signal SCAN1 [1] are synchronized, the first low-potential trigger transistor T5 charges the QB node (QB).
A second low-potential trigger transistor T3 includes a first electrode connected to an input terminal of the emission reset signal ERST, a second electrode connected to the QB node (QB), and a gate electrode connected to an output terminal of the second instance of the first scan signal SCAN1[2]. Accordingly, when the emission reset signal ERST and the second first scan signal SCAN1 [2] are synchronized, the second low-potential trigger transistor T3 charges the QB node (QB).
A third low-potential trigger transistor T11 includes a first electrode connected to an input terminal of the high-potential voltage GVDD, a second electrode connected to the QB node (QB), and a gate electrode connected to the output terminal of the first instance of the second scan signal SCAN2[1]. Accordingly, when the first instance of the second scan signal SCAN2[1] is applied, the third low-potential trigger transistor T11 charges the QB node (QB).
A fourth transistor T4 includes a first electrode connected to a high-potential voltage GVDD, a second electrode connected to a second electrode of a ninth transistor T9 and a gate electrode connected to an emission control signal output terminal EMO(1).
The sixth transistor T6 includes a first electrode connected to the Q node (Q), a second electrode connected to an input terminal of the low-potential voltage GVSS, and a gate electrode connected to the QB node (QB). Accordingly, when the QB node (QB) is charged, the sixth transistor T6 discharges the Q node (Q) to the low-potential voltage GVSS.
A seventh transistor T7 includes a first electrode connected to the QB node (QB), a second electrode connected to the low-potential voltage GVSS, a gate electrode connected to an input terminal of the third emission clock ECLK3. Accordingly, the seventh transistor T7 discharges the QB node (QB) in response to the third emission clock ECLK3.
A pull-up transistor T8 includes a first electrode connected to the high-potential voltage GVDD, a second electrode connected to an emission control signal output terminal EMO(1), a gate electrode connected to the Q node (Q). Accordingly, when the Q node (Q) is charged, the pull-up transistor T8 is turned on and subsequently generates a first emission control signal EM1 at the level of the high-potential voltage GVDD to the emission control signal output terminal EMO1.
Pull-down transistors T9 and T10 are connected in series to each other. Each of the pull-down transistors T9 and T10 includes a gate electrode connected to the QB node (QB). A first electrode of the ninth transistor T9 is connected to the emission control signal output terminal EMO(1), and a second electrode of the tenth transistor T10 is connected to the low-potential voltage GVSS. Accordingly, the pull-down transistors T9 and T10 discharges the potential of the emission control signal output terminal EMO(1) to the low-potential voltage GVSS in response to the potential of the QB node (QB).
During a first initialization period Ti1, the first instance of the first scan signal SCAN1[1] and a fifth emission clock ECLK5 are synchronized. As a result, the first low-potential trigger transistor T5 is turned on, thereby charging the QB node (QB) to a voltage of the first instance of the first scan signal SCAN1[1]. The pull-down transistors T9 and T10 are turned on as a result of the QB node (QB) being charged, and the emission control signal output terminal EMO(1) is discharged to the low-potential voltage GVSS. As a result, an emission control signal, which was output at a high-level voltage in an emission period of a previous frame, is reversed to low level at the beginning of the first initialization period Ti1.
In the sampling period Ts, a first emission clock ECLK1 and a start signal EMVST are synchronized. The first transistor T1 is turned on by the first emission clock ECLK1, and the second transistor T2 is turned on by the start signal EMVST. As the first and second transistors T1 and T2 are turned on at the same time, the Q node (Q) and a boosting capacitor C are charged to the high-potential voltage GVDD bypassing the first and second transistors T1 and T2. The pull-up transistor T8 is turned on as a result of the Q node (Q) being charged, and the first emission control signal EM1 at the level of the high-potential voltage GVDD is output to the emission control signal output terminal EMO1.
In the data writing period Tw, the first scan signal SCAN1 of the second stage and a reset signal ERST are synchronized. As a result, the second low-potential trigger transistor T3 is turned on, thereby charging the QB node (QB) using the reset signal ERST. The pull-down transistors T9 and T10 are turned on as a result of the QB node (QB) being charged, and the emission control signal output terminal EMO(1) is discharged to the low-potential voltage GVSS.
At the beginning of the emission period Te, a first emission clock ECLK1 and the start signal EMVST are synchronized. The first transistor T1 is turned on by the first emission clock ECLK1, and the second transistor T2 is turned on by the start signal EMVST. As the first and second transistors T1 and T2 are turned on at the same time, the Q node (Q) and the boosting capacitor C are charged to the high-potential voltage GVDD bypassing the first and second transistors T1 and T2. The pull-up transistor T8 is turned on as a result of the Q node (Q) being charged, and the first emission control signal EM1 at the level of the high-potential voltage GVDD is output to the emission control signal output terminal EMO(1).
In the emission period Te, the seventh transistor T7 is turned on at a specific interval in response to a third emission clock ECLK3. In a turn-on state, the seventh transistor T7 maintains the QB node (QB) at low-potential voltage in order to restrain the pull-down transistors T9 and T10 from turning on. That is, the seventh transistor T7 enables the first emission control signal EM1 to be stably output through the emission control signal output terminal EMO(1) in the emission period Te.
In the emission period Te, the eleventh transistor T11 is turned on by the first instance of the second scan signal SCAN2[1]. When the eleventh transistor T11 is turned on, the QB node (QB) is charged, thereby rendering the pull-down transistors T9 and T10 turned on. The pull-down transistors T9 and T10 are turned on, thereby discharging the voltage of the emission control signal output terminal EMO(1). That is, the first instance of the second scan signal SCAN2[1] applied in the emission period Te stops outputting of the first emission control signal EM1. The voltage of the emission control signal output terminal EMO(1), which is discharged by the first instance of the second scan signal SCAN2[1], is maintained to be a low-potential voltage until the first emission clock ECLK1 and the start signal EMVST are synchronized.
As such, the emission period Te is divided into a period of outputting the emission control signal EM and a period of suppressing the emission control signal EM, so it is possible to drive pixels at duty cycles.
The first emission control signal EM1 according to the present disclosure is applied at the same time not just to pixels arranged along the first horizontal line HL1, but to pixels arranged along the second horizontal line HL2. Thus, the first emission control signal EM1 has to satisfy driving requirements not just of the pixels arranged along the first horizontal line HL1, but of the pixels arranged along the second horizontal line HL2. The second data writing period Tw2 of the pixels arranged along the second horizontal line corresponds to a specific part of the emission period Te of the pixels arranged along the first horizontal line HL1. In the data writing period Tw of the pixels arranged along the second horizontal line HL2, the second first scan signal SCAN1[2] and the reset signal ERST turn off the second low-potential trigger transistor T3. That is, the first emission control signal EM1 may drive not just the pixels arranged along the first horizontal line HL1, but the pixels arranged along the second horizontal line HL2 at the same time.
In the OLED display according to the present disclosure, an emission control signal stage realized as one stage supplies an emission control signal to pixels arranged along a pair of horizontal lines, so it is possible to reduce the number of stages of the emission control signal stage that is configured to drive the entire display panel. As a result, a bezel area in which the emission control signal stage is disposed may be reduced.
Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2015-0138251 | Sep 2015 | KR | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20130314308 | Hsu | Nov 2013 | A1 |
| 20140111557 | Omata et al. | Apr 2014 | A1 |
| Number | Date | Country |
|---|---|---|
| 103150992 | Jun 2013 | CN |
| Entry |
|---|
| European Extended Search Report, European Application No. 16191065.8, dated Jan. 30, 2017, 11 pages. |
| Number | Date | Country | |
|---|---|---|---|
| 20170092199 A1 | Mar 2017 | US |
