Korean Patent Application No. 10-2015-0010026, filed on Jan. 21, 2015, and entitled, “Organic Light-Emitting Display Apparatus,” is incorporated by reference herein in its entirety.
1. Field
One or more embodiments herein relate to organic light-emitting display apparatus.
2. Description of the Related Art
A variety of flat panel displays have been developed. Examples include liquid crystal displays, field emission displays, plasma display panels, and organic light-emitting displays. These displays are lighter and larger than cathode ray tube displays.
In an organic light-emitting display, pixels emit light when electrons and holes combine in an emission layer that includes organic compounds. This type of display has fast response time, low power consumption, and excellent brightness, color purity, and driving voltage characteristics.
In operation, light is emitted from color pixels to form an image. Each pixel emits light with a brightness that is based on a data voltage received by a pixel circuit. The pixel circuit includes a plurality of transistors and one or more storage capacitors for controlling driving current supplied to an organic light emitting diode (OLED) of the pixel.
In accordance with one or more embodiments, an organic light-emitting display apparatus includes a plurality of pixel circuits, each of the pixel circuits to receive a data signal and to output a driving current to an output node based on the data signal, the pixel circuits to sequentially operate in an anode initialization period, a threshold voltage compensation period, a data write period, and an emission period; and a plurality of organic light-emitting diodes to emit light based on the driving currents transferred through the output nodes of respective ones of the pixel circuits, wherein: the pixel circuits are in multiple rows and multiple columns, each of the pixel circuits includes an anode initialization transistor to output an initialization voltage to the output node based on a first control signal received through a first control line, and the first control line connected to the anode initialization transistor of a pixel circuit in an odd row is different from the first control line connected to the anode initialization transistor of a pixel circuit in an even row.
Each of the pixel circuits may include a capacitor, a driving transistor, a switching transistor, and an emission control transistor, the capacitor has a first electrode connected to a first node and a second electrode connected to the output node, the driving transistor has a gate electrode connected to the first node, a first electrode connected to a second electrode of the emission control transistor, and a second electrode connected to the output node, the switching transistor has a gate electrode connected to a scan line, a first electrode connected to a data line, and a second electrode connected to the first node, and the emission control transistor has a gate electrode connected to a second control line and a first electrode connected to a first power supply.
A second control line connected to an emission control transistor of the pixel circuit in the odd row may be different from a second control line connected to an emission control transistor of the pixel circuit in the even row. The anode initialization transistor may have a first electrode connected to the data line and a second electrode connected to the output node, and the anode initialization transistor may output a voltage from the data line to the output node based on the first control signal.
The data write period of the pixel circuit in the odd row may overlap the emission period of the pixel circuit in the even row. The data write period of the pixel circuit in the even row may overlap the emission period of the pixel circuit in the odd row. The anode initialization transistor may output the initialization voltage to the output node during the anode initialization period based on the first control signal.
During the threshold voltage compensation period, the emission control transistor may be turned on based on a second control signal received through the second control line and may output a first voltage received through the first power supply to the first electrode of the driving transistor, and the switching transistor may output a reference voltage to the first node based on a scan signal received through the scan line.
The reference voltage may be set such that a level of a voltage applied to the output node is lower than a level of a turn-on voltage of the organic light-emitting diode. A level of the initialization voltage may be lower than a level of a turn-on voltage of the organic light-emitting diode.
In accordance with one or more other embodiments, an organic light-emitting display apparatus includes a plurality of pixel circuits, each of the pixel circuits to receive a data signal and to output a driving current to an output node based on the data signal, the pixel circuits to sequentially operate in an anode initialization period, a threshold voltage compensation period, a data write period, and an emission period; and a plurality of organic light-emitting diodes to emit light based on the driving currents transferred through the output nodes of respective ones of the pixel circuits, wherein: the pixel circuits are in multiple rows and multiple columns, each of the pixel circuits includes an anode initialization transistor having a first electrode connected to an initialization voltage line, a second electrode connected to the output node, and a gate electrode connected to a first control line, the anode initialization transistor to output an initialization voltage from the initialization voltage line to the output node based on a first control signal received through the first control line, and a first control line connected to an anode initialization transistor of a pixel circuit in an odd row is different from a first control line connected to an anode initialization transistor of a pixel circuit in an even row.
The data write period of the pixel circuit in the odd row may overlap the emission period of the pixel circuit in the even row, and the data write period of the pixel circuit in the even row may overlap the emission period of the pixel circuit in the odd row. An initialization voltage may be applied to the initialization voltage line during the anode initialization period, and a level of the data signal may be substantially equal to a level of a reference voltage during the threshold voltage compensation period. The reference voltage may be set such that a level of a voltage applied to the output node is lower than a level of a turn-on voltage of the organic light-emitting diode. A level of the initialization voltage may be lower than a level of a turn-on voltage of the organic light-emitting diode.
In accordance with one or more other embodiments, a display includes a first pixel circuit to output a driving current to a first light emitter; and a second pixel circuit to output a driving current to a second light emitter; wherein the first pixel circuit is in an odd row and the second pixel circuit is in an even row, each of the first and second pixel circuits including an anode initialization transistor to output an initialization voltage to an output node based on a first control signal from a first control line, the first control line connected to the first pixel circuit different from the first control line connected to the second pixel circuit.
Each of the first and second pixel circuits may operate in an anode initialization period, a threshold voltage compensation period, a data write period, and an emission period. The anode initialization transistor of each of the first and second pixel circuits may output the initialization voltage during the anode initialization period. A level of the initialization voltage may be lower than a level of a turn-on voltage of the light emitter in each of the first and second pixel circuits. A data write period of one of the first or second pixel circuits may overlap an emission period of the other of the first or second pixel circuits.
Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which:
Example embodiments are described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey exemplary implementations to those skilled in the art. The embodiments may be combined to form additional embodiments. Like reference numerals refer to like elements throughout.
The timing control unit 110 controls the data driving unit 120, the scan driving unit 130, and the control driving unit 140 based on control (e.g., synchronization) signals. The timing control unit 110 generates new data by changing bits of externally applied pixel data. The new data may compensate for mobility and a threshold voltage of a driving transistor in each of the pixels.
The data driving unit 120 generates data signals corresponding to data from the timing control unit 110. The data driving unit 120 supplies data signals to data lines in synchronization with scan signals from the scan driving unit 130 through scan lines during one frame time of a data write period. In addition, the data driving unit 120 supplies an initialization voltage and/or a reference voltage to the data lines. The reference voltage is used for initializing the gate electrode of the driving transistor and is set to a predetermined voltage. The initialization voltage is used for initializing anode electrodes of the OLEDs in the pixels and is set to a voltage at which the OLEDs do not emit light.
The scan driving unit 130 supplies scan signals to the scan lines. For example, as illustrated in
The control driving unit 140 supplies control signals to one or more control lines, which, for example, may be commonly connected to the pixels. The control driving unit 140 may supply an emission control signal to turn on emission control transistors in the pixels during the emission period.
The display panel 150 includes the pixels in regions partitioned by the scan lines and the data lines. The pixels charge data signals during the data write period and emit light based on the charged data signals during the emission period. The pixels control an amount of current flowing from the first power supply ELVDD through the OLED to the second power supply ELVSS based on the data signal.
In
Referring to
The pixels include pixels in odd rows and pixels in even rows. The scan lines may be between pixels in a first direction, and the data lines may be between pixels in a second direction. The first direction may be a horizontal direction and the second direction may be a vertical direction, or vice versa.
When apparatus 100 is a simultaneous emission type organic light-emitting display apparatus, a scan operation may be sequentially performed on the scan lines in the first direction. In the scan operation, data signals of an image frame are sequentially written to first pixels connected to the scan lines. The first pixels may be in the first row, e.g., pixel PX1 and subsequent pixels in the horizontal direction from the pixel PX1.
When writing of data to the first pixels has been completed, data is written to second pixels. The second pixels may be pixels in the second row, e.g., pixel PX2 and subsequent pixels in the horizontal direction from the pixel PX2.
The scan line connected to the first pixels may be different from the scan line connected to the second pixels. For example, the scan lines may include scan lines from the first scan line connected to the pixels in the first row (pixel PX1 and subsequent pixels in the horizontal direction from the pixel PX1) to the 2nth scan line connected to the pixels in the last row (pixel PX2n and subsequent pixels in the horizontal direction from the pixel PX2n).
In the pixel circuit, the driving transistor TRd has a gate electrode connected to a second electrode of the switching transistor TRs and a first electrode of the capacitor Cst. A first electrode of the driving transistor TRd is connected to a second electrode of the emission control transistor TRge, and a second electrode of the driving transistor TRd is connected to an anode electrode of the OLED.
The switching transistor TRs has a first electrode is connected to a data line DL, and a gate electrode of the switching transistor TRs is connected to a scan line SL.
The emission control transistor TRge has a first electrode connected to the first power supply ELVDD and a gate electrode connected to an emission control line and receives an emission control signal EC.
A second electrode of the capacitor Cst is connected to the anode electrode of the OLED and the second electrode of the driving transistor TRd through an output node. A cathode electrode of the OLED is connected to the second power supply ELVSS.
A voltage VG of the gate node corresponds to a voltage supplied from the data line DL through the switching transistor TRs. The switching transistor TRs is turned on based on the scan signal supplied from the scan line SL and outputs a voltage supplied from the data line DL to the gate node.
The capacitor Cst is charged with a voltage applied to the gate node. The voltage charged in the capacitor Cst corresponds to an anode voltage VA of the OLED.
The emission control transistor TRge is turned on based on the emission control signal EC from the emission control line and outputs a voltage of the first power supply ELVDD to the driving transistor TRd.
A current corresponding to the voltage of the first power supply ELVDD, a threshold voltage of the driving transistor TRd, and a data voltage supplied from the data line DL flows through the OLED, and the OLED emits light corresponding to the current.
The frame time may be divided into an anode initialization period, a threshold voltage (Vth) compensation period, a data write period, and an emission period. In the anode initialization period, the voltage of the first power supply ELVDD is reduced to a low voltage to initialize the anode voltage VA to a low voltage. At this time, the emission control signal EC is maintained at a high level so that the emission control transistor TRge maintains a turned-on state. The data signal has a level of a reference voltage Vref.
In the threshold voltage (Vth) compensation period, the data signal is set to a level of the reference voltage Vref so that a level of a gate node voltage VG becomes equal to the level of the reference voltage Vref. The anode voltage VA may therefore have a level of Vref-Vth, and thus the threshold voltage of the driving transistor TRd is compensated.
In the data write period, data voltages are sequentially written to the gate nodes of the pixels. At this time, data voltages are sequentially written to pixels respectively connected to the first to nth scan lines SL[1] to SL[n].
In the emission period, since the emission control signal EC has a high voltage, a high voltage of the first power supply ELVDD is supplied to the pixel circuit by the emission control transistor TRge, a current corresponding to the data voltage written to each pixel is supplied to the OLED through the driving transistor TRd, and the OLED emits light based on the magnitude of the current supplied through the driving transistor TRd.
Since such a simultaneous emission type pixel circuit has a sufficient threshold voltage compensation time, the threshold voltage compensation is facilitated and IR-drop compensation is achieved.
However, in the simultaneous emission type pixel circuit as illustrated in
When the emission current increases, IR-drop between ELVDD and ELVSS increases. Thus, the power supply voltage may be increased, thereby resulting in an increase in power consumption.
The pixel circuit PC_ODD in the odd row receives a data signal and outputs a driving current corresponding to the data signal to an output node VOUT_ODD. As described above with reference to
The pixel circuit PC_ODD further includes an anode initialization transistor TRIO in addition to the pixel circuit of
As in the pixel circuit of
The switching transistor TRSO has a gate electrode connected to a scan line SL[2n−1], a first electrode of the switching transistor TRSO is connected to the data line DL, and a second electrode of the switching transistor TRSO is connected to the first node V1_ODD. The emission control transistor TREMO has a gate electrode connected to a second control line CL2_ODD and a first electrode connected to the first power supply ELVDD. The gate electrode of the emission control transistor TREMO is connected to the second control line CL2_ODD and receives a second control signal.
The pixel circuit PC_EVEN in the even row receives a data signal and outputs a driving current corresponding to the data signal to an output node VOUT_EVEN. As described above with reference to
The pixel circuit PC_EVEN further includes an anode initialization transistor TRIE in addition to the pixel circuit of
As in the pixel circuit of
The driving transistor TRDE has a gate electrode connected to the first node V1_EVEN and a second electrode connected to the output node VOUT_EVEN.
The switching transistor TRSE has a gate electrode connected to a scan line SL[2n], a first electrode connected to the data line DL, and a second electrode connected to the first node V1_EVEN. A gate electrode of the emission control transistor TREME is connected to a second control signal CL2_EVEN and a first electrode of the emission control transistor TREME is connected to the first power supply ELVDD. The gate electrode of the emission control transistor TREME is connected to the second control line CL2_EVEN and receives a second control signal.
Referring to
The emission period of the pixel circuit PC_ODD in the odd row may not overlap the emission period of the pixel circuit PC_EVEN in the even row. For example, operation during one frame time is performed in the order of the odd anode initialization, an odd threshold voltage (Vth) compensation, an odd data writing, an odd emission, an even anode initialization, an even threshold voltage (Vth) compensation, an even data writing, and an even emission. However, the emission period of the pixel circuit PC_ODD in the odd row may overlap the emission period of the pixel circuit PC_EVEN in the even row.
Operation of the pixel circuit PC_ODD in the odd row will now be described.
During the anode initialization period, a voltage of a high level is applied to all the scan lines SL[1], SL[3], . . . , SL[2n−1] and all the switching transistors TRSO are turned on. At this time, the second control signal of a low level is applied through the second control line CL2_ODD and all the emission control transistors TREMO are turned off. The first control signal of a high level is applied through the first control line CL1_ODD and the anode initialization transistor TRIO is turned on. Since a low initialization voltage Vint is applied to the data line DL, the output node VOUT_ODD is initialized to the initialization voltage Vint. The initialization voltage Vint is set to a voltage lower than a turn-on voltage of the OLED so that the OLED does not emit light.
In the threshold voltage (Vth) compensation period, since the first control signal of the low level is applied through the first control line CL1_ODD, the anode initialization transistor TRIO is turned off. Since the second control signal of the high level is applied through the second control line CL2_ODD, the emission control transistor TREMO is turned off. Since the reference voltage Vref is applied to the data line DL, the voltage of the first node V1_ODD becomes the reference voltage Vref.
At this time, a voltage of Vref-Vth is applied to the output node VOUT_ODD by source follow. The voltage of Vref-Vth applied to the output node VOUT_ODD is set to a voltage lower than a turn-on voltage of the OLED so that the OLED does not emit light.
During the data write period, the control signal of the low level is applied to both the first control line CL1_ODD and the second control line CL2_ODD. Thus, both the anode initialization transistor TRIO and the emission control transistor TREMO are turned off.
The voltage of the high voltage is sequentially applied to the scan lines SL[1], SL[3], SL[2n−1], and data voltages Vdata are sequentially applied to the first node V1_ODD. At this time, due to a coupling between the capacitor CSTO and the capacitor COLEDO of the OLED, the voltage of the output node VOUT_ODD may be determined based on Equation (1).
During the emission period, the voltages of the low level are applied to all the scan lines SL[1], SL[3], . . . , SL[2n−1] and the first control line CL1_ODD, so that the switching transistor TRSO and the anode initialization transistor TRIO are turned off. The voltage of the high voltage are applied to the second control line CL2_ODD, so that the emission control transistor TREMO is turned on.
The current generated in the driving transistor TRDO is output to the OLEDs through the output node VOUT_ODD, so that the OLEDs in the odd row emit light.
The magnitude of current flowing through the OLED is proportional to (Vdata-VOUT_ODD-Vth)2. Therefore, the emission current, which compensates for the threshold voltage of the driving transistor TRDO, flows through the OLED, thereby exhibiting uniform brightness.
Operation of the pixel circuit PC_EVEN in the even row is substantially the same as the operation of the pixel circuit PC_ODD in the odd row. However, light is emitted in a current frame by data written in a previous frame operation.
In the simultaneous emission type pixel circuit in
In the organic light-emitting display apparatus according to the exemplary embodiment, both the pixel circuit PC_ODD in the odd row and the pixel circuit PC_EVEN in the even row perform light emission within one frame time as described above with reference to
Referring to
An anode initialization transistor TRIE has a first electrode connected to the initialization voltage line VL, a second electrode connected to an output node VOUT_EVEN, and a gate electrode connected to a second control line CL1_EVEN. The anode initialization transistor TRIE outputs an initialization voltage received from the initialization voltage line VL to the output node VOUT_EVEN based on a second control signal received through the second control line CL1_EVEN.
Thus, the anode initialization transistors TRIO and TRIE in the pixel circuits PC_ODD and PC_EVEN are connected to the initialization voltage line VL, instead of data line DL, and receive the initialization voltage from initialization voltage line VL.
Since the anode initialization transistors TRIO and TRIE of the pixel circuits PC_ODD and PC_EVEN of
However, since the anode initialization transistors TRIO and TRIE of the pixel circuits PC_ODD and PC_EVEN of
In accordance with one or more of the aforementioned embodiments, it is an organic light-emitting display apparatus increases emission time by decreasing a data write time.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the invention as set forth in the following claims.
Number | Date | Country | Kind |
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10-2015-0010026 | Jan 2015 | KR | national |