Exemplary embodiments of the present disclosure relate to an organic light-emitting display device and a driving method for the same.
In response to the development of the information society, there has been increasing demand for various types of display devices able to display images. Recently, a range of display devices, such as liquid crystal display (LCD) devices, plasma display panels (PDPs), and organic light-emitting display devices, are in use.
Among the range of display devices, organic light-emitting display devices have superior characteristics, such as high color reproduction accuracy, wide viewing angles, and rapid response rates, since organic light-emitting diodes (OLEDs) able to emit light by themselves are used therein. In addition, organic light-emitting display devices are widely used in mobile devices, such as smartphones and tablet PCs, since organic light-emitting display devices are thin and light, and consume less power.
The operating times of mobile devices may be determined by the capacities of batteries, since mobile devices are supplied with power from batteries. However, since mobile devices are designed to have thin profiles to improve ease of use, battery capacities are limited and thus the operating times of mobile devices are reduced. In particular, since mobile devices, such as smartphones and tablet PCs, include a variety of sensors, a touch panel, and the like to perform a variety of functions, there is a need to increase operating times by reducing power consumption.
Various aspects of the present disclosure provide an organic light-emitting display device and a driving method for the same, in which power consumption can be reduced.
Also provided are an organic light-emitting display device and a driving method for the same, in which luminance can be adjusted without adjustment in data voltages.
According to an aspect of the present disclosure, an organic light-emitting display device can include: a display panel having first power and second power supplied thereto, in which the display panel provides luminance based on driving current corresponding to a data signal and operates in a normal mode and a standby mode in response to a voltage level of the first power, a luminance of the standby mode is lower than a luminance of the normal mode; a control circuit outputting mode control signals corresponding to the normal mode and the standby mode; and a power source supplying the first power and the second power to the display panel. In response to the mode control signals, the power source supplies a first voltage as a voltage of the first power in the normal mode and supplies a second voltage as a voltage of the first power in the standby mode. The voltage level of the second voltage is lower than the voltage level of the first voltage. The voltage level of the second voltage is set such that a difference between the amount of driving current corresponding to the first voltage and a data voltage and the amount of driving current corresponding to the second voltage and the data voltage is greater than a predetermined value.
According to another aspect of the present disclosure, an organic light-emitting display device can include: a display panel operating such that an amount of driving current in a normal mode is greater than an amount of driving current in a standby mode; a control circuit outputting mode control signals; and a power supply applying a first voltage to the display panel in the normal mode and a second voltage to the display panel in the standby mode in response to the mode control signals. A change in the amount of driving current flowing through a pixel when a change in the voltage level of the second voltage is a predetermined voltage is greater than a change in the amount of driving current flowing through the pixel when a change in the voltage level of the first voltage is the predetermined voltage.
According to another aspect of the present disclosure, provided is a method of driving an organic light-emitting display device including a number of pixels. The method can include: receiving mode control signals for instructing a normal mode and a standby mode; supplying a first voltage to first power in the normal mode and supplying a second voltage to second power in the standby mode, the second voltage is lower than the first voltage; and supplying driving current corresponding to the first voltage to an organic light-emitting diode (OLED) in the normal mode and supplying driving current corresponding to the second voltage to the OLED in the standby mode. The second voltage is set such that a difference between an amount of driving current corresponding to the first voltage and a data voltage and an amount of driving current corresponding to the second voltage and the data voltage is greater than a predetermined value.
According to still another aspect of the present disclosure, provided is a method of driving an organic light-emitting display device including a number of pixels. The method can include: receiving mode control signals for instructing a normal mode and a standby mode; supplying a first voltage to first power in the normal mode and supplying a second voltage to second power in the standby mode, the second voltage is lower than the first voltage; and supplying driving current corresponding to the first voltage to an OLED in the normal mode and supplying driving current corresponding to the second voltage to the OLED in the standby mode. A change in the amount of driving current flowing through a pixel when a change in the voltage level of the second voltage is a predetermined voltage is greater than a change in the amount of driving current flowing through the pixel when a change in the voltage level of the first voltage is the predetermined voltage.
According to the present disclosure as set forth above, the organic light-emitting display device and the driving method for the same can reduce power consumption.
In addition, according to the present disclosure, the organic light-emitting display device and the driving method for the same can adjust luminance without adjusting data voltages.
The above and other objects, features and advantages of the present disclosure will be more clearly understood from the following detailed description when taken in conjunction with the accompanying drawings, in which:
Hereinafter, reference will be made to embodiments of the present disclosure in detail, examples of which are illustrated in the accompanying drawings. Throughout this document, reference should be made to the drawings, in which the same reference numerals and symbols will be used to designate the same or like components. In the following description of the present disclosure, detailed descriptions of known functions and components incorporated herein will be omitted in the situation that the subject matter of the present disclosure may be rendered unclear thereby.
It will also be understood that, while terms such as “first,” “second,” “A,” “B,” “(a),” and “(b)” can be used herein to describe various elements, such terms are only used to distinguish one element from another element. The substance, sequence, order, or number of these elements is not limited by these terms. When an element is referred to as being “connected to” or “coupled to” another element, not only can it be “directly connected or coupled to” the other element, but it can also be “indirectly connected or coupled to” the other element via an “intervening” element. In the same context, when an element is referred to as being formed “on” or “under” another element, not only can it be directly formed on or under another element, but it can also be indirectly formed on or under another element via an intervening element.
Referring to
In addition, the organic light-emitting display device 100 includes a driver integrated circuit (IC) 120 supplying data signals to the display panel 110. The driver IC 120 supplies gate signals to the organic light-emitting display device 100 so that data signals are sequentially provided to the display panel. The driver IC 120 includes a gate driver 120b driving gate signals and a data driver 120a receiving digital image signals, converting the digital image signals into analog data signals, and providing the analog data signals to data lines.
The display panel 110 includes a number of gate lines G1, G2, . . . , Gn-1, and Gn receiving gate signals from the gate driver 120b and a number of data lines D1, D2, . . . , Dm-1, and Dm receiving data signals from the data driver 120a. The number of gate lines G1, G2, . . . , Gn-1, and Gn intersect the number of data lines D1, D2, . . . , Dm-1, and Dm. A number of pixels 101 are arranged in areas in which the number of gate lines G1, G2, . . . , Gn-1, and Gn intersect the number of data lines D1, D2, . . . , Dm-1, and Dm. In addition, the display panel 110 has first power lines VL, through which delivering voltages of the first power are delivered to the number of pixels 101, such that the number of pixels 101 receive the voltages of the first power from the first power lines VL. Furthermore, a common electrode is disposed in the display panel 110, such that the number of pixels 101 receive voltages of the second power from the common electrode.
The control circuit 130 provides control signals to the driver IC 120. The control signals provided to the driver IC 120 can include a gate start pulse, a data start pulse, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. In addition, the control circuit 130 provides mode control signals to the power supply 140. In response to the mode control signals, the display panel 110 is controlled to operate in a normal mode or in a standby mode. In addition, the control circuit 130 provides digital images to the driver IC 120.
The power supply 140 supplies the first power ELVDD and the second power ELVSS, generated thereby, to the display panel 110. The first power ELVDD is supplied to the first power lines VL of the display panel 110, and the second power ELVSS is supplied to the common electrode of the display panel 110. However, the present disclosure is not limited thereto.
The power supply 140 regulates voltages of the first power based on mode control signals received from the control circuit 130. When the display panel 110 operates in the normal mode in response to a mode control signal, the voltage of the first power ELVDD is supplied at a first voltage level. Further, when the display panel 110 operates in the standby mode in response to a mode control signal, the voltage of the first power ELVDD is set to a second voltage level lower than the first voltage level.
Although the gate driver 120b included in the driver IC is illustrated as being a component separate from the display panel 110, the present disclosure is not limited thereto. The gate driver 120b can be disposed in a non-display area of the display panel 110. The gate driver 120b disposed in the non-display area of the display panel 110 can be referred to as a gate in panel (GIP). In addition, although the gate driver 120b is illustrated as being disposed on one side of the display panel 110, the present disclosure is not limited thereto. The gate driver 120b can be disposed on both sides of the display panel 110.
Referring to
The first transistor M1 has a first electrode connected to a first power line VL, through which the first power ELVDD is delivered, a gate electrode connected to a first node N1, and a second electrode connected to a second node N2. The first transistor M1 allows the driving current to flow from the first electrode to the second electrode, in response to a voltage of the first node N1. The first transistor M1 can be referred to as a driving transistor.
The second transistor M2 has a first electrode connected to a data line DL, through which the data voltage Vdata is delivered, a gate electrode connected to a gate line, through which a gate signal is delivered, and a second electrode connected to the first node N1. The second transistor M2 delivers the data voltage Vdata to the first node N1 in response to the gate signal provided to the gate electrode. The second transistor M2 can be referred to as a switching transistor.
The first capacitor C1 is connected to both the first node N1 and the second node N2 to allow the voltage of the first node N1 to be maintained.
The OLED has an anode connected to the second node N2 and a cathode connected to the second power ELVSS to generate light by receiving the driving current flowing through the second node N2.
In the pixel circuit 101a, the first transistor M1 has the first electrode connected to the first power ELVDD, the gate node connected to the first node N1, and the second electrode connected to the second node N2, the second transistor M2 has the first electrode connected to the data line DL, the gate electrode connected to the gate line, and the second electrode connected to the first node N1, and the capacitor C1 has the first electrode connected to the first node N1 and the second electrode connected to the second node N2.
In the pixel circuit 101a configured as above, the magnitude of a driving current flowing through the OLED can correspond to Formula 1.
where IOLED indicates the magnitude of the driving current, β is a constant, VGS indicates the difference in voltage between the second electrode and the gate electrode the first transistor M1, and Vth indicates the threshold voltage of the first transistor M1.
Referring to
When the display panel 110 operates in the normal mode, the control circuit 130 outputs a mode control signal in a high state. In addition, when the display panel 110 operates in the standby mode, the control circuit 130 outputs a mode control signal in a low state. When a mode control signal is output in a high state, the power supply 140 outputs first power ELVDD, the voltage level of which is a first voltage Vd1, in response to the mode control signal. When a mode control signal is output in a low state, the power supply 140 outputs first power ELVDD, the voltage level of which is a second voltage Vd2, in response to the mode control signal. The voltage level of the second voltage can be lower than the voltage level of the first voltage Vd1.
Referring to
In the situation, in which the voltage of the first power ELVDD increases and there is a significant difference between a voltage applied to a second electrode and the voltage of a gate electrode of the driving transistor, a driving current IOLED is indicated by curve VGS1. When the difference between the voltage applied to the second electrode and the voltage of the gate electrode of the driving transistor is insignificant, the driving current IOLED is indicated by curve VGS2.
Thus, it is possible to adjust the magnitude of the driving current IOLED by adjusting the difference in voltage between the second electrode and the gate electrode of the driving transistor based on a data voltage applied to the gate electrode, so that a gray scale can be provided for light generated by the OLED.
When the voltage of the first power ELVDD is the first voltage Vd1 located in the first section TS (normal mode), the difference in voltage between the second electrode and the gate electrode of the driving transistor is constant, and even in the situation in which the first voltage Vd1 changes in the normal mode section TS, a change in the driving current is insignificant (e.g., there is negligible increase in the driving current). Accordingly, there is no change in luminance and thus, gray scales corresponding to data voltages can be provided. It is therefore possible to vary the magnitude of the driving current IOLED flowing through the OLED, in response to the data voltages, by setting the voltage of the first power ELVDD to be the first voltage Vd1 in the normal mode.
In contrast, when the voltage of the first power ELVDD is the second voltage Vd2 located in a second section TL (standby mode), the driving current IOLED has a significant change ΔI in the second section TL in response to a change in the second voltage Vd2, even in the situation in which the difference in voltage between the second electrode and the gate electrode of the driving transistor is constant. Thus, even in the situation in which the data voltage is relatively constant, the driving current can significantly change, and a constant gray scale cannot be expressed when the second voltage Vd2 changes slightly. Accordingly, this operation region of the driving transistor cannot be used in the normal mode.
In addition, the first section TS can be referred to as a saturation section since a small amount of the driving current IOLED changes therein, while the second section TL may be referred to as a linear section, since a large amount of the driving current IOLED changes therein.
In addition, the luminance of the OLED can be provided by the first curve A in the first section TS, corresponding to changes in the voltage applied to the gate electrode of the driving transistor, while being provided by the second curve B, corresponding to changes in the voltage of the gate electrode. Comparing the first curve A and the second curve B, it can be appreciated that the amount of driving current flowing through the second section TL is significantly smaller than the amount of driving current flowing through the first section TS, even in the situation in which the difference in voltage between the second electrode and the gate electrode of the driving transistor is the same in both the first and second sections.
It is therefore possible to significantly reduce power consumption by allowing the driving transistor to drive in the second section TL. Although a difference in luminance is likely to be significant in the second section TL, a low luminance level can cause the difference in luminance to be insignificant. Thus, when the display panel 110 illustrated in
In addition, the threshold voltage of the driving transistor can be indicated by a third curve C, corresponding to the difference in voltage between the second electrode and the gate electrode of the driving transistor and the voltage difference of the first power ELVDD. The threshold voltage can be determined by a voltage of the first power ELVDD applied to the first electrode of the driving transistor, a voltage applied to the gate electrode of the driving transistor, and a voltage applied to the second electrode of the driving transistor.
Thus, the threshold voltage of the driving transistor can be expressed by Formula 2.
Vth=VGS−VDS (2),
where Vth indicates the threshold voltage of the driving transistor, VGS indicates the difference in voltage between the gate electrode and the second electrode of the driving transistor, and VDS indicates the difference in voltage between the first electrode and the second electrode of the driving transistor.
That is, the threshold voltage may be a result obtained by deducting the difference in voltage between the first electrode and the second electrode of the driving transistor from the difference in voltage between the gate electrode and the second electrode of the driving transistor. Accordingly, it is possible to determine whether the driving transistor operates in the first section TS or the second section TL, by comparing the voltage level of the threshold voltage and the voltage level of the first power.
In addition, this can be applied to the pixels illustrated in
In addition, when the voltage of the first power ELVDD is the second voltage Vd2, the voltage level of which is smaller than the voltage level of the threshold voltage, there is a significant difference in the amount of driving current. Thus, the voltage level of the first power ELVDD can be determined to be the voltage level of the first voltage Vd1 or the second voltage Vd2, based on the amount of the driving current corresponding to the data voltage Vdata. Specifically, when an amount of the driving current IOLED is not determined to be different from a predetermined value, based on the data voltage Vdata, the voltage level of the first power ELVDD can be determined to be the first voltage Vd1. When the amount of the driving current is different from the predetermined value, based on the data voltage Vdata, the voltage level of the first power ELVDD can be determined to be the second voltage Vd2. That is, when the magnitude of the driving current is equal to or lower than the magnitude of the driving current flowing in the normal mode based on the predetermined value, the voltage of the first power ELVDD is determined to be the second voltage Vd1. The voltage of the first power ELVDD can be determined to be the voltage of the first power ELVDD applied to the first electrode of the driving transistor in the standby mode. The power supply 140 illustrated in
Referring to
Referring to
In the first transistor M1, the first electrode is connected to a third node N3, the gate electrode is connected to a first node N1, and the second electrode is connected to a second node N2. The first transistor M1 allows driving current to flow from the first electrode to the second electrode in response to a voltage delivered to the gate electrode.
In the second transistor M2, the first electrode is connected to a data line DL, the gate electrode is connected to a first gate line GL1, and the second electrode is connected to the first node N1. In response to a first gate signal provided to the gate electrode, the second transistor M2 delivers the data voltage Vdata from the first electrode to the second electrode, thereby delivering the data voltage Vdata to the first node N1.
In the third transistor M3, the first electrode is connected to an initialization voltage line VL2, through which the initialization voltage is delivered, the gate electrode is connected to a second gate line GL2, and the second electrode is connected to the second node N2. The third transistor M3 delivers the initialization voltage Vref to the second node N2 in response to the second gate signal provided to the gate electrode. Here, the initialization voltage Vref can be a voltage lower than the threshold voltage of the OLED.
In the fourth transistor M4, the first electrode is connected to a power line VL1, through which the first power ELVDD is delivered, the gate electrode is connected to an emission control line EL, and the second electrode is connected to the third node N3. The fourth transistor M4 delivers a voltage of the first power ELVDD to the third node N3 in response to the emission control signal provided to the gate electrode.
The first capacitor C1 is connected to the first node N1 and the second node N2. The first capacitor C1 allows a difference in voltage between the gate electrode and the second electrode of the first transistor M1 to be maintained. In addition, the voltage stored in the first capacitor C1 can be initialized by the initialization voltage Vref delivered, in response to the third transistor M3 being turned on by the second gate signal.
The second capacitor C2 is connected to the power line VL1, through which the first power ELVDD is supplied, and the second node N2. The voltage stored in the second capacitor C2 can be initialized by the initialization voltage Vref delivered in response to the third transistor M3 being turned on by the second gate signal.
In addition, in the OLED, the anode is connected to the second electrode of the first transistor M1, and the cathode is connected to the second power ELVSS.
The first power ELVDD can deliver the first voltage Vd1 (
In the first transistor M1, the voltage of the first power ELVDD, the voltage applied to the gate electrode, and the voltage applied to the second electrode are determined. The voltage of the first power ELVDD can be determined to be the second voltage Vd2 when Formula 3 is satisfied.
where ELVDD indicates the voltage of the first power, Vdata indicates a data voltage corresponding to a data signal, Vref indicates the voltage of the initialization signal, C1 indicates the capacitance of the first capacitor, C2 indicates the capacitance of the second capacitor, VDS indicates the difference in voltage between the first electrode and the second electrode of the first transistor, and VGS indicates the difference in voltage between the gate electrode and the second electrode of the first transistor.
Referring to
In the first transistor M1, the first electrode is connected to a first power line VL1, through which first power ELVDD is delivered, the gate electrode is connected to a first node N1, and the second electrode is connected to a second node N2. The first transistor M1 allows driving current to flow from the first electrode connected to the first power ELVDD to the second electrode connected to the second node N2 in response to a voltage delivered to the gate electrode.
In the second transistor M2, the first electrode is connected to a data line DL, the gate electrode is connected to a gate line GL, through which a gate signal is provided, and the second electrode is connected to a first electrode of the first capacitor C1. In response to a gate signal provided to the gate electrode, the second transistor M2 delivers a data voltage Vdata, corresponding to a data signal, from the first electrode connected to the data line DL to the first electrode of the first capacitor C1.
In the third transistor M3, the first electrode is connected to the second node N2, the gate electrode is connected to the gate line GL, and the second electrode is connected to the first node N1. In response to the gate signal provided to the gate electrode, the third transistor M3 controls the voltage of the first node N1 and the voltage of the second node N2 to be equal, so that the first transistor M1 can allow the current to flow to the second node N2. In this instance, a voltage corresponding to the threshold voltage can be stored in the first capacitor C1 connected to the first node N1.
In the fourth transistor M4, the first electrode is connected to an initialization power line VL2, through which an initialization voltage Vref is delivered, the gate electrode is connected to an emission control line EL, through which an emission control signal is provided, and the second electrode is connected to the first electrode of the first capacitor C1 and the second electrode of the second transistor M2. In response to the emission control signal provided to the gate electrode, the fourth transistor M4 delivers the initialization voltage Vref to the first electrode of the first capacitor C1 and the second electrode of the second transistor M2.
In the fifth transistor M5, the first electrode is connected to the second node N2, the gate electrode is connected to the emission control line EL, through which the emission control signal is provided, and the second electrode is connected to the anode of the OLED. In response to the emission control signal provided through the gate electrode, the fifth transistor M5 provides the driving current to the OLED.
In the sixth transistor M6, the first electrode is connected to the initialization power line VL2, through which the initialization voltage Vref is delivered, the gate electrode is connected to an initialization control line IL, through which an initialization control signal is provided, and the second electrode is connected to the anode of the OLED. In response to the initialization control signal provided to the gate electrode, the sixth transistor M6 can deliver the initialization voltage Vref to the anode of the OLED. Since the initialization voltage Vref is lower than the threshold voltage of the OLED, the OLED does not generate light in an initialization section, in which the initialization voltage Vref is delivered.
The first capacitor C1 is connected between the first node N1 and the second electrode of the second transistor M2. When the fourth transistor M4 is turned on, the first capacitor C1 receives the initialization voltage Vref. When the third transistor M3 is turned by the gate signal, the first capacitor C1 receives a voltage corresponding to the threshold voltage.
In addition, in the OLED, the anode is connected to the second electrodes of the fifth transistor M5 and the sixth transistor M6, and the cathode is connected to the second power ELVSS. When the fifth transistor M5 is turned on, the OLED generates light by receiving the driving current.
The voltage of the first power ELVDD can be set to the first voltage Vd1 (
In the first transistor M1, the voltage of the first power ELVDD, the voltage applied to the gate electrode, and the voltage applied to the second electrode are determined. The voltage of the first power ELVDD can be determined to be the second voltage Vd2 when Formula 4 is satisfied.
ELVDD−ELVSS<(Vdata−Vref) (4),
where ELVDD indicates the voltage of the first power, ELVSS indicates the voltage of the second power, Vdata indicates the data voltage corresponding to the data signal, and Vref indicates the voltage of the initialization signal.
Referring to
In the first transistor M1, the first electrode is connected to a third node N3, the gate electrode is connected to the first node N1, and the second electrode is connected to the second node N2. The first transistor M1 allows driving current to flow from the first electrode to the second electrode in response to a voltage delivered to the gate electrode.
In the second transistor M2, the first electrode is connected to the data line DL, the gate electrode is connected to the second gate line, and the second electrode is connected to the third node N3. The second transistor M2 delivers a data voltage to the third node N3 in response to a second gate signal provided to the gate electrode through a second gate line GL2.
In the third transistor M3, the first electrode is connected to the second node N2, the gate electrode is connected to the second gate line GL, and the second electrode is connected to the second node N2. In response to the second gate signal provided to the gate electrode through the second gate line GL, the third transistor M3 controls the potential of the first node N1 and the potential of the second node N2 to be equal.
In the fourth transistor M4, the first electrode is connected to an initialization power line VL2, through which an initialization voltage Vref is delivered, the gate electrode is connected to the first gate line GL, through which a first gate signal is provided, and the second electrode is connected to the first node N1. The fourth transistor M4 delivers the initialization voltage Vref to the first node N1 in response to the first gate signal provided through the first gate line GL1.
In the fifth transistor M5, the first electrode is connected to a first power line VL1, the gate electrode is connected to an emission control line EN, and the second electrode is connected to the third node N3. In response to the emission control signal provided through the emission control line EL, the firth transistor M5 supplies the voltage of the first power ELVDD delivered to the first power line VL1 to the third node N3.
In the sixth transistor M6, the first electrode is connected to the second node N2, the gate electrode is connected to the emission control line EL, through which the emission control signal is provided, and the second electrode is connected to the anode of the OLED. In response to the emission control signal provided to the gate electrode, the sixth transistor M6 provides the driving current flowing through the second node N2 to the OLED.
In the seventh transistor M7, the first electrode is connected to the initialization power line VL2, through which the initialization voltage Vref is delivered, the gate electrode is connected to the third gate line, through which a third gate signal is provided, and the second electrode is connected to the anode of the OLED. In response to the third gate signal provided to the gate electrode, the seventh transistor M7 can deliver the initialization voltage Vref to the anode of the OLED. The voltage level of the initialization voltage Vref can be lower than the voltage level of the threshold voltage of the OLED.
The first capacitor C1 is connected to the first power line VL1, through which the first power ELVDD is supplied, as well as the first node N1, to store a voltage corresponding to a data voltage Vdata. In addition, the first capacitor C1 can be initialized by the initialization voltage Vref. When the second transistor M2 and the third transistor M3 are turned on by the second gate signal, the data voltage Vdata is delivered to the first node N1 through the first transistor M1 and the third transistor M3, so that a voltage corresponding to the threshold voltage is stored in the first node N1. Thus, the threshold voltage can be compensated for.
In the OLED, the anode is connected to the second electrode of the sixth transistor M6 and the second electrode of the seventh transistor M7, and the cathode is connected to the second power ELVSS.
The voltage of the first power ELVDD can be set to the first voltage Vd1 (
In the first transistor M1, the voltage of the first power ELVDD, the voltage applied to the gate electrode, and the voltage applied to the second electrode are determined. The voltage of the first power ELVDD can be determined to be the second voltage Vd2 when Formula 5 is satisfied.
ELVDD−ELVSS<Vref−Vdata (5),
where ELVDD indicates the voltage of the first power, ELVSS indicates the voltage of the second power, Vdata indicates the data voltage corresponding to the data signal, and Vref indicates the voltage of the initialization signal.
Referring to
Referring to
Referring to
The control circuit 130 can output the mode control signal, and the organic light-emitting display device can operate in the normal mode as well as in the standby mode in response to the mode control signal. The control circuit 130 can output the mode control signal to instruct the organic light-emitting display device to operate in the normal mode as well as in the standby mode, by determining whether or not the organic light-emitting display device is being used.
In addition, the mode control signal allows the organic light-emitting display device to receive a first voltage or a second voltage supplied from the first power. The organic light-emitting display device can operate in the normal mode when the first voltage is received and in the standby mode when the second voltage is received.
In addition, the organic light-emitting display device includes the number of pixels, each of which can emit light at a lower level of luminance upon receiving a second voltage, since the driving current corresponding to the second voltage is smaller than that of a first voltage. Accordingly, it is possible to vary luminance without varying a data voltage. Also, lowering luminance reduces power consumption. Each of the number of pixels includes a driving transistor to adjust the magnitude of driving current in response to the first voltage or the second voltage.
According to exemplary embodiments, the voltage level of the second voltage can be determined such that the difference between the amount of driving current corresponding to the first voltage and the data voltage, and the amount of driving current corresponding to the second voltage and the data voltage is greater than a predetermined value.
In addition, according to exemplary embodiments, a change in the amount of driving current flowing through a pixel when the second voltage is changed by a predetermined voltage can be greater than a change in the amount of driving current flowing through the pixel when the first voltage is changed by the predetermined voltage.
The foregoing descriptions and the accompanying drawings have been presented in order to explain the certain principles of the present disclosure. A person skilled in the art to which the present disclosure relates could make many modifications and variations by combining, dividing, substituting for, or changing the elements without departing from the principle of the present disclosure. The foregoing embodiments disclosed herein shall be interpreted as illustrative only but not as limitative of the principle and scope of the present disclosure. It should be understood that the scope of the present disclosure shall be defined by the appended Claims and all of their equivalents fall within the scope of the present disclosure.
Number | Date | Country | Kind |
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10-2016-0175038 | Dec 2016 | KR | national |
This application is a Continuation of U.S. patent application Ser. No. 15/793,541, filed on Oct. 25, 2017, which claims the benefit of priority from Korean Patent Application No. 10-2016-0175038 filed in the Republic of Korea on Dec. 20, 2016, all of these applications are hereby incorporated by reference for all purposes as if fully set forth herein.
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Number | Date | Country | |
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Parent | 15793541 | Oct 2017 | US |
Child | 16566526 | US |