Korean Patent Application No. 10-2014-0122730, filed on Sep. 16, 2014, and entitled, “Organic Light Emitting Display Device,” is incorporated by reference herein in its entirety.
1. Field
One or more embodiments described herein relate to an organic light emitting display device.
2. Description of the Related Art
Consumer demand for improvements in flat panel displays continues to increase.
Examples of these displays include liquid crystal displays, plasma display panels, and organic light emitting displays.
An organic light emitting display includes pixels disposed in a matrix form at intersections of data lines and scan lines. A data driver supplies data voltages to the data lines, and a scan driver supplies scan signals to the scan lines. The display further includes a power supply unit for supplying a plurality of power voltages to the panel. In operation, each pixel emits light with brightness based on a controlled current flowing from a first power voltage to an organic light emitting diode. The controlled current corresponds to a data voltage supplied through a data line when a scan signal is supplied.
During manufacturing, a defect occur to one or more of transistors of the pixels. As a result, manufacturing yield deteriorates.
In accordance with one embodiment, an organic light emitting display device includes data lines; auxiliary data lines; scan lines and emission control lines crossing the data lines and the auxiliary data lines; display pixels at corresponding intersections of the data lines, the scan lines, and the emission control lines; auxiliary pixels at corresponding intersections of the auxiliary data lines, the scan lines, and the emission control lines; and auxiliary lines connected to the auxiliary pixels, wherein scan signals are to be supplied in a unit of p scan lines, A emission control signals are to be supplied in a unit of p A emission control lines, and B emission control signals are to be supplied in a unit of p B emission control lines, wherein p≧2.
A same A emission control signal may be supplied to p A emission control lines, and a same B emission control signal may be supplied to p B emission control lines. The scan signals are to be sequentially supplied to p scan lines, and the scan signals are to be applied to have increasing pulse widths. A pulse width of the scan signal supplied to a k+1th scan line may be greater than a pulse width of the scan signal supplied to a kth scan line.
The auxiliary pixel may include a discharge transistor connected to the auxiliary line, and a first power voltage line to receive a first power voltage. The auxiliary pixel may include a plurality of transistors, and a discharge transistor controller to control the discharge transistor. The discharge transistor controller may include first and second discharge control transistors connected to a control electrode of the discharge transistor, and a control electrode of the first discharge control transistor and a control electrode of the second discharge control transistor may be connected to different lines.
The control electrode of the first discharge transistor may be connected to a pull-down control node of an emission stage connected to a corresponding one of the emission control lines, and the first discharge transistor may include a first electrode connected to a corresponding one of the scan lines, and a second electrode connected to the control electrode of the discharge transistor, wherein the control electrode and a second electrode of the second discharge control transistor may be connected to a corresponding one of the scan lines, and a first electrode of the second discharge control transistor may be connected to the control electrode of the discharge transistor.
The control electrode of the first discharge control transistor may be connected to a pull-down control node of an emission stage connected to a corresponding one of the emission control lines, and the first discharge control transistor may include a first electrode connected to a gate off voltage line to which a gate off voltage is supplied, and a second electrode connected to the control electrode of the discharge transistor, the control electrode of the second discharge control transistor may be connected to a corresponding one of the scan lines, and the second discharge control transistor may include a first electrode connected to the control electrode of the discharge transistor and a second electrode connected to a gate on voltage line to receive a gate on voltage.
The discharge transistor controller may include a first capacitor connected to the control electrode of the discharge transistor and a second power voltage line to receive a second power voltage. The auxiliary pixel may include an auxiliary pixel driver which includes a plurality of transistors, and the auxiliary pixel driver may supply a driving current to the auxiliary line.
The auxiliary pixel driver may include a first transistor to control the driving current according to a voltage of a control electrode; a second transistor connected to a corresponding one of the auxiliary data lines and a control electrode of the first transistor; a third transistor connected to a first electrode of the first transistor and a second power voltage line to which a second power voltage is supplied; a fourth transistor connected to a second electrode of the first transistor and the auxiliary line; a second capacitor connected to the control electrode and the first electrode of the first transistor; and a third capacitor connected to the first electrode of the first transistor and the second power voltage line.
The control electrode of the second transistor may be connected to a corresponding one of the scan lines, a control electrode of the third transistor may be connected to a corresponding one of the A emission control lines, and a control electrode of the fourth transistor may be connected to a corresponding one of the B emission control lines.
The display pixel may include an organic light emitting diode; and a display pixel driver including a plurality of transistors, the display pixel driver to supply a driving current to the organic light emitting diode.
The display pixel driver may include a first transistor to control the driving current according to a voltage of a control electrode; a second transistor connected to a corresponding one of the data lines and a control electrode of the first transistor; a third transistor connected to a first electrode of the first transistor and a second power voltage line to which a second power voltage is supplied; a fourth transistor connected to a second electrode of the first transistor and an anode electrode of the organic light emitting diode; a fifth transistor connected to the anode electrode of the organic light emitting diode and a third power voltage line to which a third power voltage is supplied; a second capacitor connected to the control electrode and first electrode of the first transistor; and a third capacitor connected to the first electrode of the first transistor and second power voltage line.
Control electrodes of the second and fifth transistors may be connected to a corresponding one of the scan lines, a control electrode of the third transistor may be connected to a corresponding one of the A emission control lines, and a control electrode of the fourth transistor may be connected to a corresponding one of the B emission control lines.
In accordance with another embodiment, a driver includes a generator to generate auxiliary data based on location information of a defective pixel to be repaired in a display; and a converter to adjust the auxiliary data to at least partially compensate for at least one of a wire resistance of an auxiliary line coupled to an auxiliary pixel circuit or a parasitic capacitance of the auxiliary line, wherein the generator is to generate the auxiliary data based on a repair control signal for the defective pixel.
The converter may adjust the auxiliary data to at least partially compensate for the wire resistance of the auxiliary line coupled to an auxiliary pixel circuit and the parasitic capacitance of the auxiliary line. The converter may add predetermined data to the auxiliary data, the predetermined data corresponding to at least one of the wire resistance of the auxiliary line coupled to the auxiliary pixel circuit or the parasitic capacitance of the auxiliary line. The location information may be a coordinate value of the defective pixel.
Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which:
Example embodiments are described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey exemplary implementations to those skilled in the art. In the drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout.
The display panel 10 includes data lines D1 to Dm (m is a positive integer equal to or greater than 2), auxiliary data lines RD1 and RD2, scan lines S1 to Sn (n is a positive integer equal to or greater than 2), A emission control lines EA1 to EAn, and B emission control lines EB1 to EBn. The data lines D1 to Dm and the auxiliary data lines RD1 and RD2 may be formed in parallel to each other. The auxiliary data lines RD1 and RD2 may be formed at outer sides of both sides of the data lines D1 to Dm. For example, as illustrated in
The data lines D1 to Dm and the scan lines S1 to Sn may be formed to cross each other. The auxiliary data lines RD1 and RD2 and the scan lines S1 to Sn may also be formed to cross each other. The scan lines S1 to Sn and the first and B emission control lines EA1 to EAn and EB1 to EBn may be formed in parallel to each other.
The display panel 10 includes a display area DA, in which display pixels DPs for displaying an image are formed, and a non-display area NDA corresponding to an area except for the display area DA. The non-display area NDA may include first and second auxiliary pixel areas RPA1 and RPA2, in which auxiliary pixels RPs for repairing the display pixels DPs are formed. The auxiliary pixels RPs connected to a first auxiliary data line RD1 may be formed in a first auxiliary pixel area RPA1. The auxiliary pixels RPs connected to a second auxiliary data line RD2 may be formed in a second auxiliary pixel area RPA2.
The display pixels DPs may be disposed in a matrix form at intersections of the data lines D1 to Dm and the scan lines S1 to Sn in the display area DA. Each of the display pixels DPs are connected to corresponding ones of the data lines, scan lines, A emission control lines, and one B emission control lines.
The auxiliary pixels RPs may be disposed at intersections of the auxiliary data lines DR1 and RD2 and the scan lines S0 to Sn in each of the auxiliary pixel areas RPA1 and RPA2. The auxiliary pixels RPs are pixels to be used for repairing the display pixels DPs, which, for example, have a defect produced during a process of manufacturing the display panel 10. Each of the auxiliary pixels RPs may be connected to corresponding ones of the auxiliary data lines, a pair of scan lines, emission control lines, and auxiliary lines RL. The auxiliary line RL is connected to the auxiliary pixel RP and extends to the display area DA from the auxiliary pixel RP for crossing the display pixels DPs.
When a defect occurs in a display pixel DP, the defective display pixel DP is connected to the auxiliary line RL, for example, through a laser short-circuit process. A corresponding auxiliary pixel RP is connected to the defective display pixel DP through the auxiliary line RL, to effect repair of the defective display pixel DP using the auxiliary pixel RP. (A defective display pixel DP which has been repaired may be referred to as a repaired pixel).
The display panel 10 may include a plurality of power voltage lines to supply a plurality of power voltages to the display pixels DPs and the auxiliary pixels RPs.
The scan driver 20 includes a scan signal output unit for outputting scan signals to the scan lines S1 to Sn, an A emission control signal output unit for outputting emission control signals to the A emission control lines EA1 to EAn, and a B emission control signal output unit for outputting emission control signals to the B emission control lines EB1 to EBn.
The scan signal output unit receives a scan timing control signal SCS from the timing controller 50, and outputs the scan signals to the scan lines S1 to Sn according to the scan timing control signal SCS.
The A emission control signal output unit receives an A emission timing control signal ECSA from the timing controller 50, and outputs the A emission control signals to the A emission control lines EA1 to EAn according to the A emission timing control signal ECSA.
The B emission control signal output unit receives a B emission timing control signal ECSB from the timing controller 50, and outputs the B emission control signals to the B emission control lines EB1 to EBn according to the B emission timing control signal ECSB.
The scan signal output unit and the first and B emission control signal output units may be formed, for example, in an Amorphous Silicon Gate in Pixel (AGS) scheme or a Gate Driver in Panel (GIP) scheme in the non-display area NDA of display panel 10.
The first data driver 30 includes at least one source drive Integrated Circuit (IC). The source drive IC receives digital video data DATA and a source timing control signal DCS from the timing controller 50. The source drive IC converts the digital video data DATA to data voltages in response to a source timing control signal DCS. The source drive IC synchronizes the scan signals and the data voltages, respectively, and supplies the synchronized data voltages to the data lines D1 to Dm. Accordingly, the data voltages are supplied to the display pixels DPs, to which the scan signal is supplied.
The second data driver 40 receives a repair control signal RCS, the digital video data DATA, and coordinate data CD of the repaired pixel from the timing controller 50. The second data driver 40 generates auxiliary data voltages using the repair control signal RCS, the digital video data DATA, and the coordinate data CD of the repaired pixel. The second data driver 40 synchronizes the auxiliary data voltages and the scan signals, respectively, and supplies the synchronized auxiliary data voltages to the auxiliary data lines RD1 and RD2. Accordingly, the auxiliary data voltages are supplied to the auxiliary pixels RPs, to which the scan signal is supplied.
For example, the second data driver 40 supplies the same auxiliary data voltage as the data voltage, which is to be supplied to the repaired pixel, to the auxiliary pixel connected to the repaired pixel in order to repair the repaired pixel. Examples of the supply of the auxiliary data voltage by the second data driver 40 will be described with reference to
The timing controller 50 receives the digital video data DATA and timing signals from an external source. The timing controller 50 generates timing control signals for controlling the scan driver 20 and the first data driver 30 based on the timing signals. The timing control signals include the scan timing control signal SCS for controlling an operation timing of the scan signal output unit of the scan driver 20, the A emission timing control signal ECSA for controlling an operation timing of the A emission control signal output unit of the scan driver 20, the B emission timing control signal ECSB for controlling an operation timing of the B emission control signal output unit of the scan driver 20, and the data timing control signal DCS for controlling an operation timing of the first data driver 30. The timing controller 50 outputs the scan timing control signal SCS, and the A and B emission timing control signals ECSA and ECSB to the scan driver 20, and the data timing control signal DCS and the digital video data DATA to the first data driver 30.
Further, the timing controller 50 generates the repair control signal RCS and the coordinate data CD of a repaired pixel. The repair control signal RCS is a signal indicating whether the repaired pixel exists. For example, when a pixel has been repaired, the repair control signal RCS may be generated to have a first logic level voltage. Otherwise, the repair control signal RCS may be generated to have a second logic level voltage.
The coordinate data CD of the repaired pixel is a signal indicating a coordinate value of the repaired pixel. The coordinate data CD of the repaired pixel may be stored in a memory of the timing controller 50. The timing controller 50 outputs the repair control signal RCS, the coordinate data CD of the repaired pixel, and the digital video data DATA to the second data driver 40.
The power supply 60 may supply a plurality of power voltages to the plurality of power voltage lines. For example, the power supply 60 may supply first to fourth power voltages VIN1, VDD, VIN2, and VSS to the first to fourth power voltage lines. Examples of the first to fourth power voltage lines will be described with reference to
Referring to
Each auxiliary pixel RP includes an auxiliary pixel driver 210 and a discharge transistor DT. The auxiliary pixel driver 210 and the discharge transistor DT are connected to the auxiliary line RL. The auxiliary pixel driver 210 supplies a driving current to the auxiliary line RL. The discharge transistor DT discharges the auxiliary line RL with the first power voltage. The discharge transistor DT may be connected to the auxiliary line RL and a first power voltage line VINL1 for supplying the first power voltage. A control electrode of the discharge transistor DT may be connected to a discharge transistor controller.
The auxiliary line RL is connected to the auxiliary pixel RP and extends to the display area DA from the auxiliary pixel RP to cross the display pixels DPs. For example, in
The auxiliary line RL may be connected to one or more of the display pixels DPs of the display area DA. A display pixel DP is connected to the auxiliary line RL when the display pixel DP is defective and needs to be repaired. In
The auxiliary pixels RPs of the first auxiliary pixel area RP1 are connected to the first auxiliary data line RD1. The auxiliary pixels RPs of the second auxiliary pixel area RP2 are connected to the second auxiliary data line RD2. The display pixels DPs of the display area DA are connected to the data lines D1 to Dm.
The second data driver 40 includes an auxiliary data calculating unit 41, an auxiliary data converter 42, a memory 43, and an auxiliary data voltage converter 44. An example of a driving method of the second data driver 40 is described with reference to
First, the auxiliary data calculating unit 41 receives the repair control signal RCS, the digital video data DATA, and the coordinate data CD of the repaired pixel RDP1/RDP2 from the timing controller 50. The auxiliary data calculating unit 41 calculates auxiliary data RD when the repair control signal RCS of the first logic level voltage is input, and does not calculate the auxiliary data RD when the repair control signal RCS of the second logic level voltage is input. For example, when the repair control signal RCS of the first logic level voltage is input, the auxiliary data calculating unit 41 calculates the auxiliary data RD from the digital video data DATA according to the coordinate data CD of the repaired pixel.
The auxiliary data calculating unit 41 may calculate the digital video data corresponding to a coordinate value of the repaired pixel RDP1/RDP2 as the auxiliary data RD. For example, when the first repaired pixel RDP1 is positioned in the second row and the second column as illustrated in
The auxiliary data calculating unit 41 may calculate digital video data corresponding to the coordinate value (2, 2) as the auxiliary data RD, which is to be supplied to the auxiliary pixel RP connected to the first repaired pixel RDP1. The auxiliary data calculating unit 41 may calculate digital video data corresponding to the coordinate value (n−1, 2) as the auxiliary data RD, which is to be supplied to the auxiliary pixel RP connected to the second repaired pixel RDP2. The auxiliary data calculating unit 41 outputs the calculated auxiliary data RD to the auxiliary data converter 42 (S101, S102, S103).
Second, the auxiliary data converter 42 receives the auxiliary data RD from the auxiliary data calculating unit 41. In this case, the repaired pixel RDP1/RDP2 receives the auxiliary data voltage from the auxiliary pixel RP through the auxiliary line RL. Accordingly, the auxiliary data converter 42 may convert the auxiliary data RD by adding predetermined data to the auxiliary data RD considering wire resistance of the auxiliary line RL and parasitic capacitance formed in the auxiliary line RL. The auxiliary data converter 42 outputs converted auxiliary data RD′ to the memory 43.
In one embodiment, the auxiliary data converter 42 may be omitted. In this case, the auxiliary data calculating unit 41 outputs the auxiliary data RD to memory 43 (S104).
Third, the memory 43 receives and stores the converted auxiliary data RD′ from the auxiliary data converter 42. When auxiliary data converter 42 is omitted, the memory 43 receives and stores the auxiliary data from the auxiliary data calculating unit 41.
The memory 43 may be set to be updated to have initialization data for every predetermined period. For example, the memory 43 may receive a signal indicating a predetermined period from the timing controller 50. The signal indicating this predetermined period may be, for example, a vertical sync signal vsync for generating a pulse for every one frame period or a horizontal sync signal hsync for generating a pulse for every one horizontal frame period.
The one frame period may correspond to a period for which the data voltages are supplied to all of the display pixels DPs. The one horizontal period may correspond to a period for which the data voltages are supplied to the display pixels DPs of any one row. When the signal indicating a predetermined period is the vertical sync signal vsync, the memory 43 may be updated to have the initialization data for every one frame period. When the signal indicating a predetermined period is the horizontal sync signal hsync, the memory 43 may be updated to have the initialization data for every one horizontal period. The memory 43 may be implemented as, or may include, a register. The memory 43 outputs data DD stored therein to the auxiliary data voltage converter 44 (S105).
Fourth, the auxiliary data voltage converter 44 receives the data DD stored in the memory 43 and converts the received data DD to the auxiliary data voltage. The auxiliary data voltage converter 44 synchronizes the auxiliary data voltages and the scan signals, respectively, and supplies the synchronized auxiliary data voltages to the auxiliary data lines RD1 and RD2. Accordingly, the auxiliary data voltages supplied to the auxiliary data lines RD1 and RD2 are synchronized with the data voltages supplied to the data lines D1 to Dm to be supplied. For example, the auxiliary data voltage supplied to the auxiliary pixel RP of the pth row is synchronized to the data voltages supplied to the display pixels DPs of the pth row to be supplied (S106).
As described above, in the present embodiment, the digital video data DATA corresponding to the coordinate value of the repaired pixel RDP1/RDP2 corresponds to the auxiliary data RD. As a result, the same auxiliary data voltage as the data voltage, which is to be supplied to the repaired pixel RDP1/RDP2, is supplied to the auxiliary pixel RP connected to the repaired pixel RDP1/RDP2.
Referring to
As illustrated in
When the signal indicating the predetermined period is the vertical sync signal vsync, the memory 43 may be updated to have the initialization data BD for every one frame period. Accordingly, as illustrated in
Further, as illustrated in
Further, as illustrated in
As a result, as illustrated in
Referring to
As illustrated in
When the signal indicating the predetermined period is the horizontal sync signal hsync, the memory 43 may be updated to have the initialization data BD for every one horizontal period (1H). Accordingly, as illustrated in
Further, as illustrated in
Further, as illustrated in
As a result, as illustrated in
Further, as described with reference to
Each scan signal output unit is connected to p scan lines (p is a positive integer equal to or greater than 2) and outputs scan signals to the plurality of scan lines. For example, the scan signals are supplied in a unit of p scan lines. For example, the first scan signal output unit SCAN_OUT1 is connected to first to pth scan lines S1 to Sp, and outputs the scan signal to each of the first to pth scan lines S1 to Sp as illustrated in
Each of the plurality of scan signal output units includes a shift register unit 21 and a buffer unit 22. The shift register unit 21 receives the scan timing control signal SCS through a scan timing control line SCSL, and outputs output signals sequentially shifted according to the scan timing control signal SCS to the buffer unit 22. Further, the shift register unit 21 outputs a carry signal to the shift resister unit 21 at a rear end thereof through a first carry signal line CL1. For example, the shift register unit 21 of the first scan signal output unit SCAN_OUT1 outputs the carry signal to the shift resister 21 of the second scan signal output unit SCAN_OUT2 through first carry signal line CL1.
The buffer unit 22 generates scan signals by using the output signals supplied from the shift register unit 21. The buffer unit 22 supplies the generated scan signals to the p scan lines. Accordingly, the scan signals are supplied in the unit of p scan lines.
Each of the plurality of A emission control signal output units is connected to p A emission control lines and supplies the A emission control signals to the p A emission control lines. For example, the A emission control signals are supplied in the unit of p A emission control lines. In one embodiment, the first A emission control signal output unit EMA_OUT1 is connected to the first to pth A emission control lines EA1 to EAp, and outputs the A emission control signals to the first to pth A emission control lines EA1 to EAp as illustrated in
Further, each of the plurality of A emission control signal output outputs the carry signal to the A emission control signal output unit at a rear end thereof through a second carry signal line CL2. For example, the first A emission control signal output unit EMA_OUT1 outputs the carry signal to the second A emission control signal output unit EMA_OUT2 through the second carry signal line CL2 as illustrated in
Each of the plurality of B emission control signal output units is connected to p B mission control lines and supplies the B emission control signal to the p B emission control lines. For example, the B emission control signals are supplied in the unit of p B emission control lines. In one embodiment, the first B emission control signal output unit EMB_OUT1 is connected to the first to pth emission control lines EB1 to EBp, and outputs the B emission control signals to the first to pth B emission control lines EB1 to EBp as illustrated in
Further, the second B emission control signal output unit EMB_OUT2 is connected to the p+1th to 2pth B emission control lines EBp+1 to EB2p, and outputs the B emission control signal to each of the p+1th to 2pth B emission control lines EBp+1 to EB2p as illustrated in
Further, each of the plurality of B emission control signal output outputs the carry signal to the B emission control signal output unit at a rear end thereof through a third carry signal line CL3. For example, the first B emission control signal output unit EMB_OUT1 outputs the carry signal to the second B emission control signal output unit EMB_OUT2 through the third carry signal line CL3.
Control lines parallel to the scan lines S1 to Sn, the A emission control lines EMA1 to EMAn, and the B emission control lines EMB1 to EMBn may be formed in the display panel 10, for example, as illustrated in
A pull-down control node of each of the plurality of A emission control signal output units may be connected to p control lines. An example of the pull-down control node of each A emission control signal output unit is described with reference to
In one embodiment, the pull-down control node of a qth A emission control signal output unit EMA_OUTq (q is a positive integer equal to or greater than 2) is connected to p control lines adjacent to the A emission control lines connected to a q−1th A emission control signal output unit EMA_OUTq. For example, as illustrated in
Otherwise, the pull-down control node of the qth B emission control signal output unit EMB_OUTq may be connected to p control lines adjacent to the A emission control lines connected to the q−1th B emission control signal output unit EMA_OUTq. For example, as illustrated in
The pull-up transistor TU controls a connection of a gate on voltage line VONL and an output line OL according to a voltage of the pull-up control node Q. The output line OL of the second A emission control signal output unit EMA_OUT2 is connected to the p+1th to 2pth A emission control lines EAp+1 to EA2p as illustrated in
The pull-down transistor TD controls a connection of a gate off voltage line VOFFL and the output line OL according to a voltage of the pull-down control node QB. A control electrode of the pull-down transistor TD is connected to the pull-down control node QB, the first electrode of the pull-down transistor TD is connected to the gate off voltage line VOFFL, and the second electrode of the pull-down transistor TD is connected to the output line OL.
The node control circuit NC controls a voltage of the pull-up control node Q and a voltage of the pull-down control node QB. The node control circuit NC includes a plurality of signal input terminals. For example, the node control circuit NC may include a start terminal START into which a start signal is input, a clock terminal CLK into which a clock signal is input, and a reset terminal RESET into which a reset signal is input.
Further, the node control circuit NC may be connected to the gate on voltage line VONL and the gate off voltage line VOFFL. The start signal may be a gate start signal or a carry signal of a front end emission stage. The clock signal may be any one of a plurality of clock signals. The reset signal may be a carry signal of a rear end emission stage. The gate on voltage line may supply a gate on voltage, and the gate off voltage line may supply a gate off voltage. The gate on voltage may correspond to a voltage capable of turning on the transistors included in the emission stages, the display pixels, and the auxiliary pixels. The gate off voltage may correspond to a voltage capable of turning off the transistors in the emission stages, display pixels, and auxiliary pixels.
The node control circuit NC supplies the gate on voltage to the pull-up control node Q in response to the start signal input to the start terminal START, and supplies the gate off voltage to the pull-down control node QB. The pull-up transistor TU is turned on by the gate on voltage of the pull-up control node Q, and the pull-down transistor TD is turned off by the gate off voltage of the pull-down control node QB. Thus, the gate on voltage of the gate on voltage line VONL is output to the output line OL.
The node control circuit NC supplies the gate off voltage to the pull-up control node Q in response to the reset signal input to the reset terminal RESET, and supplies the gate on voltage to the pull-down control node QB. The pull-up transistor TU is turned off by the gate off voltage of the pull-up control node Q, and the pull-down transistor TD is turned on by the gate off voltage of the pull-down control node QB. Thus, the gate off voltage of the gate on voltage line VONL is output to the output line OL.
The pull-down control node QB of the second A emission control signal output unit EMA_OUT2 is connected to the first to pth control lines CCL1 to CCLp as illustrated in
Referring to
Pulses of the A emission control signals EMA1 and EMA2 and the B emission control signals EMB1 and EMB2 are generated by the gate off voltage Voff. The pulse width of each of the A emission control signals EMA1 and EMA2 may be substantially or identically implemented to the pulse width of each of the B emission control signals EMB1 and EMB2. Further, the pulse width of each of the A emission control signals EMA1 and EMA2 and the pulse width of each of the B emission control signals EMB1 and EMB2 may be greater than the pulse width of each of the first to 2pth scan signals SCAN1 to SCAN2p.
The ith data voltages DVi may be supplied in a cycle of one horizontal period (1H) from a time at which each of the B emission control signals EMB1 and EMB2 is changed from the gate on voltage Von to the gate off voltage Voff to be supplied. For example, the first to pth scan signals SCAN1 to SCANp are supplied as the gate on voltage Von for the period of the supply of the first data voltage DV1, and the first scan signal SCAN1 may be supplied as the gate off voltage Voff for the period of the supply of the second data voltage DV2, so that the first data voltage DV1 may be supplied to the display pixels DPs connected to the first scan signals SCAN1.
Further, the second to pth scan signals SCAN2 to SCANp may be supplied for the period of the supply of the second data voltage DV2, and the second scan signal SCAN2 may be supplied as the gate off voltage Voff for the period of the supply of a third data voltage DV3, so that the second data voltage DV2 may be supplied to the display pixels DPs connected to the second scna signals SCAN2.
The gate off voltage Voff may correspond to a voltage capable of turning off the transistors of the display pixels and the auxiliary pixels. The gate on voltage Von may correspond to a voltage capable of turning on the transistors of the display pixels and the auxiliary pixels.
Referring to
The auxiliary line RL may be connected to the organic light emitting diode OLED of the jth display pixel DPj. In this case, the display pixel driver 110 and the organic light emitting diode OLED of the jth display pixel DPj are disconnected.
Each of the display pixels DP1 and DPj includes the organic light emitting diode OLED and the display pixel driver 110.
The display pixel driver 110 of each of the display pixels DP1 and DPj is connected to the organic light emitting diode OLED, and supplies a driving current to the organic light emitting diode OLED. However, the display pixel driver 110 and the organic light emitting diode OLED of the jth display pixel DPj corresponding to the repaired pixel are disconnected.
The display pixel driver 110 may be connected to the scan line, the A emission control line, the B emission control line, the control line, and a plurality of power lines. For example, the display pixel driver 110 may be connected the kth scan line SK, the data line D1/Dj, the kth A emission control line EAk, the kth B emission control line EBk, and the second and third power voltage lines VDDL and VINL2. A second power voltage is supplied to a second power voltage line VDDL, and a third power voltage is supplied to the third power voltage line VINL2. The second power voltage line may be a high potential voltage, and the third power voltage may be an initialization power voltage for initializing the display pixel driver 110.
The display pixel driver 110 may include a plurality of transistors. For example, the display pixel driver 110 may include first to fifth transistors T1, T2, T3, T4, and T5, and second and third capacitors C2 and C2.
The first transistor T1 controls a driving current (drain-source current Ids) according to a voltage of a control electrode thereof. The driving current Ids flowing through a channel of the first transistor T1 is in proportion to a square of a difference between a voltage between the control electrode and the first electrode of the first transistor T1 (a voltage between a gate and a source) and a threshold voltage as indicated in Equation 1.
I
ds
=k′·(Vgs−Vth)2 (1)
In Equation 1, K′ is a proportional coefficient determined by a structure and a physical property of a first transistor T1, Vgs is a voltage between a control electrode and a first electrode of the first transistor T1, and Vth is a threshold voltage of the first transistor T1.
A second transistor T2 is connected to the first electrode of the first transistor T1 and the data line D1/Dj. The second transistor T2 is turned on by a scan signal of the Kth scan line Sk to connect the first electrode of the first transistor T1 and the data line D1/Dj. Accordingly, the data voltage of the data line Dl/Dj is supplied to the first electrode of the first transistor T1. A control electrode of the second transistor T2 is connected to the kth scan line SK, a first electrode of the second transistor T2 is connected to the data line Dl/Dj, and a second electrode of the second transistor T2 is connected to the first electrode of the first transistor T1. The control electrode may be a gate electrode, the first electrode may be a source electrode or a drain electrode, and the second electrode may be an electrode different from the first electrode. For example, when the first electrode is a source electrode, the second electrode is a drain electrode.
A third transistor T3 is connected to the second power voltage line VDDL and the first electrode of the first transistor T1. The third transistor T3 is turned on by an emission control signal of the kth A emission control line EAk to connect the second power voltage line VDDL and the first electrode of the first transistor T1. Accordingly, a second power voltage is supplied to the first electrode of the first transistor T1. A control electrode of the third transistor T3 is connected to the kth emission control line Ek, a first electrode of the third transistor T3 is connected to the second power voltage line VDDL, and a second electrode of the third transistor T3 is connected to the first electrode of the first transistor T1.
A fourth transistor T4 is connected to the second electrode of the first transistor T1 and the organic light emitting diode OLED. The fourth transistor T4 is turned on by the emission control signal of the Kth A emission control line EAk to connect the second electrode of the first transistor T1 and the organic light emitting diode OLED. A control electrode of the fourth transistor T4 is connected to the kth A emission control line EAk, a first electrode of the fourth transistor T4 is connected to the second electrode of the first transistor T1, and a second electrode of the fourth transistor T4 is connected to the organic light emitting diode OLED.
When the third and fourth transistors T3 and T4 are turned on, the driving current Ids of the display pixel driver 110 is supplied to the organic light emitting diode OLED. Accordingly, the organic light emitting diode OLED of the first display pixel DP1 emits light.
The fifth transistor T5 is connected to the control electrode of the first transistor T1 and a third power voltage line VINL3 to which a third power voltage is supplied. The fifth transistor T5 is turned on by the scan signal of the Kth scan line Sk to connect the control electrode of the first transistor T1 and the third power voltage line VINL3. Accordingly, the control electrode of the first transistor T1 may be initialized with the third power voltage. A control electrode of the fifth transistor T5 is connected to the kth scan line Sk, a first electrode of the fifth transistor T5 is connected to the control electrode of the first transistor T1, and a second electrode of the fifth transistor T5 is connected to the third power voltage line VINL3.
The organic light emitting diode OLED emits according to the driving current Ids of the display pixel driver 110. The amount of emission of the organic light emitting diode OLED may be in proportion to the driving current Ids. An anode electrode of the organic light emitting diode OLED is connected to the second electrode of the fourth transistor T4, and a cathode electrode of the organic light emitting diode OLED is connected to the fourth power voltage line VSSL. A fourth power voltage is supplied to the fourth power voltage line VSSL.
The second capacitor C2 is connected to the control electrode and the first electrode of the first transistor T1. For example, one electrode of the second capacitor C2 is connected to the control electrode of the first transistor T1, and the other electrode of the second capacitor C2 is connected to the first electrode of the first transistor T1.
A third capacitor C3 is connected to the first electrode of the first transistor T1 and the second power voltage line VDDL. For example, one electrode of the third capacitor C3 is connected to the control electrode of the first transistor T1, and the other electrode of the third capacitor C3 is connected to the first electrode of the first transistor T1.
In
Each of the auxiliary pixels RP includes an auxiliary pixel driver 210, a discharge transistor DT, and a discharge transistor controller 220. Each of the auxiliary pixels RP1s does not include the organic light emitting diode OLED. The auxiliary pixel driver 210 is connected to the auxiliary line RL. Accordingly, the driving current of the auxiliary pixel driver 210 is supplied to the organic light emitting diode OLED of the jth display pixel DPj through the auxiliary line RL.
The display pixel driver 210 may be connected to the scan line, the auxiliary data line, the A emission control line, the B emission control line, and the plurality of power lines. For example, the display pixel driver 210 may be connected the kth scan line SK, the first auxiliary data line RD1, the kth A emission control line EAk, the kth B emission control line EBk, and the second and third power voltage lines VDDL and VINL2.
The auxiliary pixel driver 210 may include a plurality of transistors, e.g., first to fourth transistors T1′, T2′, T3′, and T4′. The first and third transistors T1′ and T3′ and second and third capacitors C2′ and C3′ of the auxiliary pixel driver 210 may be substantially or identically formed to the first and third transistors T1 and T3 and the second and third capacitors C2 and C3 of the display pixel driver 110.
The second transistor T2′ is connected to a first electrode of the first transistor T1′ and the first auxiliary data line RD1. The second transistor T2′ is turned on by the scan signal of the Kth scan line Sk to connect to the first electrode of the first transistor T1′ and the first auxiliary data line RD1. Accordingly, the auxiliary data voltage of the first auxiliary data line RD1 is supplied to the first electrode of the first transistor T1′. A control electrode of the second T2′ is connected to the kth scan line Sk, a first electrode of the second transistor T2′ is connected to the first auxiliary data line RD1, and a second electrode of the second transistor T2′ is connected to the first electrode of the first transistor T1′.
The fourth transistor T4′ is connected to a second electrode of the first transistor T1′. The fourth transistor T4′ is turned on by the emission control signal of the Kth B emission control line EBk to connect the second electrode of the first transistor T1′ and the auxiliary line RL. A control electrode of the fourth transistor T4′ is connected to the kth B emission control line EBk, a first electrode of the fourth transistor T4′ is connected to the second electrode of the first transistor T1′ and a second electrode of the fourth transistor T4′ is connected to the auxiliary line RL. When the third and fourth transistors T3′ and T4′ are turned on, a driving current Ids′ is supplied to the organic light emitting diode OLED of the jth display pixel DPj through the auxiliary line RL, so that the organic light emitting diode OLED of the jth display pixel DPj emits light.
The discharge transistor DT is connected to the auxiliary line RL and the first power voltage line VINL1. The first power voltage is supplied to the first power voltage line VINL1. The first power voltage may be an initialization power voltage for initializing the auxiliary line RL.
For example, the discharge transistor DT is turned on by the voltage supplied to the control electrode of the discharge transistor DT to connect the auxiliary line RL and the first power voltage line VINL1. Accordingly, the voltage of the auxiliary line RL is discharged with the first power voltage. For example, the discharge transistor DT serves to discharge the auxiliary line RL. The control electrode of the discharge transistor DT may be connected to the discharge transistor controller 220, a first electrode of the discharge transistor DT may be connected to the auxiliary line RL, and a second electrode of the discharge transistor DT may be connected to the first power voltage line VINL1.
The discharge transistor controller 220 controls turn-on and turn-off of the discharge transistor DT. The discharge transistor controller 220 may include a plurality of transistors and the first capacitor C1. For example, the discharge transistor controller 220 may include, for example, first and second discharge control transistors DCT1 and DCT2 and the first capacitor C1 as illustrated in
Each of the first and second discharge control transistors DCT1 and DCT2 is connected to the control electrode of the discharge transistor DT. In this case, a control electrode of the first discharge control transistor DCT1 and a control electrode of the second discharge control transistor DCT2 are connected to different lines.
For example, the first discharge control transistor DCT1 may be connected to the control electrode of the discharge transistor DT and the kth scan line Sk. The control electrode of the first discharge control transistor DCT1 may be connected to the kth control line CCLk, a first electrode of the first discharge control transistor DCT1 may be connected to the kth scan line Sk, and a second electrode of the first discharge control transistor DCT1 may be connected to the control electrode of the discharge transistor DT.
The second discharge control transistor DCT2 may be connected to the control electrode of the discharge transistor DT and the kth scan line Sk. The control electrode and the second electrode of second discharge control transistor DCT2 are connected to the kth scan line, and the first electrode of the second discharge control transistor DCT2 is connected to the control electrode of the discharge transistor DI. For example, the second discharge control transistor DCT2 is driven as a diode.
The first capacitor C1 is connected to the control electrode of the discharge transistor DT and the second power voltage line VDDL to maintain a voltage of the control electrode of the discharge transistor DT. One electrode of the first capacitor C1 is connected to the control electrode of the discharge transistor DT, and the other electrode of the first capacitor C1 is connected to the second power voltage line VDDL. The first capacitor C1 may be omitted in an another embodiment.
In
As described above, the display pixel driver 110 of the remaining display pixels DP1 except for the jth display pixel corresponding to the repaired pixel is connected to the organic light emitting diode OLED, and supplies the driving current to the organic light emitting diode OLED. However, the display pixel driver 110 of the jth display pixel DPj is not connected with the organic light emitting diode OLED. For example, since the display pixel driver 110 of the jth display pixel DPj may not properly perform its function due to a defect, the display pixel driver 110 and the organic light emitting diode OLED are disconnected, and the anode electrode of the organic light emitting diode OLED of the jth display pixel DI) is connected to the auxiliary line RL, for example, through a laser short-circuit process.
Accordingly, the anode electrode of the organic light emitting diode OLED of the jth display pixel DI) may be connected to the auxiliary pixel driver 210 of the first auxiliary pixel RP1 through the auxiliary line RL. As a result, the organic light emitting diode OLED of the jth display pixel DPj receives the driving current from the auxiliary pixel driver 210 of the first auxiliary pixel RP1 to emit light. Thus, the jth display pixel DPj may be repaired.
Further, FIG. illustrates only the first display pixel DP1 as one of the display pixels in which a defect is not generated. In one embodiment, each of the display pixels, in which a defect is not generated, may be substantially or identically implemented as the first display pixel DP1. Further,
The auxiliary line RL overlaps the anode electrodes of the organic light emitting diodes OLEDs of the display pixels, so that parasitic capacitance PC may be formed between the auxiliary line RL and the anode electrodes of the organic light emitting diodes OLEDs of the display pixels as illustrated in
In order to solve the problem, in accordance with one embodiment, the auxiliary line RL is discharged with the first power voltage using the discharge transistor DT. As a result, it is possible to prevent the voltage of the auxiliary line RL from varying by the parasitic capacitance PC and fringe capacitance FC. Accordingly, it is possible to prevent the organic light emitting diode OLED from erroneously emitting light. An example of this case is described with reference to
Referring to
Hereinafter, a driving method of the first auxiliary pixel RP1 and the jth display pixel DPj, and a driving method of the first display pixel DP1 will be described in detail with reference to
First, the first period t1 is a period for which an on-bias is applied to the first transistor T1. For the first period t1, the first scan signal SCAN1 of the gate on voltage Von is supplied to the pth scan line Sp. The first A emission control signal EMA1 of the gate on voltage Von is supplied to the first A emission control line EAk. The first B emission control signal EMB1 of the gate on voltage Von is supplied to the first B emission control line EBk. Accordingly, the second to fifth transistors T2, T3, T4, and T5 are turned on for the first period t1.
Because the second transistor T2 is turned on, the control electrode of the first transistor T1 is initialized with the initialized voltage Vref of the first data line D1. Because the third to fifth transistors T3, T4, and T5 are turned on, a current path is formed through which a current flows from the second power voltage line VDDL to the third power voltage line VINL2 via the third transistor T3, the first transistor T1, the fourth transistor T4, and the fifth transistor T5. The first transistor T1 may be implemented as a PMOS transistor, so that when a voltage difference Vgs between the control electrode and the first electrode of the first transistor T1 is smaller than a threshold voltage Vth of the first transistor T1, the first transistor T1 is turned on. The third power voltage VIN2 is set to be sufficiently lower than the second power voltage VDD, so that the voltage difference (Vgs=VIN2−VDD) between the control electrode and the first electrode of the first transistor T1 is smaller than the threshold voltage Vth of the first transistor T1 for the first period t1. Thus, current flows through the current path.
As a result, the control electrode of the first transistor T1 is discharged with the third power voltage and the on-bias may be applied to the first transistor T1 for the first period t1. Thus, it is possible to apply the on-bias to the first transistor T1 before the data voltage is supplied to the control electrode of the first transistor T1, thereby solving a problem in that an image quality deteriorates due to a hysteresis characteristic of the first transistor T1.
Second, the second period t2 is a period for which the threshold voltage of the first transistor is sampled. For the second period t2, the first scan signal SCAN1 of the gate on voltage Von is supplied to the first scan line S1, the pth scan signal SCANp of the gate on voltage Von is supplied to the pth scan line Sp, the first A emission control signal EMA1 of the gate off voltage Voff is supplied to the first A emission control line EAk, and the first B emission control signal EMB1 of the gate on voltage Von is supplied to the first B emission control line EBk. Accordingly, the second, fourth, and fifth transistors T2, T4, and T5 are turned on for the second period t2.
Because the second transistor T2 is turned on, the control electrode of the first transistor T1 is initialized with the initialized voltage Vref of the first data line D1. Because the third transistor T3 is turned off, the first electrode of the first transistor T1 is floated. Because a voltage difference (Vgs=VIN2−Vdata) between the control electrode and the first electrode of the first transistor T1 is smaller than the threshold voltage Vth for the second period t2, a current flows through the first transistor T1 until the voltage difference Vgs between the control electrode and the first electrode reaches the threshold voltage Vth of the first transistor T1. Accordingly, the voltage of the first electrode of the first transistor T1 is dropped to “VIN2−Vth,” for the second period t2.
Third, the third period t3 is a period for which the data voltage is supplied to the control electrode of the first transistor T1. For the third period t3, the first scan signal SCAN1 of the gate on voltage Von is supplied to the first scan line S1, the pth scan signal SCANp of the gate on voltage Von is supplied to the pth scan line Sp, the first A emission control signal EMA1 of the gate off voltage Voff is supplied to the first A emission control line EAk, and the first B emission control signal EMB1 of the gate off voltage Voff is supplied to the first B emission control line EBk. Accordingly, the second transistor T2 is turned on for the third period t3.
Because the second transistor T2 is turned on, the data voltage Vdata is supplied to the control electrode of the first transistor T1. In this case, a variation of the voltage of the control electrode of the first transistor T1 is reflected to the first electrode of the first transistor T1 by the second capacitor C2. Accordingly, the voltage of the first electrode of the first transistor T1 is changed to “VIN2−Vth+α”.
Fourth, the fourth period t4 is a period for which the sampling of the data voltage and the threshold voltage is completed. For the fourth period t4, the first scan signal SCAN1 of the gate off voltage Voff is supplied to the first scan line S1, the pth scan signal SCANp of the gate off voltage Voff is supplied to the pth scan line Sp, the first A emission control signal EMA1 of the gate on voltage Von is supplied to the first A emission control line EAk, and the first B emission control signal EMB1 of the gate off voltage Voff is supplied to the first B emission control line EBk. Accordingly, the third transistor T3 is turned on for the fourth period t4.
Because the third transistor T3 is turned on, the first electrode of the first transistor T1 is connected to the second power voltage line VDDL. Accordingly, the second power voltage is supplied to the first electrode of the first transistor T1 for the fourth period t4. In this case, a variation of the voltage of the first electrode of the first transistor T1 is reflected to the control electrode of the first transistor T1 by the second capacitor C2. However, the voltage difference Vgs between the control electrode and the first electrode of the first transistor T1 is maintained at “Vdata−(VIN2−Vth+α)”.
Fifth, the fifth period t5 is a period for which the organic light emitting diode OLED emits light. For the fifth period t5, the first scan signal SCAN1 of the gate off voltage Voff is supplied to the first scan line S1, the pth scan signal SCANp of the gate off voltage Voff is supplied to the pth scan line Sp, the first A emission control signal EMA1 of the gate on voltage Von is supplied to the first A emission control line EAk, and the first B emission control signal EMB1 of the gate on voltage Von is supplied to the first B emission control line EBk. Accordingly, the third and fourth transistors T3 and T4 are turned on for the fifth period t5.
Because the third and fourth transistors T3 and T4 are turned on, the driving current Ids flows through the first transistor T1 according to the voltage difference Vgs between the control electrode and the first electrode of the first transistor T1 for the fifth period t5. The voltage difference Vgs between the control electrode and the first electrode of the first transistor T1 is maintained at “Vdata−(VIN2−Vth+α)” for the fifth period t5. In this case, the driving current Ids flowing through the first transistor T1 may be defined as Equation 2.
I
ds
=k′·(Vgs−Vth)2=k′·[{Vdata−(VIN2−Vth+α)}−Vth]2 (2)
In Equation 2, k′ is a proportional coefficient determined by a structure and a physical property of the first transistor T1, Vgs is a voltage between the control electrode and the first electrode of the first transistor T1, is the threshold voltage of the first transistor T1, VIN2 is the third power voltage, and Vdata is the data voltage. The voltage difference between the control electrode and the first electrode of the first transistor T1 is “Vdata−(VIN2−Vth+α)”. When Equation 2 is simplified, Equation 3 is deduced.
I
ds
=k′·(Vdata−VIN2−α)2 (3)
Finally, the driving current Ids is not dependent on the threshold voltage Vth of the first transistor T1 as expressed by Equation 3. That is, the threshold voltage Vth of the first transistor T1 is compensated. The driving current Ids of the display pixel driver 110 is supplied to the organic light emitting diode OLED. Accordingly, the organic light emitting diode OLED emits light.
Sixth, the sixth period t6 is a period for which the organic light emitting diode OLED emits light. For the sixth period t6, the first scan signal SCAN1 of the gate off voltage Voff is supplied to the first scan line S1, the pth scan signal SCANp of the gate off voltage Voff is supplied to the pth scan line Sp, the first A emission control signal EMA1 of the gate on voltage Von is supplied to the first A emission control line EAk, and the first B emission control signal EMB1 of the gate on voltage Von is supplied to the first B emission control line EBk. Accordingly, the third and fourth transistors T3 and T4 are turned on for the sixth period t6.
Because the third and fourth transistors 13 and T4 are turned on for the sixth period t6, the organic light emitting diode OLED emits light similar to the fifth period t5.
Hereinafter, a driving method of the first auxiliary pixel RP1 and the jth display pixel DPj will be described in detail. First, the first period t1 is a period for which an on-bias is applied to the first transistor T1′.
For the first period t1, the first scan signal SCAN1 of the gate on voltage Von is supplied to the first scan line S1, the pth scan signal SCANp of the gate on voltage Von is supplied to the pth scan line Sp, the first A emission control signal EMA1 of the gate on voltage Von is supplied to the first A emission control line EAk, the first B emission control signal EMB1 of the gate on voltage Von is supplied to the first B emission control line EBk, and the voltage V_EMA_OUT2_QB of the full-down control node QB of the second A emission control signal output unit EMA_OUT2 of the gate off voltage Voff is supplied to the first control line CCL1. Accordingly, the second to fourth transistors T2′, T3′, and T4′ and the second discharge control transistor DCT2 are turned on for the first period t1.
Because the second discharge control transistor DCT2 is turned on, the control electrode of the discharge transistor DT is increased to have a voltage difference (Von−Vth
Because the second transistor T2′ is turned on, the control electrode of the first transistor T1′ is initialized with the initialized voltage Vref of the first data line D1. Because the third and fourth fifth transistors T3′ and T4′, and the discharge transistor DT are turned on, a current path, through which a current flows from the second power voltage line VDDL to the first power voltage line VINL1 via the third transistor T3′, the first transistor T1′, the fourth transistor T4′, and the discharge transistor DT, is formed.
For example, the first transistor T1′ is implemented as a PMOS transistor, so that when a voltage difference Vgs between the control electrode and the first electrode of the first transistor T1′ is smaller than a threshold voltage Vth of the first transistor T1′ (Vgs<Vth), the first transistor T1′ is turned on. The third power voltage VIN2 is set to be sufficiently lower than the second power voltage VDD, so that the voltage difference (Vgs=VIN2−VDD) between the control electrode and the first electrode of the first transistor T1 is smaller than the threshold voltage Vth of the first transistor T1′ for the first period t1, and thus the current flows through the current path.
As a result, the control electrode of the first transistor T1′ is discharged with the third power voltage and the on-bias may be applied to the first transistor T1′ for the first period t1. Thus, it is possible to apply the on-bias to the first transistor T1′ before the data voltage is supplied to the control electrode of the first transistor T1′, thereby solving a problem in that an image quality deteriorates due to a hysteresis characteristic of the first transistor T1′.
Second, the second period t2 is a period for which the threshold voltage of the first transistor′ is sampled. For the second period t2, the first scan signal SCAN1 of the gate on voltage Von is supplied to the first scan line S1, the pth scan signal SCANp of the gate on voltage Von is supplied to the pth scan line Sp, the first A emission control signal EMA1 of the gate off voltage Voff is supplied to the first A emission control line EAk, the first B emission control signal EMB1 of the gate on voltage Von is supplied to the first B emission control line EBk, and the voltage V_EMA_OUT2_QB of the full-down control node QB of the second A emission control signal output unit EMA_OUT2 of the gate off voltage Voff is supplied to the first control line CCL1. Accordingly, the second and fourth transistors T2′ and T4′ and the second discharge control transistor DCT2 are turned on for the second period t2.
Because the second discharge control transistor DCT2 is turned on, the control electrode of the discharge transistor DT maintains a voltage difference (Von−Vth
Because the second transistor T2′ is turned on, the control electrode of the first transistor T1′ is initialized with the initialized voltage Vref of the first data line D1. Because the third transistor T3′ is turned off, the first electrode of the first transistor T1′ is floated. Since a voltage difference (Vgs=VIN2−Vdata) between the control electrode and the first electrode of the first transistor T1′ is smaller than the threshold voltage Vth for the second period t2, a current flows through the first transistor T1′ until the voltage difference Vgs between the control electrode and the first electrode reaches the threshold voltage Vth of the first transistor T1′. Accordingly, the voltage of the first electrode of the first transistor T1′ is dropped to “VIN2−Vth” for the second period t2.
Third, the third period t3 is a period for which the data voltage is supplied to the control electrode of the first transistor T1′. For the third period t3, the first scan signal SCAN1 of the gate on voltage Von is supplied to the first scan line S1, the pth scan signal SCANp of the gate on voltage Von is supplied to the pth scan line Sp, the first A emission control signal EMA1 of the gate off voltage Voff is supplied to the first A emission control line EAk, the first B emission control signal EMB1 of the gate off voltage Voff is supplied to the first B emission control line EBk, and the voltage V_EMA_OUT2_QB of the full-down control node QB of the second A emission control signal output unit EMA_OUT2 of the gate off voltage Voff is supplied to the first control line CCL1. Accordingly, the second transistor T2 and the second discharge control transistor CDT2 are turned on for the third period t3.
Because the second discharge control transistor DCT2 is turned on, the control electrode of the discharge transistor DT maintains a voltage difference (Von−Vth
Because the second transistor T2′ is turned on, the data voltage Vdata is supplied to the control electrode of the first transistor T1′. In this case, a variation of the voltage of the control electrode of the first transistor T1′ is reflected to the first electrode of the first transistor T1′ by the second capacitor C2′. Accordingly, the voltage of the first electrode of the first transistor T1′ is changed to “VIN2−Vth+α”.
Because the first scan line S1 and the auxiliary line RL are formed to be parallel to each other, the fringe capacitance FC illustrated in
Fourth, the fourth period t4 is a period for which the sampling of the data voltage and the threshold voltage is completed. For the fourth period t4, the first scan signal SCAN1 of the gate off voltage Voff is supplied to the first scan line S1, the pth scan signal SCANp of the gate off voltage Voff is supplied to the pth scan line Sp, the first A emission control signal EMA1 of the gate on voltage Von is supplied to the first A emission control line EAk, the first B emission control signal EMB1 of the gate off voltage Voff is supplied to the first B emission control line EBk, and the voltage V_EMA_OUT2_QB of the full-down control node QB of the second A emission control signal output unit EMA_OUT2 of the gate off voltage Voff is supplied to the first control line CCL1. Accordingly, the third transistor T3 is turned on for the fourth period t4.
Even though the second discharge control transistor DCT2 is turned on for the fourth period t4, the control electrode of the discharge transistor DT maintains a voltage difference (Von−Vth
Because the third transistor T3 is turned on, the first electrode of the first transistor T1 is connected to the second power voltage line VDDL. Accordingly, the second power voltage is supplied to the first electrode of the first transistor T1 for the fourth period t4. In this case, a variation of the voltage of the first electrode of the first transistor T1 is reflected to the control electrode of the first transistor T1 by the first capacitor C1. However, the voltage difference Vgs between the control electrode and the first electrode of the first transistor T1 is maintained at “Vdata−(VIN2−Vth+α)”.
Fifth, the fifth period t5 is a period for which the auxiliary line RL is discharged with the first power voltage. For the fifth period t5, the first scan signal SCAN1 of the gate off voltage Voff is supplied to the first scan line S1, the pth scan signal SCANp of the gate off voltage Voff is supplied to the pth scan line Sp, the first A emission control signal EMA1 of the gate on voltage Von is supplied to the first A emission control line EAk, the first B emission control signal EMB1 of the gate on voltage Von is supplied to the first B emission control line EBk, and the voltage V_EMA_OUT2_QB of the full-down control node QB of the second A emission control signal output unit EMA_OUT2 of the gate off voltage Voff is supplied to the first control line CCL1. Accordingly, the third and fourth transistors 13 and T4′ are turned on for the fifth period t5.
Even though the second discharge control transistor DCT2 is turned off for the fifth t5, the control electrode of the discharge transistor DT maintains a voltage difference (Von−Vth
Because the third and fourth transistors T3′ and T4′ are turned on, the driving current Ids flows through the first transistor T1 according to the voltage difference Vgs between the control electrode and the first electrode of the first transistor T1 for the fifth period t5. The voltage difference Vgs between the control electrode and the first electrode of the first transistor T1′ is maintained at “Vdata−(VIN2−Vth+α)” for the fifth period t5. In this case, the driving current Ids flowing through the first transistor T1′ may be defined as Equation 2. When Equation 2 is simplified, Equation 3 is deduced.
Finally, the driving current Ids is not dependent on the threshold voltage Vth of the first transistor T1 as expressed by Equation 3. That is, the threshold voltage Vth of the first transistor T1′ is compensated.
However, the auxiliary line RL is connected to the first power voltage line VINL1 by the turn-on of the discharge transistor DT, the driving current Ids of the auxiliary pixel driver 210 is discharged to the first power voltage line VINL1 through the discharge transistor DT. Accordingly, the organic light emitting diode OLED of the jth display pixel DPj does not emit light for the fifth period t5.
The auxiliary line RL overlaps the anode electrodes of the organic light emitting diodes OLEDs of the display pixels DP1, so that parasitic capacitance PC may be formed between the auxiliary line RL and the anode electrodes of the organic light emitting diodes OLEDs of the display pixels DP1 as illustrated in
However, the auxiliary line RL is connected to the first power voltage line VINL1 for the fifth period t5, so that even though the voltage change of the anode electrodes of the organic light emitting diodes OLEDs of the display pixels DP1 is reflected by the fringe capacitance FC, the auxiliary line RL is discharged with the first power voltage VIN1.
Sixth, the sixth period t6 is a period for which the organic light emitting diode OLED emits light. For the sixth period t6, the first scan signal SCAN1 of the gate off voltage Voff is supplied to the first scan line S1, the pth scan signal SCANp of the gate off voltage Voff is supplied to the pth scan line Sp, the first A emission control signal EMA1 of the gate on voltage Von is supplied to the first A emission control line EAR, the first B emission control signal EMB1 of the gate on voltage Von is supplied to the first B emission control line EBk, and the voltage V_EMA_OUT2_QB of the full-down control node QB of the second A emission control signal output unit EMA_OUT2 of the gate on voltage Von is supplied to the first control line CCL1. Accordingly, the third and fourth transistors T3′ and T4′ and the first discharge control transistor DCT1 are turned on for the sixth period t6.
Because the first discharge control transistor DCT1 is turned on, the first scan signal SCAN1 of the gate off voltage Voff is supplied to the control electrode of the discharge transistor DT. Accordingly, the discharge transistor DT is turned off. Accordingly, the auxiliary line RL is not connected to the first power voltage line VINL1.
Further, because the third and fourth transistors T3′ and T4′ are turned on, the driving current Ids' of the auxiliary pixel driver 210 is supplied to the organic light emitting diode OLED of the jth display pixel DPj through the auxiliary line RL. Accordingly, the organic light emitting diode OLED of the jth display pixel DPj emits light.
As described above, in the present embodiment, it is possible to prevent the voltage of the auxiliary line RL from being varied by the parasitic capacitance PC and the fringe capacitance FC. As a result, it is possible to prevent the organic light emitting diode OLED of the jth display pixel DPj from erroneously emitting light by the parasitic capacitance PC and the fringe capacitance FC.
Referring to
The auxiliary line RL may be connected to the organic light emitting diode OLED of the jth display pixel DPj. In this case, the display pixel driver 110 and the organic light emitting diode OLED of the jth display pixel DPj disconnected.
Each of the display pixels DP1 and DPj includes the organic light emitting diode OLED and the display pixel driver 110. The display pixels DP1 and DPj in
The first auxiliary pixel RP1 includes an auxiliary pixel driver 210, a discharge transistor DT, and a discharge transistor controller 220. The first auxiliary pixel RP1 does not include an organic light emitting diode OLED.
The auxiliary pixel driver 210 and the discharge transistor DT of the first auxiliary pixel RP1 in
The discharge transistor controller 220 controls turn-on and turn-off of the discharge transistor DT. The discharge transistor controller 220 may include a plurality of transistors and a first capacitor C1. For example, the discharge transistor controller 220 may include first and second discharge control transistors DCT1 and DCT2 and the first capacitor C1 as in
Each of the first and second discharge control transistors DCT1 and DCT2 is connected to a control electrode of the discharge transistor DT. In this case, a control electrode of the first discharge control transistor DCT1 and a control electrode of the second discharge control transistor DCT2 are connected to different lines.
For example, the first discharge control transistor DCT1 may be connected to the control electrode of the discharge transistor DT and a gate off voltage line VOFFL. The control electrode of the first discharge control transistor DCT1 may be connected to the kth control line CCLk, a first electrode of the first discharge control transistor DCT1 may be connected to the gate off voltage line VOFFL, and a second electrode of the first discharge control transistor DCT1 may be connected to the control electrode of the discharge transistor DT.
The second discharge control transistor DCT2 may be connected to the control electrode of the discharge transistor DT and a gate on voltage line VONL. The control electrode of the second discharge control transistor DCT2 may be connected to the kth scan line Sk, a first electrode of the second discharge control transistor DCT2 may be connected to the control electrode of the discharge transistor DT, and a second electrode of the second discharge control transistor DCT2 may be connected to the gate off voltage line VONL.
The first capacitor C1 is connected to the control electrode of the discharge transistor DT and the second power voltage line VDDL to maintain a voltage of the control electrode of the discharge transistor DT. One electrode of the first capacitor C1 is connected to the control electrode of the discharge transistor DT, and the other electrode of the first capacitor C1 is connected to the second power voltage line VDDL. The first capacitor C1 may be omitted.
The signals supplied to the display pixels DP1 and DPj and the auxiliary pixel RP1 in
The methods, processes, and/or operations described herein may be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device may be those described herein or one in addition to the elements described herein. Because the algorithms that form the basis of the methods (or operations of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments may transform the computer, processor, controller, or other signal processing device into a special-purpose processor for performing the methods described herein.
Also, another embodiment may include a computer-readable medium, e.g., a non-transitory computer-readable medium, for storing the code or instructions described above. The computer-readable medium may be a volatile or non-volatile memory or other storage device, which may be removably or fixedly coupled to the computer, processor, controller, or other signal processing device which is to execute the code or instructions for performing the method embodiments described herein.
By way of summation and review, during manufacturing of a display, a defect may occur for one or more of transistors of the pixels. As a result, manufacturing yield deteriorates. In an attempt to solve this problem, a method has been proposed to repair a defective pixel by forming auxiliary pixels in an organic light emitting display device and connecting the defective pixel to any one of the auxiliary pixels. However, in this method, parasitic capacitance may form between an auxiliary line and an anode electrode of an OLED in a pixels. Also, fringe capacitance may form between the auxiliary line and an adjacent scan line. In this case, a voltage of the auxiliary line may be changed by the parasitic capacitance and the fringe capacitance, and thus the OLED of the repaired pixel may erroneously emit light.
In accordance with one or more of the aforementioned embodiments, the auxiliary line is discharged with the first power voltage using a discharge transistor. As a result, it is possible to prevent a voltage of the auxiliary line from varying by parasitic capacitance between an auxiliary line and an anode electrode of an OLED in a display pixel and by fringe capacitance between the auxiliary line and a scan line adjacent to the auxiliary line. Accordingly, it is possible to prevent the OLEDs in the display from erroneously emitting light.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.
Number | Date | Country | Kind |
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10-2014-0122730 | Sep 2014 | KR | national |