Patent Grant
10181286
This application claims the benefit of Korea Patent Application No. 10-2015-0123258 filed on Aug. 31, 2015, the entire contents of which is incorporated herein by reference for all purposes as if fully set forth herein.
Field of the Invention
The present disclosure relates to a display device and a method of driving the same.
Discussion of the Related Art
With reduced size and weight, flat panel displays (FPDs) have been extensively used in portable computers such as notebook computers or personal digital assistants (PDAs), as well as monitors of a desktop computers, or mobile terminals. Such flat panel displays include a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), and an organic light emitting display device.
An organic light emitting display device, among flat panel displays, has high response speed and is advantageous in terms of luminous efficiency, brightness, and viewing angle. In general, in an organic light emitting display device, a data voltage is received through a driving transistor that is turned on by a scan signal, and the received data voltage is charged in a storage capacitor. Also, the data voltage charged in the storage capacitor is output to an organic light emitting diode (OLED) by using an emission control signal to thereby emit light.
The demand for high-resolution display devices is increasing. As display devices are implemented with a high resolution, designing driving circuits for driving display devices may become complicated, and such driving circuits may become more susceptible to noise.
Accordingly, the present invention is directed to a display device and a method of driving the same that substantially obviate one or more problems due to limitations and disadvantages of the related art.
An advantage of the present invention is to provide a display device with improved circuit design.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. These and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a display device may, for example, include a display panel in which a data line and a scan line are disposed; a driving circuit configured to supply a data voltage to the data line, control an operation timing of a scan pulse applied to the scan line, and output a voltage output control signal to a signal transmission line; and a power module circuit configured to generate one or more of first and second driving voltages in response to the voltage output control signal received from the signal transmission line, wherein the voltage output control signal includes a preparation field and a channel selection field, wherein the power module circuit recognizes the voltage output control signal in response to the preparation field, and outputs the one or more of the first and second driving voltages to the driving circuit in response to the channel selection field.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:
Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Like reference numerals refer to like elements throughout. In describing the present invention, if a detailed explanation for a related known function or construction is considered to unnecessarily divert the gist of the present invention, such explanation will be omitted but would be understood by those skilled in the art.
Referring to
The display panel 100 includes a display region 100A in which a plurality of pixels P are disposed to display an image and a non-display region 100B, outside the display region 100A, in which various signal lines or signal pads are formed. Each pixel P is connected to a data line part DL and a gate line part SL and EL, crossing each other. The data line part DL includes an initialization line 14a and a data voltage supply line 14b, and the gate line part SL and EL includes a scan line SL and an emission line EL.
Each pixel P includes an OLED, a driving transistor DT, first to third transistors T1, T2, and T3, a storage capacitor Cst, and an auxiliary capacitor Csub. The driving transistor DT and the first to third transistors T1, T2, and T3 may be implemented as an oxide thin film transistor (TFT) including an oxide semiconductor layer.
A gate driver 40 applies a scan pulse SCAN to the scan lines SL disposed in the display region 100A and applies an emission control signal EM to an emission line EL. The gate driver 40 may be formed together with the array of pixels on a lower substrate of the display panel 100 through a gate-in-panel (GIP) process.
The driving circuit D-IC writes data of an input image into pixels. The driving circuit D-IC may include functions of a data driver and a timing controller.
The driving circuit D-IC receives image data and timing signals in synchronization with the image data from a host (not shown). The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock CLK.
The driving circuit D-IC converts the image data into positive polarity/negative polarity data voltages using positive polarity/negative polarity gamma compensation voltages and subsequently outputs the positive polarity/negative polarity data voltages to the data line part DL.
The driving circuit D-IC transmits a voltage output control signal GPO to the power module P-IC, and receives first and second driving voltages DDVDH and ELVDD generated by the power module P-IC. Timing and operation of the voltage output control signal GPO will now be described with reference to
As described above, the pixel P according to an embodiment of the present disclosure includes an organic light emitting diode (OLED), a driving transistor DT, first to third transistors T1 to T3, a storage capacitor Cst, and an auxiliary capacitor Csub.
The OLED emits an amount of light in accordance with a driving current supplied from the driving transistor DT. Multiple organic compound layers may be formed between an anode and a cathode of the OLED. The organic compound layers may include a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the OLED may be connected to a source electrode of the driving transistor DT, and the cathode electrode thereof may be connected to a ground terminal VSS.
The driving transistor DT controls an amount of driving current applied to the OLED based on a voltage between a gate electrode and a source electrode thereof. A gate electrode of the driving transistor DT is connected to a first node n1, a drain electrode thereof is connected to a source electrode of the first transistor T1, and a source electrode thereof is connected to a second node n2.
In response to the emission control signal EM, the first transistor T1 controls a current path between an input terminal of the first driving voltage ELVDD and the driving transistor DT. To this end, a gate electrode of the first transistor T1 is connected to the emission line EL, a drain electrode thereof is connected to a second channel CH2 to receive the second driving voltage ELVDD, and a source electrode thereof is connected to a drain electrode of the driving transistor DT.
In response to a scan signal SCAN[n−1] of a previous stage, the second transistor T2 provides an initialization voltage Vini provided through the initialization line 14a to the second node n2. To this end, a gate electrode of the second transistor T2 is connected to a scan line SL[n−1] of the previous stage, a drain electrode thereof is connected to the initialization line 14a, and a source electrode thereof is connected to the second node n2.
In response to a scan signal SCAN[n] of the current stage, the third transistor T3 provides a reference voltage Vref or a data voltage Vdata provided from the data voltage supply line 14b to the driving transistor DT. To this end, a gate electrode of the third transistor T3 is connected to a gate line SLn of the current stage, a drain electrode thereof is connected to the data voltage supply line 14b, and a source electrode thereof is connected to the driving transistor DT.
The storage capacitor Cst serves to maintain the data voltage Vdata provided from the data voltage supply line 14b during one frame period to enable the driving transistor DT to maintain a constant voltage. To this end, both electrodes of the storage capacitor Cst are connected to the gate electrode and the source electrode of the driving transistor DT, respectively. The auxiliary capacitor Csub serves to enhance efficiency of the data voltage Vdata, and both electrodes of the auxiliary capacitor Csub are connected to the second node n2 and the input terminal of the second driving voltage ELVDD.
An operation of the pixel P will be described with reference to
Referring to
During the initialization period T1, in response to a scan signal SCAN[n−1] of the previous stage, the second transistor T2 supplies the initialization voltage Vini provided from the initialization line 14a to the second node n2. Also, in response to the scan signal SCAN[n] of the current stage, the third transistor T3 supplies the reference voltage Vref provided from the data voltage supply line 14b to the first node n1. The initialization voltage Vini supplied to the second node n2 during the initialization period T1 is to initialize the pixel P to a predetermined level. The initialization voltage Vini beneficially has a voltage value lower than that of an operating voltage of the OLED so that the OLED does not emit light. For example, the initialization voltage Vini may be set to a voltage ranging from −1 to +1 (V).
During the sampling period Ts, in response to the scan signal SCAN[n] of the current stage, the third transistor T3 supplies the reference voltage Vref provided from the data voltage line 14b to the first node n1. In response to the emission control signal EM, the first transistor T1 supplies the second driving voltage ELVDD to the driving transistor DT. Here, a gate electrode voltage Vg of the driving transistor maintains the reference voltage Vref. The second node n2 has a voltage increased as the current flowing to the source electrode of the driving transistor DT through the drain electrode thereof is accumulated. The voltage of the second node n2 increased during the sampling period Ts is saturated to a voltage corresponding to a difference between the reference voltage Vref and a threshold voltage Vth of the driving transistor DT. As a result, during the sampling period Ts, a potential difference between the gate and source electrodes of the driving transistor DT is substantially equal to the threshold voltage Vth.
During the writing period Tw, the first and second transistors T1 and t2 are turned off. Also, while being turned on, the third transistor T3 supplies the data voltage Vdata provided from the data voltage supply line 14b to the first node n1. Here, the voltage of the second node n2 in a floating state is coupled according to a ratio of the storage capacitor Cst and the auxiliary capacitor Csub so as to be increased or decreased.
During the emission period Te, the second transistor T2 is maintained in a turn-off state, the third transistor T3 is turned off, and the first transistor T1 is turned on. During the emission period Te, the data voltage Vdata stored in the storage capacitor Cst is supplied to the OLED, and thus, the OLED emits light with brightness in proportion to the data voltage Vdata. Here, an amount of current flows in the driving transistor DT in accordance with a voltage between the first node n1 and the second node n2 determined during the writing period Tw, and the amount of current passing through the source electrode of the driving transistor DT is supplied to the OLED. As a result, the OLED emits light with brightness in proportion to the data voltage Vdata.
A process of generating the first driving voltage DDVDH and a second driving voltage ELVDD will now be described with reference to
When power is supplied to a display device in a sleep-in state to operate it in a sleep-out state, the driving circuit D-IC is provided with a vertical synchronization signal Vsync from a host (not shown). The driving circuit D-IC transmits a voltage output control signal (or a general purpose output (GPO)) to the power module P-IC at a time synchronized with the vertical synchronization signal Vsync.
The voltage output control signal GPO includes a first control field Field1 and a second control field Field2. The first control field Field1 is synchronized with a start time of a first frame, and the second control field Field2 is synchronized with a start time of a frame which has elapsed for a predetermined period of time after a termination of the first control field Field1.
As illustrated in (a) of
In response to the first control field Field1, the power module P-IC generates a first driving voltage DDVDH and outputs the generated first driving voltage DDVDH to a first channel CH1. In detail, the power module P-IC recognizes the voltage output control signal GPO in response to the first preparation field T11. After checking the first channel selection field T12, the power module P-IC outputs the first driving voltage DDVDH to the first channel CH1. A voltage level of the first driving voltage DDVDH at a point in time at which the first channel selection field T11 terminates is previously set or predetermined as a default value.
The driving circuit D-IC supplies the first driving voltage DDVDH supplied through the first channel CH1, and a buffer of the driving circuit D-IC outputs the data voltage Vdata using the first driving voltage DDVDH.
The first voltage level setting field T13 starts after the lapse of a predetermined period of time since the first channel selection field T12 is terminated. In detail, the first voltage level setting field T13 starts, for example, after one frame period has lapsed from a start point of the first channel selection field T12. The power module P-IC varies a voltage level of the first driving voltage DDVDH transmitted immediately after a termination of the first preparation field T11 according to the first voltage level setting field T12. Upon checking the first voltage level setting field T13, the power module P-IC varies a voltage level of the first driving voltage DDVDH at a point in time at which the first voltage level setting field T13 terminates. An embodiment in which the power module P-IC varies the voltage level will now be described.
The driving circuit D-IC generates the data voltage Vdata using the first driving voltage DDVDH of a varied voltage level transmitted after the first voltage level setting field T13.
The voltage output control signal GPO has a hold field of a predetermined frame period after the first control field Field1 terminates. After the hold field has lapsed, the second control field Field2 starts, for example, at a point in time at which a fifth frame starts.
In response to the second control field Field2, the power module P-IC generates a second driving voltage ELVDD and outputs the generated second driving voltage ELVDD through the second channel CH2. In detail, the power module P-IC checks the second preparation field T21 to recognize the voltage output control signal GPO. After checking the second channel selection field T22, the power module P-IC outputs the second driving voltage ELVDD through the second channel CH2 at a point in time at which the second channel selection field T22 terminates.
The driving circuit D-IC adds the second driving voltage ELVDD supplied through the second channel CH2 and the first driving voltage DDVDH supplied through the first channel CH1 to generate a gate high voltage VGH. The gate high voltage VGH is supplied to the gate driver 40 of the display panel 100. Also, the driving circuit D-IC supplies the second driving voltage ELVDD to the pixel array of the display panel 100.
The second voltage level setting field T22 starts, for example, after one frame period has lapsed from a time point of the second channel selection field T21. In response to the second voltage level setting field T23, the power module P-IC varies a voltage level of the second driving voltage ELVDD transmitted as a default vale. That is, after checking the second voltage level setting field T23, the power module P-IC varies a voltage level of the second driving voltage ELVDD at a point in time at which the second voltage level setting field T23 terminates.
A method for the power module P-IC to recognize the voltage output control signal GPO illustrated in
The first preparation field T11 and the second preparation field T21 of the voltage output control signal GPO include a pulse stream. Similarly, the first and second channel selection fields T12 and T22 and the first and second voltage level setting fields T13 and T23 also include a pulse stream.
The power module P-IC detects a pulse stream and counts the detected pulse stream. In a state in which a count value corresponding to an accumulation value of the pulse stream and a control command corresponding to the count value are stored in a look-up table (LUT), the power module P-IC searches for a count value corresponding to the accumulation value and performs a control command corresponding to the searched count value.
In a state in which a count value corresponding to a pulse stream is set in advance, when the power module P-IC calculates an accumulation value of the pulse stream corresponding thereto, the power module P-IC recognizes the corresponding field as the first preparation field T11. Alternatively, in a state in which a count value corresponding to a pulse stream of the second preparation field t21 is set in advance, when the power module P-IC calculates an accumulation value of a pulse stream corresponding thereto, the power module P-IC recognizes the corresponding field as the second preparation field T21. When the power module P-IC checks the first preparation field T11 or the second preparation field T21, the power module P-IC recognizes a continued pulse stream as a channel selection field.
Similarly, the power module P-IC counts a pulse stream transmitted after the preparation field, and compares an accumulation value of the counted pulse stream with a count value stored in the LUT. The power module P-IC performs a control command corresponding to the count value.
Table 1 illustrates an example of the LUT storing count values and control commands correspond thereto. In Table 1, logic represents a logic configuration of a pulse stream of a voltage output control signal capable of matching a corresponding count vale. For logic values, “0” denotes a signal of a low level voltage, and “1” denotes a signal of a high level voltage. Thus, the power module P-IC counts, for example, the number as a pulse of one time when the logic values of “0” and “1” alternate.
Referring to Table 1, when an accumulation value of pulses counted in the channel selection fields T12 and T22 is 1, the power module P-IC searches for the same count value as the corresponding accumulation value, and performs a control command corresponding to the searched accumulation value. That is, when a pulse stream of logic “01” is checked, the power module P-IC outputs the first driving voltage DDVDH via the first channel CH1. Similarly, when the power module P-IC detects logic values of “0101” in the channel selection fields T12 and T22, the power module P-IC outputs the second driving voltage ELVDD via the second channel CH2. When logic values of “010101” are detected, the power module P-IC outputs the first driving voltage DDVDH via the first channel CH1 and outputs the second driving voltage ELVDD via the second channel CH2.
The channel selection fields T12 and T22 of the voltage output control signal GPO may further include a logic for preparing for setting of a voltage level. When logic values of the channel selection fields T12 and T22 are “01010101”, the power module P-IC varies a voltage level of the first driving voltage DDVDH output via the first channel CH1 during the voltage level setting fields T13 and T23. Also, when logic values of the channel selection fields T12 and T12 are “0101010101”, the power module P-IC varies a voltage level of the second driving voltage ELVDD output via the second channel CH2 during the voltage level setting fields T13 and T23.
Table 2 illustrates an LUT for setting the first driving voltage DDVDH during the voltage level setting field, and Table 3 illustrates an LUT for setting a second driving voltage ELVDD during the voltage level setting field.
Referring to Table 2, since the count values 1 to 5 correspond to logic values used in the channel selection fields T12 and T22, these count values are not used in the first voltage level setting field T13. When an accumulation value of the counted pulses is “7”, the power module P-IC searches for the count value “7” from the LUT and sets a voltage level of the first driving voltage DDVDH to 3.6V. In this way, the power module P-IC varies a voltage level of the first driving voltage DDVDH according to an accumulation value of counted pulses.
Referring to Table 3, since count values from “1” to “5” correspond to logic values used during the channel selection fields T12 and T22, these count values are not used during the second voltage level setting field T23. As in the first voltage level setting field T13, the power module P-IC varies a voltage level of the second driving voltage ELVDD on a basis of the LUT illustrated in Table 3 during the second voltage level setting field T23.
As discussed above, the power module P-IC may control output timing and voltage levels of the first and second driving voltages DDVDH and ELVDD respectively supplied to the first channel CH1 and the second channel CH2 using a voltage output control signal GPO transmitted from a signal transmission line GPO_L.
Since the power module P-IC controls an output of a driving voltage using the signal transmission line GPO_L, the power module P-IC may be easily disposed outside the driving circuit D-IC. When the power module P-IC generates a driving voltage, a noise may be generated. Since the power module P-IC can be disposed outside the driving circuit D-IC, a noise generated in the power module P-IC may not affect the driving circuit D-IC according to an embodiment.
In particular, since the power module P-IC according to an embodiment may not require two signal transmission lines to receive a signal for controlling an output of a driving voltage provided to the first channel CH1 and the second channel CH2, the number of the signal transmission lines GPO_L may be reduced. Such a reduction in the number of signal transmission lines is advantageous in circuit design and can be advantageously applied to a portable display device due to its reduced size.
The voltage output control signal GPO illustrated in
Referring to Table 4, when an accumulation value of counted pulses is “1” to “3”, the power module P-IC supplies a driving voltage to any one of first to third channels corresponding to each of the counted values. When an accumulation value of counted pulses is “4” to “6”, the power module P-IC supplies a driving voltage to two channels among the first to third channels. When an accumulation value of counted pulses is “7”, the power module P-IC supplies a driving voltage to the first to third channels.
When an accumulation value of counted pulses is “8”, the power module P-IC varies a voltage output to the first channel during the voltage level setting field. Also, when an accumulation value of counted pulses is “9”, the power module P-IC varies a voltage output supplied to the second channel, and when an accumulation value of counted pulses is “10”, the power module P-IC varies a voltage output supplied to the third channel.
In this manner, since the power module P-IC according to an embodiment of the present disclosure controls a driving voltage output via three channels through a single signal transmission line, it can be advantageous in circuit design and a display device may be further reduced in size.
Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2015-0123258 | Aug 2015 | KR | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20120293479 | Han | Nov 2012 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20170061870 A1 | Mar 2017 | US |
