Patent Application
20070262297
The present invention relates generally to an organic thin-film transistor (O-TFT) device.
More specifically, an embodiment of the invention relates to an organic thin-film transistor device integrated on a substrate and including at least an organic active layer and metallic contact regions realized on an insulating layer.
Another embodiment of the invention further relates to a process for manufacturing an organic thin-film transistor device on a substrate.
As it is well known, in recent years there has been a growing interest in organic thin-film transistors, usually indicated as O-TFT device. This increased interest is mainly due to attractive features of these kind of transistors, such as low cost, low-temperature processing, and mechanical flexibility, the former being essentially linked to the use of organic materials, cheaper than the integrated inorganic ones.
O-TFT devices have been realized on a variety of substrates, including silicon, glass, or plastics, and different organic active layers have been investigated, as described in the following articles:
It is also known in the field that pentacene is the organic layer which realizes an active layer having good performance.
Moreover, the performance of such O-TFT devices are dependent on their gate structure, and more particularly, to the material to be used for forming the gate insulator layer.
Different dielectric materials can be employed as a gate insulator layer, both inorganic [such as, SiO2, Si3N4, Al2O3] and organic [such as poly(4-vinylphenol) (PVP), polyimide, parylene, polyaniline (PANI)].
Recent works have shown that using organic dielectrics as gate insulator layer, very high values for the field-effect mobility of the O-TFT device have been obtained, even higher than those obtained with inorganic dielectrics as gate insulator layers, although inorganic dielectric materials provide lower leakage current and lower hysteresis.
The best solution for an O-TFT device nowadays is a pentacene-based thin-film transistor coupled with both inorganic and organic gate dielectrics.
However, it has also been found that the interaction of π-conjugated pentacene with metal contact or gate dielectric surfaces, strongly affects the growth process and affects the morphology of the organic film so realized.
Referring to
The O-TFT device 10 comprises a thick oxide protective layer 1 whereon a gate region 2 is formed, as well as a gate insulating layer 3, the latter covering both the gate region 2 and the thick oxide protective layer 1.
On the gate insulating layer 3 a drain contact region 4 and a source contact region 5 are then realized, spaced apart from each other and define therebetween a intermediate region 3A of the gate insulating layer 3 which is substantially aligned with the gate region 2.
The O-TFT device 10 further comprises an organic active layer 6, preferably a pentacene layer, which is deposited over the drain and source contact regions, 4 and 5, as well as over the gate insulating layer 3 in correspondence with the intermediate region 3A.
The O-TFT device 10 is then completed by a buffer layer 7 realized on the organic active layer 6, which a corresponding profile, and a final layer 8, usually made of an optical resist and also used to planarize the final device so obtained.
It has been discovered that in this kind of O-TFT device having a BC configuration, the polycrystalline pentacene of the organic active layer 6 degrades in an amorphous phase along boundaries of the drain and source contact regions, 4 and 5, decreasing the performance of the O-TFT device 10.
This known problem is reduced by using thin buffer layer 9 made of a monolayer of octadecyltrichlorosilane (OTS) and realized on the drain and source regions, 4 and 5, as well on the intermediate region 3A of the gate insulating layer 3 before the organic active layer 6 is deposited. In fact, it has been demonstrated that the interaction of the π-conjugated links with interfaces are thus decreased.
Referring to
For corresponding layers with respect to the O-TFT device 10 described with reference to
In particular, the O-TFT device 20 comprises a thick oxide protective layer 1 in which a gate region 2 is formed by doping a corresponding portion of the thick oxide protective layer 1, which is then covered by a gate insulating layer 3.
Moreover, on the gate insulating layer 3, a organic active layer 6, in particular a pentacene layer, is deposited.
Finally a drain contact region 4 and a source contact region 5 are formed on the organic active layer 6.
Due to the integration of the drain and source contact regions, 4 and 5, only after the deposition of the organic active layer 6, the O-TFT device 20 having a TC configuration is normally reported to have better performance with respect to the O-TFT device 10 having a BC configuration.
In particular, pentacene-thin-film transistors with a field-effect mobility of 3 cm2/Vs, without a thin buffer layer 9, have been realized by using a gate insulating layer 3 of PVP. Furthermore, pentacene-thin-film transistors have been realized by using a gate insulating layer 3 of polyimide with a field-effect mobility of 1 cm2/Vs. Such high mobility values can be achieved only through an effective control of the interface between the pentacene layer 6 and the gate insulating layer 3, that allows to reduce defects and grain boundaries.
However, the manufacturing of O-TFT device 20 having a TC configuration is nowadays difficult in an industrial context and not easily repeatable, due to the definition of the contact regions as well as of the terminal region of the integrated device so obtained on a pentacene layer.
In conclusion, O-TFT devices 20 having a BC configuration are more suitable from an industrial point of view, even if they require a control of the interfaces between pentacene, contact, and gate dielectric layers. In particular, an OTS thin buffer layer 9, which substantially improves the interface quality, can be used only with the dielectric layers that contain hydroxy groups (OH), allowing an OTS monolayer to self-assemble on their surfaces.
An embodiment of this invention provides an organic thin-film transistor device showing a good field-effect mobility and reduced manufacturing problems and costs, in this way overcoming the limits which still affect the devices realized according to the prior art.
More specifically, this embodiment of the invention is an organic thin-film transistor device which comprises a thin film of polymethylmetacrylate (PMMA) acting as a buffer layer for an organic active layer of pentacene.
Yet another embodiment of the invention further relates to a process for manufacturing such an organic thin-film transistor device on a substrate.
The characteristics and advantages of the organic thin-film transistor and corresponding manufacturing process according to an embodiment of the invention will be apparent from the following description of an embodiment thereof given by way of indicative and non limiting example with reference to the annexed drawings.
In the drawings:
The following discussion is presented to enable a person skilled in the art to make and use the invention. Various modifications to the embodiments will be readily apparent to those skilled in the art, and the generic principles herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
Referring to
To structurally and/or functionally equal elements, in particular layers, with respect to the O-TFT devices described with reference to
The O-TFT device 30 comprises a thick oxide protective layer 1, whereon a gate region 2 is formed, as well as a gate insulating layer 3, the latter covering both the gate region 2 and the thick oxide protective layer 1.
On the gate insulating layer 3, a drain contact region 4 and a source contact region 5 are then realized, spaced apart from each other and define therebetween a intermediate region 3A of the gate insulating layer 3 which is substantially aligned with the gate region 2.
The O-TFT device 30 further comprises an organic active layer 6, preferably a pentacene layer, which is deposited over the drain and source contact regions, 4 and 5, as well as over the gate insulating layer 3 in correspondence with the intermediate region 3A in a top contact configuration for sake of illustration only, an embodiment of the invention also relating to an O-TFT device having a BC configuration, as will be clear from the following description.
Advantageously according to an embodiment of the invention, the O-TFT device 30 comprises a thin buffer layer 31 of polymethylmetacrylate (PMMA), also known as Plexiglass. The PMMA thin buffer layer 31 is realized on the drain and source regions, 4 and 5, as well on the intermediate region 3A of the gate insulating layer 3 before the organic active layer 6 is deposited.
More particularly, the manufacturing process of the organic thin-film transistor according to an embodiment of the invention comprises the following steps.
A first formation step of a thick oxide protective layer 1 on a substrate, made silicon, or glass or other flexible material being suitable handled. It should be noted that embodiments of the present invention also apply to any kind of plastic material to be used to realize such a substrate, only requiring that a temperature whereat the substrate is damaged is not to be reached nor overcame.
In particular, the first formation step comprises a first cleaning step of the substrate to remove any contaminants or undesired particles and a step wherein the thick oxide protective layer 1 is realize, for instance by a ECR-PECVD (Electron Cyclotron Resonance Plasma Enhanced Chemical Vapour Deposition) at 250° C., particularly suitable for plastic substrate. It should be remarked that the thick oxide protective layer 1 acts as a mechanical, electrical and thermal insulation element for the substrate itself.
The process then comprises a step of depositing a metallic layer, for instance made of Au or Cr and having a thickness from 10 to 200 nanometers, preferably 50 nanometers, followed by a step of patterning this metallic layer in order to form the gate region 2.
A second formation step is then carried out on the gate region 2 and on the thick oxide protective layer 1 to form the gate insulating layer 3, by depositing a dielectric material or even by using an organic layer, with a thickness from 10 to 500 nanometers, preferably 100 nanometers, as shown in
After a second cleaning step, the process comprises a definition step of the drain contact region 4 and the source contact region 5, in turn comprising a step of deposition (sputtering or evaporating) of a metal layer with a thickness from 10 to 200 nanometers, preferably 20 nanometers, on the gate insulating layer 3, followed by an optical lithography and a wet attack, as shown in
Referring to
Advantageously, the integration step of the PMMA thin buffer layer 31 comprises a spinning step wherein a layer having a thickness of 5-10 nanometers is formed, followed by an annealing step at 90° C. for 10 minutes.
Referring to
More particularly, the step of forming the pentacene layer 6 comprises an evaporation step, for instance having an evaporation rate of 0.5-5 nm/min.
In this way, the PMMA thin buffer layer 31 does not enable a direct interface between the pentacene layer 6 and the metallic contact layers of the drain and source contact regions, 4 and 5, thus improving the performances of the organic thin-film transistor so obtained and its correct industrial reproducibility.
The O-TFT device 30 is then completed in a standard way.
It should be remarked that the PMMA thin buffer layer 31 reduces the interaction between a π-conjugated system of a pentacene layer and a metal or dielectric adjacent layer and that it can be used to realize thin-film transistors, both in bottom contact and top contact configuration, such thin-film transistors showing very high field-effect mobility (μFE=0.65 and 1.4 cm2/Vs, for bottom and top contact configuration, respectively) and a remarkably steep subthreshold region.
More particularly, it can be demonstrated that a PMMA thin buffer layer 31 improves the crystal quality along the metal contacts' boundaries, while still allowing good ohmic contact.
The Applicant has produced bottom and top contact O-TFT devices on heavily doped silicon wafers (acting as gate region 2) with a thermal silicon oxide 120-nm thick (acting as gate insulating layer 3).
More particularly, in a BC configuration, the source and drain contact region 4 and 5 (30-nm thick) have been defined by optical lithography and wet etching with channel lengths L=15, 25, 100, 500 μm and channel width W=200 μm. The samples have been annealed at 120° C. for 30 min, cleaned with HF:H20=1:80 for 5 s, and finally covered by spinning with a film of PMMA 950 K annealed at 90° C. for 10 min (thickness about 8 nm).
Thermal evaporation of pentacene (Sigma Aldrich 97%) has been performed on the samples with or without the PMMA thin buffer layer 31, with no extra purification process or substrate heating (evaporation rate about 3 nm/min, vacuum pressure 3*10−6 mbar).
Moreover, for a TC configuration, gold source and drain contacts have been evaporated through a shadow mask on top of the pentacene active layer (L=100 μm, W=200 μm).
Referring to
AFM measurements show that the pentacene film, grown on a SiO2 surface, exhibit a very good polycrystalline structure, with a characteristic “terrace” structure with a 1.6-nm step. However, referring to
In addition, AFM measurements on a wide number of samples show that the rms roughness of gold contacts (about 0.6 nm) is not appreciably modified by the presence of the PMMA thin buffer layer 31, indicating that no planarization effects are achieved for the used PMMA thickness.
It is thus clear that the role of the PMMA layer is primarily to allow an ordered pentacene growth by inhibiting the direct interaction of the π-conjugated pentacene system with metal or SiO2 surfaces.
Referring to
From the experimental data, a field-effect mobility μFE=0.65 (0.13) cm2/Vs, a subthreshold slope (measured at the onset of subthreshold region) of 0.57 (0.64) V/dec, a threshold voltage Vth=−6 (−5) V, and an on/off current ratio of 106 (106) can be estimated for devices with (without) the PMMA thin buffer layer 31.
In particular, it should be emphasized that O-TFT devices including a PMMA buffer layer according to an embodiment of the invention show parameters comparable to the best values reported for pentacene-based thin-film transistors according to the prior art. The main parameters of a group of representative devices are summarized in the following Table I, the devices having been measured at Vds=−1 V (W=200 μm, dox=130 nm, for all devices).
It should be noted that no significant difference can be observed between the mobility values deduced from the saturation regime (Vd=Vg) and the value obtained from the linear regime (Vd=−1 V).
Moreover, a good linear behavior at low Vd is observed, suggesting an efficient hole injection from the PMMA/Au contacts; in particular, referring to
Also, referring to
It can be seen that the electrical characteristics do not show the correct scaling for short L, while for L>25 μm the correct scaling is observed. This behavior can be caused by the series resistance induced by the PMMA thin buffer layer 31, indeed for small value of L, the channel resistance becomes comparable to parasitic resistance related to the transport through the PMMA thin buffer layer 31 itself.
To optimize the resistance of the PMMA thin buffer layer 31, different devices have been manufactured by changing the annealing temperature (90/180° C.) and the thickness (8/30 nm) of the PMMA thin buffer layer 31 indeed. The PMMA resistance increases with the increasing annealing temperature and thickness, and it has been discovered that an optimized value of the annealing temperature is 90° C. with a layer thickness of 8 nm: these conditions are a good compromise to get low series resistance while still having a continuous and homogeneous PMMA film.
However, by improving the control of PMMA film thickness, it could be still possible to further decrease the PMMA series resistance by reducing film thickness.
In order to better understand the influence of the series resistance induced by the PMMA layer, O-TFT devices have been realized in both bottom and top contact configuration, codepositing on the two types of substrates the same PMMA thin buffer layer 31 and pentacene layer 6. The transfer characteristics are compared in
This is quite surprising, especially considering that the oxide/PMMA/pentacene interfaces in the channel region of both devices are expected to be the same, as they have been cofabricated, and that, for a given Vg, the same amount of holes should be present in the channels of the two thin-film transistors.
This reduced current in the O-TFT device having a TC configuration is probably due to the effect of the series resistance induced by the vertical transport through the pentacene film and/or the pentacene/Au contact. As the gate voltage is increased in modulus, hole accumulation expands towards the back-channel region, decreasing pentacene vertical resistance as well as contact resistance.
In this case, the subthreshold region of O-TFT devices having a TC configuration is not controlled by the channel resistance, as also suggested by the known pentacene-film-thickness dependence of the electrical characteristics. On the contrary, above a threshold voltage value, such O-TFT devices having a TC configuration show higher on current, if compared to O-TFT devices having a BC configuration, suggesting that in this regime the PMMA series resistance limits the on current while the gate-controlled parasitic resistance in the O-TFT devices having a TC configuration becomes negligible. This last effect is confirmed by the correct L scaling of the on current in the O-TFT devices having a TC configuration.
In conclusion, an improved O-TFT device has been provided by using a polymethylmetacrylate (PMMA) layer as buffer layer between an organic active layer, in particular a pentacene layer.
The pentacene-thin-film transistor including the PMMA thin buffer layer shows very good performances both in BC and TC configuration.
Advantageously, the PMMA thin buffer layer 31 can be used in order to obtain a good interface quality between pentacene and SiO2 or Au layers, while still allowing good ohmic contact.
In particular, the realized O-TFT devices in the BC and TC configurations exhibit mobility, on/off current ratio, threshold voltage, and subthreshold slope values among the best reported in literature.
Finally, it should be pointed out that, advantageously according to an embodiment of the invention, the polymethylmetacrylate (PMMA), also known as Plexiglass, most often used as electronic resist, is one of the most common plastic material in electronics, thanks to a low-cost, low-temperature process, high stability, and easy processing.
Organic thin film transistors having the structure and formed according to the described embodiments of the present invention can be utilized in a variety of different types of electronic devices, such as memory devices, computer systems, communications devices such as cellular phones, personal digital assistants, and so on.
From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention.
