Patent Application
20090250690
This application claims priority from and the benefit of Korean Patent Application No. 10-2008-0015830, filed on Feb. 21, 2008, which is hereby incorporated by reference for all purposes set forth herein.
1. Field of the Invention
The present invention relates to an organic thin film transistor (TFT) substrate. More particularly, the present invention relates to an organic TFT substrate and a simplified method of manufacturing the organic TFT substrate.
2. Discussion of the Background
With the development of information technologies, the demand for high-performance display apparatuses capable of displaying various types of information, such as videos, graphics, and characters, has greatly increased. In response to this demand, the display industry has rapidly grown.
Particularly, since a liquid crystal display (LCD) has low power consumption, is slim and lightweight, and suppresses harmful electromagnetic waves as compared with a cathode ray tube (CRT), the LCD has been greatly advanced for several years as a next-generation high-technology display apparatus. In addition, the LCD has been extensively employed in various fields such as electronic clocks, electronic calculators, personal computers (PCs), and televisions (TVs). In such an LCD, liquid crystal cells arranged in a matrix type in a liquid crystal panel adjust light transmittance according to video signals, so that an image may be displayed.
Each liquid crystal cell uses a TFT as a switching device to independently supply video signals. An active layer of such a TFT may include amorphous silicon or poly silicon.
However, since an active layer including amorphous silicon or poly silicon is generally patterned through a thin film deposition process, a photolithography process, and an etching process, the manufacturing process may be complicated and costly.
In this regard, research has been actively conducted to provide an organic TFT including an organic semiconductor layer, which may be formed through a printing process, as an active layer. However, since a process of forming an organic TFT substrate uses masks when forming a gate metal pattern and a data metal pattern, the manufacturing cost may increase and additional processes my be required.
The present invention provides an organic thin film transistor (TFT) substrate that may be made by a simplified manufacturing process.
The present invention also provides a method of manufacturing the organic TFT substrate.
Additional features of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention.
The present invention discloses an organic TFT substrate including gate lines, data lines, a gate electrode, a source electrode, a drain electrode, a gate insulating layer, an organic semiconductor layer, and an organic protective layer. The gate lines and data lines are insulated from each other and cross each other to define pixel areas. The gate electrode is connected to the gate line. The source electrode is connected to the data line. The drain electrode faces the source electrode with the gate electrode disposed therebetween. The gate insulating layer covers the gate electrode while exposing a portion of the source and drain electrodes. The organic semiconductor layer contacts the source and drain electrodes. The organic protective layer is disposed on the organic semiconductor layer to protect the organic semiconductor layer.
The present invention also discloses a method of manufacturing an organic TFT substrate including forming gate lines, data lines, a gate electrode, a source electrode, and a drain electrode on a same plane of a substrate. A gate insulating layer is formed to cover the gate electrode wand expose a portion of the source and drain electrodes. An organic semiconductor layer contacts the source and drain electrodes. An organic protective layer is formed on the organic semiconductor layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the principles of the invention.
The invention is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.
It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms, “a”, “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “includes” and/or “including”, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Hereinafter, exemplary embodiments of the present invention will be explained in detail with reference to the accompanying drawings.
Referring to
The gate line 209 receives a scan signal from a gate driver (not shown) and the data line 208 receives a pixel signal from a data driver (not shown). The gate and data lines 209 and 208 have a double layer structure. Particularly, the gate lines 209 include a first conductive layer 209a and a second conductive layer 209b that are stacked on the substrate 101, and the data lines 208 include a first conductive layer 208a and a second conductive layer 208b that are stacked on the substrate 101. Although not shown in
When the organic TFT 160 is turned on and off, an insulating layer 106 may improve on-current and off-current characteristics of the organic TFT 160. The insulating layer 106 may include an inorganic insulating layer including inorganic substances or an organic insulating layer including organic substances. For example, the inorganic insulating layer may include silicon nitride (SiNx). Further, the organic insulating layer may include an organic substance such as polyvinylpyrrolidone (PVP), polyvinylacetate (PVA), phenolic polymer, acrylic polymer, imide polymer, fluorine polymer, or vinylalcohol polymer. The insulating layer 106 is patterned through photolithography and etching processes to cover a gate electrode 103 and partially exposes source and drain electrodes 108 and 109 to form a channel.
A bank insulating layer 112 is formed on the insulating layer 106 on the source and drain electrodes 108 and 109, and forms a hole 113 together with the insulating layer 106. The hole 113 formed by the bank insulating layer 112 and the insulating layer 106 exposes a part of the source and drain electrodes 108 and 109 to form the channel. The parts of the source and drain electrodes 108 and 109, which are exposed by the bank insulating layer 112 and the insulating layer 106, are connected with an organic semiconductor layer 114. The bank insulating layer 112 may include a photosensitive organic substance and may be treated with fluorine plasma. Thus, since the bank insulating layer 112 has water-resistant and oil-resistant characteristics, the plasma-processed bank insulating layer 112 allows a liquid-phase organic semiconductor to be easily defined within the bank insulating layer 112 when forming the organic semiconductor layer 114.
The organic TFT 160 allows the pixel signal supplied to the data line 208 to be charged to the pixel electrode 118 in response to the scan signal supplied to the gate line 209. To this end, the organic TFT 160 includes the gate electrode 103 connected to the gate line 209, the source electrode 108 connected to the data line 208, and the drain electrode 109 facing the source electrode 108 with the gate electrode 103 disposed therebetween and connected to the pixel electrode 118. Further, the organic TFT 160 includes the organic semiconductor layer 114 that overlaps the gate electrode 103 with the insulating layer 106 disposed therebetween to form the channel between the source and drain electrodes 108 and 109.
The organic semiconductor layer 114 is formed on the source and drain electrodes 108 and 109 and in the hole 113, which is formed by the bank insulating layer 112 and the insulating layer 106, in an overlapping area with the gate electrode 103. The organic semiconductor layer 114 includes an organic semiconductor substance such as pentacene, tetracene, anthracene, naphthalene, α-6T, α-4T, perylene, derivative of the perylene, rubrene, derivative of the rubrene, coronene, derivative of the coronene, perylene tetracarbocylic diimide, derivative of the perylene tetracarbocylic diimide, naphthalene tetracarboxylic dianhydride, derivative of the naphthalene tetracarboxylic dianhydride, a conjugated polymer derivative containing substituted or non-substituted thiophene, or a conjugated polymer derivative containing substituted fluorine.
The organic semiconductor layer 114 makes ohmic contact with the source and drain electrodes 108 and 109 through a self-assembled monolayer (SAM) process. In detail, the work function difference between the source/drain electrodes 108 and 109 and the organic semiconductor layer 114 is reduced through the self-assembled monolayer process. Thus, holes may be easily injected from the source and drain electrodes 108 and 109 to the organic semiconductor layer 114, so that contact resistance between the source and drain electrodes 108 and 109 and the organic semiconductor layer 114 may be reduced.
An organic protective layer 116 is formed on the organic TFT 160 to protect the organic TFT 160. As shown in
The pixel electrode 118 is formed on the organic protective layer 116 and the bank insulating layer 112 and is connected with the drain electrode 109 through a first contact hole 130 that exposes a portion of the drain electrode 109 and is formed through the bank insulating layer 112 and the insulating layer 106. Meanwhile, as shown in
The gate lines 209 are spaced apart from each other with the data lines 208 disposed therebetween, and a gate bridge 220 is formed on the bank insulating layer 112 to interconnect the gate lines 209. The gate bridge 220 is insulated from the data lines 208 and connected with the gate lines 209 through second contact holes 230.
Hereinafter, the method of manufacturing the organic TFT substrate according to one exemplary embodiment of the present invention will be described with reference to
As shown in
In detail, first and second conductive layers are sequentially stacked on the substrate 101 through a deposition method including sputtering. After stacking the first and second conductive layers, the first and second conductive layers are patterned through the photolithography and etching processes, thereby forming the conductive pattern including the gate line 209, the gate electrode 103, the source electrode 108, and the drain electrode 109. The first conductive layer may include ITO and the second conductive layer may include a metal material such as aluminum, molybdenum, chrome, or copper.
Alternatively, as shown in
As described above, the conductive pattern according to the present exemplary embodiment may have a single layer structure including the first conductive layer or a double layer structure including the first and second conductive layers that are stacked.
In exemplary embodiments of the present invention, the gate and data patterns are simultaneously formed using only one mask differently from the conventional method of forming the gate and data patterns using separate masks, thereby simplifying the manufacturing process by reducing the number of masks.
Then, as shown in
Then, as shown in
Then, as shown in
As shown in
Further, as shown in
According to the organic TFT substrate and the method of manufacturing the organic TFT substrate, gate, source, and drain electrodes are formed on the same plane, so that a gate metal pattern and a data metal pattern may be formed substantially simultaneously using one mask. Thus, the manufacturing process may be simplified.
It will be apparent to those skilled in the art that various modifications and variation can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2008-0015830 | Feb 2008 | KR | national |
