Embodiments of the invention generally relate to the field of digital data transmission over computer networks and particularly to error detection and correction within video channels.
The transmittal of video data over a video channel in modern digital video interface systems is generally subject to some non-zero bit error rate. Modern video interface standards e.g., High-Definition Multimedia Interface (HDMI), Mobile High-Definition Link (MHL) and other audio/video interface standards, support transmission of uncompressed video data and specify an acceptable bit error rate for the transmission of the video data. An occasional bit error in transmitted video data results in a corrupted pixel of the video data. However, the error rate of transmitted video data over a video channel in digital video interface systems based on HDMI, MHL and other audio/video interface standards is generally low such that the occasional bit error in the transmitted video data is not visible to human vision.
Development of modern digital audio/video interface, e.g., Display Stream Compression Standard (DSC), may support transmission of compressed digital video data. Supporting transmission of compressed digital video data by modern digital video interface systems faces challenges of providing efficient error detection and correction in transmitted digital video data because when compressed digital video data is transmitted, a single bit error can corrupt a large block of pixels of the digital video data and may be visible to human vision even if the errors are not frequent to occur.
A solution for generating error codes for digital data and detecting corrupted data bits in the digital data at a receiving end is described herein. The solution organizes codes words for the digital data into one or more orthogonal data blocks, where each code word has a data portion representing the content of the digital data and an error correction portion for detecting corrupted data bits in the data portion. By using orthogonal data blocks, the solution enables a sink device to detect and correct corrupted data bits resulting from a single transmission error in a data block and to detect corrupted data bits resulting from multiple transmission errors in a data block.
A source device receives digital data comprising uncompressed video data and its associated metadata and compresses the video data. The source device generates an error code for each data word representing the compressed video data and each data word representing the metadata associated with the video data. The data word and its corresponding error code are combined to form a code word. The source device organizes code words of the video data and its metadata into orthogonal data blocks and transmits the data blocks to a sink device. The sink device detects corrupted data bits in the received data based on analysis of the error codes of the code words in the data blocks. Organizing code words into orthogonal data blocks helps isolate corrupted data bits in data blocks and enables the sink device to detect and correct multiple corrupted data bits resulting from a single transmission error and to detect corrupted multiple data bits resulting from multiple transmission errors.
Embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements:
As used herein, “network” or “communication network” mean an interconnection network to deliver digital media content (including music, audio/video, gaming, photos/images, and others) between devices using any number of technologies, such as Serial ATA (SATA), Frame Information Structure (FIS), etc. A network includes a Local Area Network (LAN), Wide Area Network (WAN), Metropolitan Area Network (MAN), intranet, the Internet, etc. In a network, certain network devices may be a source of digital media content, such as a digital television tuner, cable set-top box, handheld device (e.g., personal device assistant (PDA)), video storage server, and other source device. Such devices are referred to herein as “source devices” or “transmitting devices”. Other devices may receive, display, use, or store digital media content, such as a digital television, home theater system, audio system, gaming system, video and audio storage server, and the like. Such devices are referred to herein as “sink devices” or “receiving devices”.
As used herein, a “video interface environment” refers to an environment including a source device and a sink device coupled by a transmission channel for transmitting video data and metadata associated with the video data. One example of a video interface environment is a HDMI environment, in which a source device (such as a DVD player) is configured to provide media content encoded according to HDMI protocol over an HDMI channel or a MHL3 channel to a sink device (such as television or other display).
It should be noted that certain devices may perform multiple media functions, such as a cable set-top box that can serve as a receiver (receiving information from a cable head-end) as well as a transmitter (transmitting information to a TV) and vice versa. In some embodiments, the source and sink devices may be co-located on a single local area network. In other embodiments, the devices may span multiple network segments, such as through tunneling between local area networks. It should be noted that although generating error codes for digital data and detecting corrupted data bits in received digital data is described herein in the context of a video interface environment, the error generating and detecting techniques described herein are applicable to other types of digital data transfer between a source device and a sink device, such as network data in a networking environment, and the like.
In one embodiment, the input data 104 has uncompressed video data 110 and metadata 111 associated with the video data 110. Examples of metadata associated with video data include high dynamic range metadata describing a range of the video data and video compression metadata describing characteristics of the video data, e.g., length of the video, bitrate and frame size of the video and/or characteristics of the encoding used to encode video frames of the video data, e.g., the type of compression algorithm. The input data 104 can be stored on a non-transitory computer-readable storage medium, such as a memory, or received from a source external to the source device 100, for example, from an external video server communicatively coupled to the source device 100 by the Internet or some other type of network.
The video compression module 112 is configured to digitally compress video of the video data 110. The video compression module 112 can implement compression using any known video encoding standards, for example, Display Stream Compression (DSC) of the Video Electronics Standards Association (VESA) and the like. Embodiments of the video compression module 112 may use any video compression schemes known to those of ordinary skills in the art, including, for example, discrete cosine transform (DCT), wavelet transform, quantization and entropy encoding. The video compression module 112 provides the compressed video data to the error code generator 200 for error code generation. The metadata associated with the video data 110 is provided directly to the error code generator 200 for error code generation.
The error code generator 200 generates error codes for the compressed video data and metadata associated with the video data. In one embodiment, the error code generator 200 receives a portion of compressed video data from the video compression module 112, and generates an error code based on the portion of compressed video data. In one embodiment, a portion of the compressed video data has multiple data words, each of which has multiple data bits. For each data word, the error code generator 200 generates an error code, which comprises a predetermined number of syndrome bits (also referred to as “parity bits”). Each data word and its corresponding error code are combined to form an error correction code word (or simply “code word”). In one embodiment, the error code generated by the error code generator 200 is added to the data word, e.g., using a multiplexor prior to being line encoded by the digital line encoder 114 and transmitted over the transmission channel 116.
In one embodiment, the error code generator 200 applies an error correction algorithm to each data word to generate the corresponding syndrome bits. Examples of error correction algorithms that can be used by the error code generator 200 include BCH codes, Reed-Solomon codes and Hamming error correction codes. The error code generator 200 chooses an error correction algorithm based on one or more factors, including, e.g., characteristics of the algorithm (such as cyclic or non-cyclic), size of code word, number of syndrome bits and number of errors within a code word that can be detected and corrected.
The error code generator 200 may further consider error code efficiency when choosing an error correction algorithm to use. The error code efficiency is defined as the ratio of the size of a data word over the size of its corresponding code word. For example, for a code word generated using BCH algorithm, having a total of 255 bits for the code word, 191 bits for the data word, up to 8 errors that can be corrected by the error code, the error code efficiency is 191/255, i.e., 0.749. For another example, for a code word generated using BCH algorithm, having a total of 255 bits for the code word, 247 bits for the data word, correcting 1 error by the error code, the error code efficiency is 247/255, i.e., 0.968.
The error code generator 200 similarly generates error codes for the metadata associated with the video data. For example, the error code generator 200 receives a portion of metadata associated with the video data. The portion of the received metadata has multiple data words, each of which has multiple data bits. For each data word, the error code generator 200 generates an error code, which comprises a predetermined number of syndrome bits. Each data word of the metadata and its corresponding error code are combined to form an error correction code word.
To improve error code efficiency, the error code generator 200 organizes the code words (e.g., the code words for compressed video data and the code words for metadata associated with the video data) according to an orthogonal data organization structure. In one embodiment, the error code generator 200 organizes the code words into one or more orthogonal data blocks. Each orthogonal data block has a number of code words, each of which has a number of data bits and corresponding syndrome bits. The bits that are in a single vertical column are sent to the digital line coder, e.g. the bits labeled 0, 1, 2, 3, 4, 5, 6, 7 from the left most column are sent to the digital line coder first. Next, the same bits 0 through 7 from the 2nd column are sent to the digital line coder second, and so forth.
Organizing code words into orthogonal data blocks allows for efficient correction of multiple bit errors. For the system shown in
Turning now to
Referring back to
The digital line encoder 114 outputs the line encoded code words onto the transmission channel 116 as a serial bit stream. In one embodiment, the line encoded code words for the compressed video data and the line encoded code words for the metadata associated with the compressed video data are output during different time intervals. For example, the line encoded code words for the compressed video data are output during an active interval and the line encoded code words for the metadata associated with the compressed video data are output during blanking intervals, where the active interval and blanking interval are defined according to the HDMI video interface standard.
The digital line decoder 118 of the sink device 102 is configured to receive and decode the line encoded code words from the source device 100. In one embodiment, the digital line decoder 118 applies a line decoding scheme corresponding to the line encoding scheme used by the digital line encoder 114. For example, responsive to the 8b/10b line encoding at the source device 110, the digital line decoder 118 converts a 10-bit data symbol to an 8-bit data symbol. The block buffer 120 is a memory or other storage medium configured to buffer code words decoded by the digital line decoder 118.
The video decompression module 124 is configured to decode video data received from the error correction module 122. The decoding process performed by the video decompression module 124 is an inversion of each stage of the encoding process performed by the video compression module 112 (except the quantization stage in lossy compression). For example, the video decompression module 124 performs decoding process according to the DSC coding standard responsive to the video compression module 112 encoding the video frame according to the DSC coding standard.
The error correction module 122 is configured to receive line decoded code words from the block buffer 120 and to detect and correct errors (i.e., corrupted data bits) in the code words. The transmittal of video data over a video channel in modern digital video interface systems is generally subject to some non-zero bit error rate. For example, a single bit error in a 10-bit TMDS data symbol transported over a transmission channel, e.g., the transmission channel 116, can corrupt up to all 8 bits in the line decoded data. With the code words organized in orthogonal data blocks, the error correction module 122 is enabled to detect corrupted data bits in the code words and correct multiple corrupted data bits resulting from a single TMDS transmission error.
In one embodiment, the error correction module 122 detects one or more errors in code words of a data block by checking the values of syndrome bits in each code word and differences among the values of the syndrome bits of the code words. Responsive to the values of the syndrome bits of all code words in the data block being a predefined value indicating error free, e.g., zero, the error correction module 122 determines that the data block does not have any errors. Responsive to the syndrome bits of all code words being non-zero, but having the same value, the error correction module 122 determines that the data block has 8 corrupted data bits resulting from a single transmission error. Responsive to the syndrome bits of multiple code words (but not all code words) being non-zero and the syndrome bits of the remaining code words having the value of zero, the error correction module 122 determines that the data blocks has a number of corrupted data bits resulting from a single transmission error, and the number of the corrupted data bits equals to the number of the code words having non-zero syndrome bits. Response to the syndrome bits of all code words being non-zero and the non-zero values of the syndrome bits being different, the error correction module 122 determines that there are multiple corrupted data bits in the data block resulting from multiple transmission errors.
Responsive to corrupted data bits resulting from a single transmission error, the error correction module 122 corrects the corrupted data bits in the code words. Any error correction schemes known to those of ordinary skill in the art can be used by the error correction module 112 for correcting the corrupted data bits. For example, responsive to code words having corrupted data bits in the data block resulting from a single transmission error, the error correction module 122 accesses the line decoded data stored in the block buffer 120 and corrects the corrupted bits by replacing the each corrupted bit with its inverse. Responsive to multiple corrupted data bits resulting from multiple transmission errors, the error correction module 122 detects the corrupted data bits and reports the detected errors for further processing.
The error code generator generates error codes comprising a number of syndrome bits for the compressed video data and its metadata a portion a time. In one embodiment, a portion of the compressed video data/metadata has multiple data words, each of which has a predefined number of data bits. For each data word, the error code generator generates 506 an error code having multiple syndrome bits and combines the data word with its corresponding error code into a code word. The size of the code word is configurable, e.g., 255 bits in total. Multiple code words are organized into an orthogonal data block, which helps isolate transmission errors in the code words.
Prior to transmission of the orthogonal data blocks to the sink device 102, a digital line encoder of the source device 100 line encodes 510 the code words, e.g., using 8b/10b line coding of TMDS standard. Other line coding schemes, such as 16b/18b, can be used by the digital line encoder of the source device 100. The source device 100 transmits 512 the line encoded code words over a transmission channel, e.g., a HDMI serial connection, to the sink device 102.
An error correction module of the sink device 102 analyzes 608 the code words and detects 610 the corrupted data bits in the code words of each data block. In one embodiment, the error correction module detects corrupted data bits in the code words of a data block by checking the syndrome bits of all code words of the data block, comparing the syndrome bits with a predefined value representing error free and comparing the values of the syndrome bits of the code words among themselves. Based on the checking and comparison, the error correction module detects the corrupted bits in the data block as illustrated through
Responsive to the corrupted data bits of a data block resulting from a single transmission error, e.g., an error to a 10-bit TMDS data symbol, the error correction module corrects 612 the corrupted data bits, e.g., by flipping those bits determined to be incorrect. Responsive to the corrupted data bits of a data block resulting from multiple transmission errors, the error correction module reports 614 the detection of corrupted data bits in the data block for further processing.
The foregoing description of the embodiments has been presented for the purpose of illustration; it is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above disclosure.
Some portions of this description describe the embodiments in terms of algorithms and symbolic representations of operations on information. These algorithmic descriptions and representations are commonly used by those skilled in the data processing arts to convey the substance of their work effectively to others skilled in the art. These operations, while described functionally, computationally, or logically, are understood to be implemented by computer programs or equivalent electrical circuits, microcode, or the like. Furthermore, it has also proven convenient at times, to refer to these arrangements of operations as modules, without loss of generality. The described operations and their associated modules may be embodied in software, firmware, hardware, or any combinations thereof.
Any of the steps, operations, or processes described herein may be performed or implemented with one or more hardware or software modules, alone or in combination with other devices. In one embodiment, a software module is implemented with a computer program product comprising a computer-readable medium containing computer program code, which can be executed by a computer processor for performing any or all of the steps, operations, or processes described.
Embodiments may also relate to an apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, and/or it may comprise a general-purpose computing device selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a non transitory, tangible computer readable storage medium, or any type of media suitable for storing electronic instructions, which may be coupled to a computer system bus. Furthermore, any computing systems referred to in the specification may include a single processor or may be architectures employing multiple processor designs for increased computing capability.
Embodiments may also relate to a product that is produced by a computing process described herein. Such a product may comprise information resulting from a computing process, where the information is stored on a non transitory, tangible computer readable storage medium and may include any embodiment of a computer program product or other data combination described herein.
Finally, the language used in the specification has been principally selected for readability and instructional purposes, and it may not have been selected to delineate or circumscribe the inventive subject matter. It is therefore intended that the scope of the embodiments be limited not by this detailed description, but rather by any claims that issue on an application based herein. Accordingly, the disclosure of the embodiments is intended to be illustrative, but not limiting.
This application claims the benefit of U.S. Provisional Application No. 61/973,837, filed Apr. 1, 2014, which is incorporated by reference in its entirety.
Number | Date | Country | |
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61973837 | Apr 2014 | US |