The present invention relates to an oscillating electrical circuit having multiple loops.
The basic concept of a single ended oscillator comprising an active element A and the feedback element p is illustrated in
This is further illustrated in
To achieve fast switching, the loop-gain may be increased by increasing the gain of the active device either by having a wider device, which is valid in the case of FET (Field Effect Transistor), or by increasing the bias current for the active device. However, increasing the power consumption is not desired and wider transistors will result in more parasitic capacitance, which counteracts fast switching. Moreover, it is not possible to control the phase of the injected current pulse in an optimal way with the common oscillator topologies shown in
In
b illustrates another oscillator circuit 100b in which a resonant element 101b is connected to the drains of active elements T1b and T2b. Active elements comprising two transistors T3b and T4b are connected with gate and drain common to T1b and T2b, respectively. The drain of T3b is connected to the common gates of T4b and T2b while the drain of T4b is connected to the common gates of T3b and T1b, constituting the feedback. The circuit is fed with a supply voltage 110b through the sources of T3b and T4b. The sources of transistors T1b and T2b are grounded, optionally through a current bias source 130b.
It is also possible to provide additional feedback elements in the circuit according to
Prior art according to “Design Issues in CMOS Differential LC Oscillators”, by A. Hajimiri et al, IEEE journal of Solid State Circuits, Vol. 34, No. 5, May 1999, discloses a topology for oscillators, in which fast switching and current pulse optimisation is achieved. However, this document is silence about the novel connection according to the present invention.
The objects of the present invention are to provide an oscillator with fast switching characteristics and current pulse optimisation. The presented invention allows realization in a very compact (and low parasitic) way. The characteristics will further allow very high frequency VCOs based on this topology.
Thus, the invention according to a preferred embodiment will provide a faster or/and more optimised switching resulting in lower oscillator phase noise for a fixed bias current.
In the preferred embodiment, the current between the source node and the ground obtains a lower amplitude for its DC component.
For these reasons an oscillator circuit comprises a resonant element, an active element, a feedback loop, and an additional feedback loop comprising a phase shifting element. The resonant element is connected to a drain of the active element and the feedback loop is connected to gate of the active element and resonant element and the additional feedback loop is connected between drain and gate of the active element.
The additional element may also be provided with supplementary amplification.
According to one embodiment of the invention, the oscillator circuit further comprises: two resonant elements, having a first common terminal fed from a supply voltage and second terminals connected to the drains of first and second transistors, respectively provided as active elements, feedback elements connected between the drain of the first transistor and gate of the second transistor, and a feedback for each transistor comprising the phase shifting element. Preferably, the feedback comprises an amplifier and inverter networks connected between drain and gate of the first and second transistor, respectively. The sources of the transistors may be connected to ground through one of directly, a current bias source, via a resistor, impeditive element or current generator. A voltage bias network may be connected to gates of the first and second transistors.
According to a second embodiment, the oscillator circuit comprises: a first transistor pair, a second transistor pair, a resonant element arranged connected to the drains of a first and a second active element pair, first and second active element pair, each transistor pair has gate and drain connected, wherein a drain of a first transistor in the transistor pair is connected to gate common of a second transistor in the transistor pair, a supply voltage source connected to the sources of the first and second transistors, and additional feedback elements connected between the drains and gates of the active elements.
The resonant elements may comprise one or several of LC circuits and the feedback elements may comprise capacitors or transformers.
The additional feedback loops may comprise transistors having their gates connected to the drains of the same transistors, respectively, and their outputs (drain) connected to the gates of transistors. A bias voltage can be applied to the sources of the feedback transistors.
Preferably, the feedback loop comprises an inverter network and/or an amplifier.
The invention also relates to a method of providing an oscillator with fast switching characteristics and current pulse optimization, the method comprising the steps of: arranging an oscillator circuit with a resonant element, an active element and a feedback loop, and providing the circuit with an additional feedback loop comprising a phase shifting element.
The invention also relates to an electrical circuit comprising an oscillator as mentioned above.
In the following, the invention will be further described in a non-limiting way with reference to the accompanying drawings, in which:
a and 1b schematically illustrate electrical circuits with oscillator topologies according to prior art,
a and 2b schematically illustrate electrical circuits with oscillator topologies according to the basic concept of the present invention corresponding to the circuits illustrated in
According to the invention, the circuits according to
Thus,
Even though active elements T1a and T2a are illustrated as MOS transistors, it is obvious that they may be substituted by any type of active elements. This is valid for all embodiments illustrated and described herein.
b illustrates another oscillator circuit 200b, in accordance with a second exemplary embodiment of the invention and corresponding to the circuit of
A more detailed exemplary implementation embodiment of the present invention is illustrated in
In a fourth exemplary embodiment as illustrated in
To verify the functionality of a circuit according to the present invention some simulations have been carried out. The graph of
In the simulated topology, the transistors are assumed as: NMOS 100 μm/0.1 μm (W/L=1000) and PMOS 50 μm/0.1 μm (W/L 500).
The oscillator of the invention may be used for any frequencies and within for example radio and communication applications.
The invention is not limited to the shown embodiments but can be varied in a number of ways without departing from the scope of the appended claims; the arrangement and the method can be implemented in various ways using different technologies depending on application, functional units, needs and requirements etc.
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/SE2005/001429 | 9/27/2005 | WO | 00 | 3/26/2008 |