Patent Application
20110156829
This application is based upon and claims the benefit of the priority of Japanese patent application No. 2009-297134, filed on Dec. 28, 2009, the disclosure of which is incorporated herein in its entirety by reference thereto.
This invention relates to an oscillator, and in particular, relates to an oscillator combined circuit, a semiconductor device, and a current reuse method, that are preferable for lowering power consumption when applied to a frequency synthesizer or the like.
In high frequency integrated circuits used in communication devices, mobile telephone units, and the like, it is necessary to generate a carrier signal by a local oscillator, and to lock frequency and phase of a carrier signal by using a phase locked loop (abbreviated as PLL).
In this configuration, respective DC supply currents are necessary to operate the voltage controlled oscillator 10, the frequency divider 20 and the mixer 60. Since these circuits operates in high frequency, relatively large power is consumed in the integrated circuit overall.
On the other hand, in a mobile communication device such as a mobile telephone unit or the like, in order to have a long standby time, lower power consumption in transmission and reception circuits is required.
As means of lowering power consumption, there exist various methods such as lowering an operation voltage or reducing a current in each functional block, and a technique of reusing a current of a functional block has been proposed. For example, Patent Document 1 (Patent Application Publication No. 2002-529949), as shown in
In this type of a stack configuration, an oscillation signal of the oscillator is supplied to the mixer in the form of an AC current and a DC supply current is supplied and with regard to a DC supply current of the oscillator, the DC supply current of the mixer is shared when viewed from the overall circuit, as a result of which the mixer current is saved and low power consumption is realized.
The entire disclosure of Patent Document 1 is incorporated herein by reference thereto. An analysis of related art is given as follows.
In the related art technology shown in
In accordance with one aspect of the present invention, there is provided an oscillator combined circuit comprising:
an oscillator including a resonance circuit that includes an inductor and a capacitors connected in parallel; and
a circuit including a differential pair that receives an oscillation output signal of the oscillator, and that forms first and second current paths from a first power supply, the first and second current paths having respective first ends on a side opposite to the first power supply coupled together and connected to the center tap of the inductor of the oscillator,
the oscillator and the circuit including the differential pair being cascode-connected between a second power supply and the first power supply.
In accordance with one aspect of the present invention, there is provided a method of reusing a current in a circuit comprising an oscillator having a resonance circuit including an inductor and a capacitor connected in parallel; and another circuit including a differential pair that receives an oscillation output signal of the oscillator and forms first and second current paths from a first power supply side, the method comprising:
connecting respective first ends of the first and second current paths on a side opposite to the first power supply in common to the center tap of the inductor of the oscillator;
cascode-connecting the oscillator and the another circuit between a second power supply and the first power supply; and
using, by the oscillator, a current supplied from the commonly connected first ends of the first and second current paths of the another circuit including the differential pair, as a power supply current of the oscillator.
According to the present invention, it is possible to share a DC power supply current by a circuit combined with an oscillator, to eliminate effect of a disturbing wave and avoid unstable operation of the oscillator, and to realize lower power consumption.
Still other features and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description in conjunction with the accompanying drawings wherein only exemplary embodiments of the invention are shown and described, simply by way of illustration of the best mode contemplated of carrying out this invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.
Preferred modes of the present invention will be described below.
The oscillator 100A, which includes a resonance circuit 110A and a cross pair 120, has output ends that provide differential outputs of an oscillation signal, and that are connected to input ends (differential input terminals) 210 of the differential circuit 300. The resonance circuit 110A includes a parallel circuit of an inductor (L) 111 and a capacitor which includes two capacitors (C) connected in series between the both ends of the inductor (L) 111. The capacitors (C) may be variable-capacitance elements in which a capacitance value is able to vary. The cross pair 120, which is connected between outputs of the resonance circuit 110A and ground, as shown in
Capacitors 240a and 240b connected between outputs of the oscillator 100A and the differential input terminals 210 are capacitors (coupling capacitors) for cutting off a DC current. The differential input terminals 210 of the differential circuit 300 are AC coupled via the coupling capacitors 240a and 240b to differential outputs of the oscillator 100A, and output a differential output signal from the differential output terminals 220. The differential circuit 300 has a power supply connection terminal 270 on one side (high potential side), and has a DC supply current terminal 230 on an opposite side (low potential side). The power supply terminal 270 is connected to a power supply. The DC supply current terminal 230 is connected to a center tap of the inductor 111 of the resonance circuit 110A, and a DC supply current is supplied to the nMOS transistors M11 and M12 of the cross pair 120 via the inductor 111.
Referring to
The frequency divider 200 has a power supply connection terminal 270, differential output terminals (frequency divided signal output terminal) 220 for differentially outputting a frequency divided signal, and a DC supply current terminal 230. The power supply connection terminal 270 is connected to a power supply, and the DC supply current terminal 230 is connected to a center tap of the inductor 111 of the resonance circuit of the VCO 100. The DC supply current is supplied to the nMOS transistors M11 and M12 of the VCO cross pair 120 via the inductor 111. The differential outputs of the VCO 100 is AC coupled via capacitors 240a and 240b (coupling capacitors) for DC cutoff to the differential input terminals 210 of the frequency divider 200. The frequency divider 200 differentially outputs a frequency divided signal from the differential output terminals (frequency divided output terminals) 220.
It is to be noted that in
The binary frequency divider 200 includes:
nMOS transistors M9 and M10 having coupled sources connected to a midpoint (center tap) of an inductor 111, and gates connected respectively to differential signal input ends 210a and 210b,
nMOS transistors M2 and M3 having coupled sources connected to a drain of the transistor M9, and each gate cross-connected to a drain of the other transistor,
nMOS transistors M1 and M4 having coupled sources connected to a drain of the transistor M10,
nMOS transistors M6 and M7 having coupled sources connected to a drain of the transistor M10, and each gate cross-connected to a drain of the other transistor, and
nMOS transistors M5 and M8 having coupled sources connected to the drain of the transistor M9.
The drains of the nMOS transistors M1 and M2, and the gates of the nMOS transistors M3 and M8 are connected to a first end of a load resistance element R1. A second end of the load resistance element R1 is connected to a power supply.
The drains of the nMOS transistors M3 and M4, and the gates of the nMOS transistors M2 and M5 are connected to a first end of a load resistance element R2. A second end of the load resistance element R2 is connected to the power supply.
The drains of the nMOS transistors M5 and M6, and the gates of the nMOS transistors M7 and M4 are connected to a first end of a load resistance element R3. A second end of the load resistance element R3 is connected to the power supply.
The drains of the nMOS transistors M7 and M8, and the gates of the nMOS transistors M6 and M1 are connected to a first end of a load resistance element R4. A second end of the load resistance element R4 is connected to the power supply. An output signal 220 is taken from a first end of the load resistance elements R3 and R4.
In the binary frequency divider 200 configured by the source coupled T flip-flops, differential signal input ends 210a and 210b are connected via capacitors 240a and 240b to terminals of the both ends of the inductor (L) 111 of a resonance circuit of the VCO 100.
Sources of the input transistors M9 and M10 of the binary frequency divider 200 are coupled and connected to a DC supply current terminal 230, to form a DC path (DC power supply current path), and are connected to a center tap of the inductor 111 of the resonance circuit 110.
A description is given below concerning circuit operation in
The VCO cross pair 120 that receives a DC supply current forms a negative resistance, forms an energy supply source of the resonance circuit 110 configured from the inductor 111 and varactors (varactor diode: variable capacitance element) 112a and 112b, and causes the VCO 100 to oscillate.
When the VCO 100 oscillates, an AC differential oscillator signal appears at the two ends (differential output terminals) of the VCO 100) of the inductor 111, and passes through the capacitors 240a and 240b to be applied to the gates of the nMOS transistors M9 and M10 of the binary frequency divider 200. The binary frequency divider 200 that receives this signal operates as a T flip-flop (reverses an output state each time an active state input signal is received), and a differential signal after frequency division of ½ of an oscillator signal frequency of the VCO 100 is outputted.
During the abovementioned operation, the value of the DC supply current is related to a voltage applied to a bias terminal 250. That is, the DC supply current of the VCO 100, determined by a bias voltage applied to the bias terminal 250, is entirely shared with the binary frequency divider 200.
As a result, regarding a function of the VCO 100 and the binary frequency divider 200, the DC supply current (power supply current) of the binary frequency divider 200 unit is 0, so that it is possible to realize lower power consumption.
Since the binary frequency divider 200 is configured as a source coupled type, according to a principle of differential operation, at a coupled source node, that is, the DC supply current terminal (DC path) 230, an AC current does not appear, and it is possible to supply the VCO 100 with a pure DC current.
In this way, the operation of the binary frequency divider 200 does not affect operation of the VCO 100. In addition, in a configuration of the related technology of a mixer and a VCO in
In a configuration of Example 1 shown in
In an actual circuit, even if there is a temperature variation or a power supply voltage variation, since a normal operation of a circuit characteristic, especially, the frequency divider 200, is required, it is necessary to have variation of the DC supply current as small as possible. There is some difficulty in appropriately generating the bias voltage of the bias terminal 250.
When an oscillation amplitude of the VCO 100 changes, the DC current flowing in the VCO cross pair 120 varies, and the supply current of the frequency divider 200 also varies. Thus, there is a possibility that a frequency range in which an operation can be assured will become narrow.
As a means for avoiding this problem, consideration may be given to arranging a constant current source at a source coupled end of the VCO cross pair 120.
However, if this is done, the number of transistor stages that are cascode-connected increases. As a result, in order to have a normal operation of transistors at each stage, it is necessary to increase a power supply voltage. This is in violation of the object of lowering power consumption. In a second example described below, an improvement is made with regard to this point.
An operation point of the nMOS transistors M10 and M9 connected to differential input terminals 210a and 210b of the binary frequency divider 110 is determined by an applied voltage (a gate voltage of the nMOS transistor M16) of a bias 1. An operation point of the transistors M11 and M12 of the VCO cross pair 120 is determined by an applied voltage (a gate voltage of the nMOS transistor M15) of a bias 2.
As a result thereof, even if an amplitude of an oscillation output signal of the VCO 100 changes, for example, its DC level is decided by the bias 2. Therefore, a DC voltage variation does not occur in source coupled ends of the nMOS transistors M11 and M12 of the VCO cross pair 120. Accordingly, a drain voltage of the nMOS transistor M13 that forms an output (constant current source) of a current mirror is constant, and variation of a current (drain-to-source current) is suppressed.
According to Example 2, without increasing a power supply voltage, it is possible to realize stability of the DC supply current with regard to the VCO 100 and the frequency divider 200 that share a current. As a result, an operation range of the frequency divider 200 can be easily assured, and this is particularly effective with respect to lowering power consumption.
Referring to
In
An output signal of a binary frequency divider 110 may be passed to a frequency divider 20 outside of a PLL (refer to
An operation of the buffer amplifier 400 will now be described. An output signal of the binary frequency divider 200 is differentially applied to gates of nMOS transistors M17 and M18 each operating as a source follower, and after crossing with capacitor coupling by capacitors 411b and 411a, also applied to gates of nMOS transistors M19 and M20 that operate as a source coupled differential circuit. A connection node of sources of the nMOS transistors M19 and M20 of the buffer amplifier 400, and a connection node of sources of nMOS transistors M9 and M10 of the binary frequency divider 200 are connected in common to a DC supply current terminal (DC path) 230, and are connected to a center tap of the inductor 111. A connection node of a source of the nMOS transistor M17 and a drain of the nMOS transistor M19 is an output terminal (node) 280a, and a connection node of a source of the nMOS transistor M18 and a drain of the nMOS transistor M20 is an output terminal (node) 280b.
The nMOS transistor M17 and nMOS transistor M19, each of which is configured as a source follower, operate as push-pull transistors, and the nMOS transistor M18 and nMOS transistor M20, each of which is configured as a source follower, operate as push-pull transistors.
When a rising pulse is supplied to a gate of the nMOS transistor M18, as an output 220 of the binary frequency divider 200, a falling pulse is supplied to a gate of the nMOS transistor M17, a drain-to-source current (source current) flowing from the nMOS transistor M18 to the output terminal 280b increases, and a drain-to-source current flowing from the nMOS transistor M17 to the output terminal 280a decreases. At this time, a drain-to-source current (sink current) of the nMOS transistor M20 that receives an output (a differential pulse of a negative polarity) of the capacitor 411b at its gate, decreases and a charging operation of the output terminal 280b is strengthened by the drain-to-source current of the nMOS transistor M18. On the other hand, a drain-to-source current of the nMOS transistor M19 that receives an output (a differential pulse) of the capacitor 411a at its gate, increases, and a discharging operation of the output terminal 280a is strengthened by the drain-to-source current of the nMOS transistor M19.
In the same way, when a rising pulse is supplied to a gate of the nMOS transistor M17, a falling pulse is supplied to a gate of the nMOS transistor M18, a drain-to-source current of the nMOS transistor M17 increases, a drain-to-source current of the nMOS transistor M18 decreases, a drain-to-source current of the nMOS transistor M19 that receives an output (a differential pulse of a negative polarity) of the capacitor 411a at is gate, decreases, and a drain-to-source current of the nMOS transistor M20 that receives output (a differential pulse of a positive polarity) of the capacitor 411b at is gate, increases. As a result, a discharging operation of the output terminal 280b is strengthened by the drain-to-source current of the nMOS transistor M20 a charging operation of the output terminal 280a is strengthened by the drain-to-source current of the nMOS transistor M17.
With regard to the binary frequency divider 200, even if an oscillation output signal (sinusoidal signal) from the VCO 100 is received, a differential output signal has a pulse waveform (transformed pulse wave) by a latch operation (an operation by a differential latch circuit) of the binary frequency divider 200. That is, other than a fundamental wave (frequency of ½ of an oscillation frequency of the VCO 100), a harmonic component such as a second harmonic, a third harmonic, and so forth, are included in the binary frequency divider 200 output (an output signal of the differential output terminal 220). After capacitance coupling by the capacitors 411a and 411b, this signal is applied to respective gates of the nMOS transistors M19 and M20. The fundamental wave and odd numbered harmonic wave signals do not affect DC bias, since a plus side and a minus side are in symmetry with a DC bias as a center. Even numbered harmonic wave signals such as a second harmonic wave and the like, affect the DC bias.
If the output oscillation (oscillation of an output signal of the differential output terminal 220) of the binary frequency divider 200 becomes large, a DC level becomes larger than a gate bias voltage of the nMOS transistors M19 and M20, by the presence of the even numbered harmonic signals. As a result, the DC supply current of the buffer amplifier 400 increases.
However, a total current of the binary frequency divider 200 and the buffer amplifier 400 is equivalent to a current of the DC supply current terminal 230, that is, the DC supply current of the VCO 100, and is set to a constant current value (steady value) of a constant current source M13. As a result, when the DC supply current of the buffer amplifier 400 increases, the DC supply current (current sum of current flowing in the nMOS transistors M9 and M10) of the binary frequency divider 200 decreases. As a result, an output amplitude of the binary frequency divider 200 (amplitude of the output signal of the differential output terminal 220) decreases. That is, according to the present exemplary embodiment, by providing the buffer amplifier 400, the output amplitude of the binary frequency divider 200 is more stably held, to provide an effect of improving operation stability.
In this regard, in a case of a configuration where the binary frequency divider 200 shown in
As described above, according to the present invention, in a high frequency circuit, the voltage control oscillator (VCO) having a relatively large current consumption and the frequency divider are made to share a DC supply current, without an increase of a power supply voltage, and a significant effect is achieved in lowering power consumption.
While sharing the power supply current, the VCO and the frequency divider can both operate stably.
It is to be noted that, in the abovementioned exemplary embodiment, a description was given according to an example of a configuration where the transistors forming the VCO cross pair 120, the transistors forming the frequency divider 200, and the transistors forming the bias and the constant current circuit 300 are nMOS transistors, but changing polarity, a configuration is also possible with PMOS transistors. Furthermore, the configuration of the voltage control oscillator is clearly not limited to the above-mentioned configuration or the like. Furthermore, in the above-mentioned exemplary embodiments, a description was given of MOS transistors as an example, but a configuration with bipolar transistors (bipolar junction transistors) is also possible. In this case, M1 to M12 of
Below, a description is given of correspondences between invention claims and embodiments. It is to be noted that reference symbols inside parentheses are for describing a configuration of the present invention, and clearly are not to be interpreted as limiting the present invention.
A device according to the present invention includes:
an oscillator including a resonance circuit (110, 110A) of a parallel in which an inductor (L) and a capacitor (C) are connected in parallel, and another circuit (200, 300) including a differential pair (M9 and M10) that receives an oscillation output signal of the oscillator and that forms first and second current paths from a first power supply side, wherein ends of the first and second current paths on a side opposite to the first power supply are coupled together and connected to a midpoint (center tap) of the inductor (L) of the oscillator and the oscillator and the another circuit are cascode-connected between a second power supply (GND) and the first power supply.
The device according to the present invention may include a frequency divider including the differential pair (M9 and M10).
A first transistor pair (M9 and M10) forming the differential pair receives, as differential inputs, outputs of the both ends of the resonance circuit at control terminals (gate terminals), second terminals (source terminals) of the first transistor pair are connected in common and are connected to the center tap of the inductor (111) of the oscillator and form a first end (230) on a side opposite to the first power supply of the current path, and first terminals (drain terminals) of the first transistor pair (M9 and M10) are connected to a path to the first power supply side.
The oscillator (100) may include first and second transistors (M11 and M12), with first terminals each connected to the both ends of the resonance circuit (110), and second terminals connected in common to the second power supply, wherein control terminals (gate terminals) of the first and second transistors are respectively cross-connected to first terminals (drain terminals) of the second and first transistors.
The oscillator (100) may include first and second variable capacitance elements (112a and 112b) in which the capacitors of the resonance circuit (110) are connected in series between the both ends of the inductor (111), and a control voltage (113) is applied to a connection node of the first and second variable capacitance elements. The control elements (gate terminals) of the first transistor pair (M9 and M10) of the differential stage are respectively AC coupled to outputs of both ends of the resonance circuit (110), and also are connected to a first bias voltage supply terminal (250 in
In the oscillator (100), control terminals (gate terminals) of the first and second transistors (M11 and M12) may be respectively cross-connected to first terminals (drain terminals) of the second and first transistors (M12 and M11) via fifth and sixth capacitors (121b and 121a of
In the present invention, a bias and constant current circuit (300 in
a third transistor (M13) that is connected between a second power supply (GND) and commonly connected second terminals (source terminals) of the first and second transistors (M11 and M12) of the oscillator (100);
a reference current source (310) having a first end connected to the first power supply; and
fourth to sixth transistors (M14 to M16) that are cascode connected between a second end of the reference current source (310) and the second power supply (GND), wherein the control terminal (gate terminal) of the fourth transistor (M14) is connected to the control terminal (gate terminal) of the third transistor (M13) and also is connected to a connection point of a second end of the reference current source (310) and the sixth transistor (M16). The control terminal (gate terminal) of the sixth transistor (M16) and the control terminal (gate terminal) of the fifth transistor (M15) are the first bias voltage supply terminal (bias 1) and the second bias voltage supply terminal (bias 2), respectively.
In the present invention, the frequency divider (200) may include a flip-flop including a transistor pair in which second terminals (sources) are coupled with the first terminals (drain terminals) of the first transistor pair (M9 and M10) of the differential stage, respectively.
In the present invention, the frequency divider (200) may include:
ninth and tenth transistors (M9 and M10 in
eleventh and fourteenth transistors (M1 and M4 in
twelfth and thirteenth transistors (M2 and M3 in
fifteenth and eighteenth transistors (M5 and M8 in
sixteenth and seventeenth transistors (M6 and M7 in
In the present invention, there may be provided a configuration in which the first terminals (drain terminals) of the eleventh and twelfth transistors (M11 and M12) and the control terminals (gate terminals) of the thirteenth and eighteenth transistors (M3 and M8) are connected in common and are connected to a first end of a first load element (R1 in
In the present invention, there may be provided a configuration in which second ends of the first to the fourth load elements (R1, R2, R3, and R4) are connected in common and are connected to the first power supply as a first power supply terminal of the frequency divider (200). The first ends of the third and fourth load elements (R3 and R4) are connected to a differential output pair (220 in
In the present invention, there may be provided a configuration in which an in-phase signal is differentially outputted from a first end of the third and fourth load elements (R3 and R4), and a quadrature signal is differentially outputted from a first end of the first and second load elements (R1 and R2).
In the present invention, there may be provided a buffer amplifier (400 in
seventh and eighth transistors (M17 and M18 in
nineteenth and twentieth transistors (M19 and M20 in
It is to be noted that each disclosure of the above-mentioned patent document is incorporated herein by reference. Modifications and adjustments of embodiments and examples are possible within the bounds of the entire disclosure (including the scope of the claims) of the present invention, and also based on fundamental technological concepts thereof. Furthermore, a wide variety of combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention clearly includes every type of transformation and modification that a person skilled in the art can realize according to the entire disclosure including the scope of the claims and to technological concepts thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2009-297134 | Dec 2009 | JP | national |
