Patent Application
20090066434
The present invention relates to an oscillator device comprising an oscillator core and a capacitive loading unit having a controllable capacitance value.
An oscillator device, such as a crystal oscillator, may be used to establish an operating frequency on which various units in a communication device are to operate. In a battery powered communication device, the power consumption is a critical parameter. Therefore, when there is no need for an oscillator signal, the oscillator device may be switched to a stand-by mode to save power.
The oscillator device may be used to generate a high-precision clock signal with low noise. To obtain a high-precision clock signal, a tank circuit with very high Q-value, typically based on a crystal, may be used. This results in that the start-up time may be relatively long (several ms). Hence, at start-up of the oscillator device, it may take some time before a useful oscillator signal has been generated. A useful oscillator signal may e.g. be a signal having a predetermined minimum amplitude or a predetermined frequency accuracy. The oscillator signal may be used as a system clock signal. One way to minimize power consumption is to provide a short start-up time of the oscillator device, thereby allowing the oscillator to be switched into stand-by mode often without loss of overall system performance.
The oscillator device may be implemented with an oscillator core connected to a capacitive loading unit. The capacitive loading unit may be controlled to provide different capacitive loading in response to a control signal. When designing the oscillator device, a compromise may have to be made concerning the capacitive loading resulting in a trade-off between tuning range and start-up time of the oscillator device. The tuning range may be set by the difference between the maximum and minimum capacitance value provided by the capacitive loading unit. However, the start-up time is, e.g. dependent on the minimum capacitance value provided by the capacitive loading unit. Thus, the tuning range may have some influence on the start-up time. Furthermore, the tuning range defines how much component parameter spread of components of the oscillator device, temperature variation and crystal aging that can be handled. Since the start-up time is dependent on the capacitive loading, it is desired to have as low minimum capacitive loading as possible to obtain a short start-up time.
The capacitive loading unit may be controllable to provide a first capacitive loading during start-up. Once the oscillator device is generating a useful oscillator signal, the capacitive loading unit may be controlled to provide a second capacitive loading giving the desired frequency of oscillation.
The capacitive loading unit may be controlled by a processor running software for the control. The processor may control the capacitive loading unit to provide either the first or the second capacitive loading. It is a disadvantage with this solution in that it put requirements on the system design, such as software, that is used to control start-up of the oscillator device, which makes it complex. If the system to which the oscillator device is connected comprises more than one user device of the oscillator signal, and each user device may request start-up of the oscillator device, the system design may become even more complex. The system may also become expensive to manufacture, as each user device e.g. needs software for controlling the start-up of the oscillator device.
US-A-5 844 448 discloses an oscillator circuit for providing fast start-up. The oscillator circuit comprises a first and a second bank of capacitors connected to a crystal. Only the first bank of capacitors is applied during start-up. The second bank of capacitors is controllable and may be switched in when the oscillator output has stabilized at a first oscillation frequency. A processor may be provided to control when the second bank of capacitors should be switched in to provide a desired oscillation frequency. The design according to this document is complex, as it involves a processor requiring software for the control of the start-up. Furthermore, the control of the start-up is based on the detection of the oscillation frequency of the oscillator device. The oscillation frequency is relatively complex to determine, as a reference clock may be required. Consequently, if the signal provided by the oscillator device is the first clock signal in a system in which the oscillator device is implemented, it may become difficult or even impossible to detect the oscillation frequency.
US-A-6 747 522 discloses a method of tuning a DCXO (Digitally Controlled Crystal Oscillator) by providing a coarse tuning array and a fine tuning array of capacitors. Each of the coarse and the fine tuning array of capacitors is tunable to provide a desired operating frequency. Control for short start-up time is not described in this document.
It is an object of the invention to provide an oscillator device with reduced complexity.
According to a first aspect, an oscillator device comprises an oscillator core and a capacitive loading unit having a controllable capacitance value and being connected to the oscillator core. The oscillator device further comprises a memory device including a first and a second memory unit and being connected to the capacitive loading unit. The first memory unit is adapted to store a first value to be supplied to the capacitive loading unit for controlling the capacitance value during a first time period. The first time period is a start-up period of the oscillator device. The second memory unit is adapted to store a second value to be supplied to the capacitive loading unit for controlling the capacitance value during a second time period. The second time period is an operational period of the oscillator device.
The memory device includes at least one control terminal for receiving a first and a second control signal, and is adapted to supply the first value to the capacitive loading unit in response to the first control signal and to supply the second value to the capacitive loading unit in response to the second control signal.
The oscillator core is adapted to generate at least the second control signal, which is dependent on the amplitude of an oscillator signal of the oscillator device.
The oscillator core may include an amplitude detection unit adapted to generate at least the second control signal in dependence of the amplitude of the oscillator signal.
The amplitude detection unit may be adapted to generate the second control signal when the amplitude of the oscillator signal exceeds a predefined threshold value.
The amplitude detection unit may form part of an Automatic Gain Control unit.
The amplitude detection unit may comprise a clock squarer operatively connected to an oscillator output and to a counter. The clock squarer may be adapted to generate a square wave in response to that the amplitude of said oscillator signal exceeds a predefined threshold value. The counter may be adapted to start counting when the clock squarer starts to generate the square wave and to generate the second control signal when it reaches a stop value.
The stop value of the counter may be programmable.
The first and second memory units may be registers.
The capacitive loading unit may include at least one digitally controllable capacitor circuit.
Each digitally controllable capacitor circuit may include at least one capacitor ladder.
The oscillator device may further comprise an input interface circuit adapted to provide an enable signal in response to a start-up request.
The input interface circuit may be connected to at least one external device adapted to generate the start-up request.
According to a second aspect, an electronic device comprises the oscillator device.
The electronic device may be a portable or handheld mobile radio communication equipment, a mobile radio terminal, a mobile telephone, a pager, a communicator, an electronic organizer, a smartphone or a computer.
According to a third aspect, a method for start-up of an oscillator device is provided, the oscillator device including an oscillator core, a capacitive loading unit having a controllable capacitance value and being connected to the oscillator core, a memory device operatively connected to the capacitive loading unit and to the oscillator core, the memory device including a first and a second memory unit. The method comprises supplying a first value stored in the first memory unit to the capacitive loading unit for controlling the controllable capacitance value during a first time period, which is a start-up period of the oscillator device. The method further comprises measuring the amplitude of an oscillator signal. A starting-time instant for a second time period is chosen as the time instant when the oscillator signal exceeds a predetermined threshold value. The second time period is an operational period of the oscillator device. Moreover, the method comprises supplying a second value stored in the second memory unit to the capacitive loading unit for controlling the capacitance value during the second time period.
Further embodiments of the invention are defined in the dependent claims.
It is an advantage of the invention that control of start-up is flexible, as control values for the capacitive loading unit are stored in the memory device. It is a further advantage of the invention that the complexity of the control of short start-up time of the oscillator device is low, resulting in an overall reduced complexity of the oscillator device and of a system in which the oscillator device may operate.
It should be emphasized that the term “comprises/comprising” when used in this specification is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.
Further objects, features and advantages of the invention will appear from the following detailed description of embodiments of the invention, reference being made to the accompanying drawings, in which:
a-7b are embodiments of amplitude detection units for the embodiment in
a-8b are circuit diagrams of capacitor ladders;
The capacitive loading unit may be connected to a crystal 6. The crystal 6 may be located off a chip on which the oscillator device 1 is located.
The first memory unit 5a is adapted to store a first value to be supplied to the capacitive loading unit 3 for controlling the capacitance value of the capacitive loading unit 3 during a first time period. The first time period may be a start-up phase of the oscillator device 1. The second memory unit 5b is adapted to store a second value to be supplied to the capacitive loading unit 3 for controlling the capacitance value of the capacitive loading unit 3 during a second time period. The second time period may be an operational phase of the oscillator device 1.
In the embodiments illustrated in the figures, components, which are similar or the same in the embodiments, are denoted by the same or similar reference numerals and will only be described once.
By providing the memory device 4 for storing the first and the second value, it is possible to provide short start-up time without the need to supply a value for setting the capacitance value of the capacitive loading unit 3 from an external device. Thus, the flexibility of the oscillator device is enhanced. Software for supplying the capacitance value to the capacitive loading unit 3 during the first time period will not be necessary. Consequently, the complexity of a system in which the oscillator device 1 may operate will be decreased.
The memory device 4 may include at least one control terminal for receiving a first and a second control signal. Furthermore, the memory device 4 may be adapted to supply the first value to the capacitive loading unit 3 in response to the first control signal and to supply the second value to the capacitive loading unit 3 in response to the second control signal. The first control signal may e.g. be a “0”. The second control signal may e.g. be a “1”. The first control signal may be generated by an external device or internally within the oscillator device 1. The second control signal may be generated by an external device or internally within the oscillator device 1. In an embodiment, the first control signal is supplied to the memory device 4 by applying a “0” to a control terminal of the memory device 4. The second control signal is supplied to the memory device 4 by applying a “1” to the control terminal. Generating the second control signal internally within the oscillator device 1 corresponds to initiating the transition from “0” to “1” internally within the oscillator device 1. Generating at least the second control signal internally within the oscillator device 1 has the advantage that the complexity of the oscillator device and external devices connected to the oscillator device 1 is reduced.
The oscillator core 2 may comprise an enable input terminal for receiving an enable signal for switching the oscillator device 1 from an OFF or idle mode to an ON mode. The enable signal may be generated by an external device, such as a processor 7 or CPU (Central Processing Unit), which runs software to provide the function. The processor 7 may be positioned in an external device. The external device may e.g. be an ASIC (Application Specific Integrated Circuit). Alternatively, the enable signal may be generated by an input interface circuit 17, which is adapted to respond to start-up requests from external devices, in the oscillator device 1.
The first control signal may be generated in response to the enable signal. In response to the first control signal, the capacitance value of the capacitive loading unit 3 is set during a first time period. The capacitive loading during the first time period is sufficiently low to obtain a start-up time that is shorter than the start-up time that would have been obtained if the capacitive loading to be applied during the second time period was used also during the first time period. Thus, the capacitive loading during the first time period is lower than the capacitive loading during the second time period.
The second control signal may be dependent on the amplitude of an oscillator signal generated by the oscillator device 1. The oscillator signal may be an output signal of the oscillator device 1. In order to obtain a stable operating frequency, it is important to have sufficient amplitude of the oscillator signal. When the amplitude of the oscillator signal has reached a certain threshold, a stable operating frequency may be obtained and the capacitive loading of the capacitive loading unit 3 may be set to a value determined by the second value stored in the second memory unit 5b. Detecting the amplitude of the oscillator signal is relatively easy. When the amplitude of the oscillator signal is below a threshold value, the first control signal may be generated. When the amplitude of the oscillator signal is equal to or above the threshold value, the second control signal may be generated.
In an alternative embodiment, the second control signal is generated a predetermined time period after the first control signal or the enable signal has been generated. The predetermined time period is dependent on the capacitance value determined by the first value stored in the first memory unit 5a. The smaller the capacitance value is during the first time period, the shorter the predetermined time period may be, at least up to a certain extent. The second control signal may be generated by a delay circuit included in the oscillator core 2. The delay circuit may be adapted to generate the second control signal in response to the enable signal. The delay circuit may be implemented with, e.g., one or more cascaded and capacitively loaded inverters.
The oscillator core 2 may be adapted to generate at least the second control signal, which may be dependent on the amplitude of the oscillator signal of the oscillator device 1. An amplitude detection unit 8 may be adapted to generate at least the second control signal. In one embodiment, the amplitude detection unit 8 is adapted to generate the first and the second control signal. The amplitude detection unit 8 may generate a signal, which may have a first and a second reference value or state. The first reference value or state may be represented with a voltage that is smaller than 0.2Vdd, where Vdd is a supply voltage of the oscillator device. The second reference value or state may be represented with a voltage that is larger than 0.8Vdd. The signal may be generated in response to detecting the predetermined amplitude threshold value of the oscillator signal. When the first level of the signal generated by the amplitude detection unit 8 is generated, the first control signal is provided. When the second level of the signal generated by the amplitude detection unit 8 is generated, the second control signal is provided.
The amplitude detection unit 8 may be adapted to generate the first and/or the second control signal in dependence of the amplitude of the oscillator signal. For example, the amplitude detection unit 8 may be adapted to generate the first control signal in response to detecting that the amplitude of the oscillator signal is below the predetermined amplitude threshold value. The amplitude detection unit 8 may be also adapted to generate the second control signal in response to detecting that the amplitude of the oscillator signal is equal to or higher than the predetermined amplitude threshold value. For example, the predetermined amplitude threshold value may be in the range of hundreds of mV.
The first and the second memory units 5a, 5b may be digital memory units. In an embodiment, the memory units 5a, 5b are digital memory registers. Thus, the first and the second values to be stored in the first and the second memory units 5a, 5b, respectively, may be digital values.
The capacitive loading unit 3 may include at least one digitally controllable capacitor circuit. Each digitally controllable capacitor circuit may e.g. be implemented with a varactor. Alternatively, each digitally controllable capacitor circuit includes a capacitor ladder.
The oscillator device 1 may include an input interface circuit 17 adapted to provide the enable signal in response to a start-up request from an external device. The start-up request may e.g. be issued by the processor 7 of the external device and may be received at an input terminal of the input interface circuit 17. The input interface circuit 17 may e.g. be implemented with a resistive component, such as a pull-down resistor, connected to ground and the input terminal of the input interface circuit 17. The use of a pull-down resistor allows one or more external devices to be connected to the input terminal of the input interface circuit 17. The external device may issue the start-up request by supplying a voltage having a first level, corresponding to a “1”, to the input terminal of the interface circuit 17. If no start-up request has been issued by an external device, i.e., no external voltage is supplied to the input terminal of the input interface circuit 17, then the voltage at the input terminal of the input interface circuit 17 is pulled to a second level, corresponding to a “0”, through the pull-down resistor. The first voltage level may be higher than the second voltage level. The input terminal of the input interface circuit 17 may also be connected to buffers in the input interface circuit 17 driving the enable signal internally in the oscillator device 1.
In an embodiment, the value stored in at least the second memory unit 5b may be varied, e.g., by the processor 7. Varying the value stored in the second memory unit 5b during the second time period changes the capacitance of the capacitive loading unit 3 during the second time period and, hence, the frequency of the oscillator device 1. Hence, allowing the value stored in the second memory unit 5b to be varied provides for tunability of the oscillator frequency during the second time period.
The serial interface 10 may be adapted to receive a digital value from an interface 12 connected to the processor 13, or directly from the processor 13, of the external device over a serial bus. The serial interface 10 is adapted to input the received data of the digital value into the second memory unit 5b. The serial interface 10 may also be adapted to communicate data to other units located on the same chip as the oscillator device.
The multiplexer 11 has at least one control terminal connected to the control terminal of the oscillator device 1 for receiving the first and the second control signals. Also, the multiplexer device comprises a first and a second input terminal connected to the first and the second memory units 5a, 5b, respectively. The multiplexer 11 may be adapted to output the value stored in the first memory unit 5a in response to the first control signal. Also, the multiplexer 11 may be adapted to output the value stored in the second memory unit 5b in response to the second control signal.
When the oscillator device 1 should be switched over to the operative phase, the last value programmed into the second memory unit 5b may be applied. Thus, the second memory unit 5b does not have to be reprogrammed, i.e. a new value does not have to be supplied to the second memory unit 5b, before a useful oscillator signal may be generated. Instead, the last value stored in the second memory unit 5b may be reused. Consequently, a useful oscillator signal may be generated without involvement of any external device.
Also shown in
Furthermore, the AM detector 50 may form part of an Automatic Gain Control (AGC). In an AGC implementation, the voltage at output terminal 60 may be operative to control the current drawn in the oscillator core 2. Referring to the embodiment illustrated in
a shows an embodiment of the amplitude detection unit 8 that may be used in the embodiment of the oscillator core illustrated in
b shows another embodiment of the amplitude detection unit 8 that may be used in the embodiment of the oscillator core 2 illustrated in
a illustrates an embodiment of the capacitive loading unit 3 embodied as a capacitor ladder. The capacitor ladder comprises a plurality of capacitor devices 70a, 70b, . . . 70n. The capacitor devices have equivalent design and function. Therefore, only capacitor device 70a will be described. Capacitor device 70a may be implemented with transistors, such as MOS transistors. Capacitor device 70a comprises a first transistor 71a and a second transistor 71b. The source and drain terminals of transistors 71a and 71b are all connected to a common node 72. The gates of the transistors 71a and 71b may be connected to terminals 73a and 73b of the capacitor ladder, respectively. The capacitor device 70a may have a first and a second state, such as on and off, with different associated capacitance values. The state may be controlled by one bit 74 of a digital control word supplied to the common node 72. The digital control word may be supplied over a bus 75. The number of bits in the control word supplied over the bus 75 is the same as the number of capacitor devices. Different values of the digital control word supplied over the bus 75 result in different capacitance values for the capacitive loading unit illustrated in
b illustrates another embodiment of the capacitive loading unit 3 embodied as a capacitor ladder. The capacitor ladder comprises a plurality of capacitor devices 80a, 80b, . . . 80n with essentially the same functionality as the capacitor devices 70a, 70b, . . . 70n illustrated in
Either of the capacitor ladders of
Different approaches may be used for the implementation in terms of choosing the capacitance values of the capacitor devices in the capacitor ladders. For example, a binary-weighted approach can be used, wherein the on-state capacitance of the capacitor device associated with the k:th bit is 2k−1 times a unit capacitance. This solution provides low complexity in that it allows the control word 75, 86 to be in binary representation resulting in a small number of bits. However, the binary-weighted approach may be susceptible to capacitance mismatch caused by parameter variations in components. An alternative solution is to use a thermometer-coded approach, wherein the on-state capacitance of all capacitor devices are equal. This approach is less susceptible to capacitor mismatch than the binary-weighted approach and guarantees that the capacitance of the capacitor ladder is a monotonic function of the control signal represented with the control word 75, 86. However, the thermometer-coded approach may result in a higher complexity since the control word 75, 86 is in thermometer-coded representation, which requires more bits than the binary-weighted approach. A hybrid between the binary-weighted and thermometer-coded approaches, wherein a first part of the control word 75, 86 is in binary representation and a second part is thermometer-coded, is an alternative approach.
In alternative embodiments, at least one capacitive loading unit 3, 3a, 3b, may be realized with a varactor diode which is digitally controlled via a digital-to-analog converter. In further alternative embodiments, at least one capactive loading unit may be realized with a capacitor ladder digitally controlled via a sigma-delta modulator. The digitally controlled capacitor ladder may comprise a single capacitance, which is switched in/out by the sigma-delta modulator.
According to the embodiments of the present invention, any of external devices 200, 300, 400 may request a clock signal. Consequently, short start-up time of the oscillator device 1 may be provided without having to power up the external device 100 or implement software in any of the external devices 200, 300, 400 to control the start up. Hence, system design becomes less complex.
In
The output signal from the oscillator device 1 may provide a clock signal. The clock signal may be the first clock signal that is provided in a system, wherein several devices, such as externals devices 100, 200, 300, 400, require a clock signal. The clock signal may also be the only clock signal provided in the system.
According to some embodiments, a method for fast start up of an oscillator device 1, illustrated with a flow chart in
In an embodiment, the method further comprises the step of determining a starting-time instant for the second time period. The starting-time instant for the second time period may be determined based upon when the amplitude of an oscillator signal exceeds a predetermined threshold value, as discussed above with regard to some of the embodiments of the oscillator device 1. The starting-time instant for the second time period may also be determined as a time instant occurring a predetermined amount of time after the reception of an enable signal at the oscillator core 2, as discussed above with regard to embodiments of the oscillator device 1.
The present invention has been described above with reference to specific embodiments. However, other embodiments than the above described are possible within the scope of the invention. Different method steps than those described above, performing the method by hardware or software, may be provided within the scope of the invention. The different features and steps of the invention may be combined in other combinations than those described. The scope of the invention is only limited by the appended patent claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 05111220.9 | Nov 2005 | EP | regional |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/EP06/68852 | 11/23/2006 | WO | 00 | 8/22/2008 |
