Claims
- 1. A method for error detection, comprising:
receiving a block of data that is divided into a plurality of sub-blocks having respective offsets within the block; processing the data in each of the sub-blocks so as to compute respective partial error detection codes for the sub-blocks; modifying the partial error detection codes of the sub-blocks responsive to the respective offsets; and combining the modified partial error detection codes to determine a block error detection code for the block of data.
- 2. A method according to claim 1, wherein processing the data in each of the sub-blocks comprises taking a modulo of the data.
- 3. A method according to claim 2, wherein taking the modulo comprises computing the modulo with respect to a predetermined polynomial, so as to determine a cyclic redundancy code (CRC) of the sub-block.
- 4. A method according to claim 3, wherein the block error detection code is equal to the CRC of the block of data computed with respect to the predetermined polynomial.
- 5. A method according to claim 2, wherein modifying the partial error detection codes comprises finding the modulo of respective offset factors for each of the sub-blocks based on the respective offsets, and multiplying the partial error detection codes by the modulo of the respective offset factors.
- 6. A method for detecting an error in a block of data to which an error detection code has been appended, the block having been divided for transmission over a network into a sequence of sub-blocks, each of the sub-blocks at a respective offset within the block of data, the method comprising:
receiving the sub-blocks in an order that does not necessarily correspond to the sequence; computing respective partial error detection codes for the sub-blocks in substantially the order in which the sub-blocks are received; combining the partial error detection codes of the sub-blocks to determine a total error detection code of the block; and comparing the total error detection code to the appended error detection code in order to detect the error.
- 7. A method according to claim 6, wherein combining the partial error detection codes comprises finding respective offsets of the sub-blocks within the block, and modifying the partial error detection codes responsive to the respective offsets.
- 8. A method according to claim 6, wherein receiving the sub-blocks comprises receiving over the network a series of data packets containing the sub-blocks.
- 9. A method according to claim 8, wherein receiving the series of data packets comprises receiving Transport Control Protocol/Internet Protocol (TCP/IP) packets.
- 10. A method according to claim 9, wherein receiving the sub-blocks comprises receiving the data in accordance with an Internet Small Computer System Interface (iSCSI) protocol.
- 11. A method according to claim 6, wherein the appended error detection code comprises a cyclic redundancy code (CRC) of the block of data, and wherein comparing the total error detection code to the appended error detection code comprises verifying that the total error detection code is equal to the CRC.
- 12. An error detection device, for calculating a block error detection code for a block of data that is divided into a plurality of sub-blocks having respective offsets within the block, the device comprising:
a sub-block code calculator, adapted to process the data in each of the sub-blocks so as to compute respective partial error detection codes for the sub-blocks; a position adjustment circuit, adapted to modify the partial error detection codes of the sub-blocks responsive to the respective offsets; and a combiner, coupled to combine the modified partial error detection codes to determine a block error detection code for the block of data.
- 13. A device according to claim 12, wherein the sub-block calculator is adapted to take a modulo of the data in each of the sub-blocks.
- 14. A device according to claim 13, wherein the sub-block calculator is adapted to compute the modulo with respect to a predetermined polynomial, so as to determine a cyclic redundancy code (CRC) of the sub-block.
- 15. A device according to claim 14, wherein the block error detection code is equal to the CRC of the block of data computed with respect to the predetermined polynomial.
- 16. A device according to claim 13, wherein the position adjustment circuit is adapted to find the modulo of respective offset factors for each of the sub-blocks based on the respective offsets, and to multiply the partial error detection codes by the modulo of the respective offset factors.
- 17. A data receiver, for receiving a block of data to which an error detection code has been appended, the block having been divided for transmission over a network into a sequence of sub-blocks, each of the sub-blocks at a respective offset within the block of data, the receiver comprising:
a sub-block receiving circuit, which is adapted to receive the sub-blocks in an order that does not necessarily correspond to the sequence; and an error detection circuit, coupled to compute respective partial error detection codes for the sub-blocks in substantially the order in which the sub-blocks are received, to combine the partial error detection codes of the sub-blocks to determine a total error detection code of the block, and to compare the total error detection code to the appended error detection code in order to detect the error.
- 18. A receiver according to claim 17, wherein the error detection circuit is adapted to determine respective offsets of the sub-blocks within the block, and to modify the partial error detection codes responsive to the respective offsets.
- 19. A receiver according to claim 17, wherein the sub-blocks are transmitted over the network to the receiver in a series of data packets containing the sub-blocks, and wherein the sub-block receiving circuit is adapted to extract the sub-blocks from the packets.
- 20. A receiver according to claim 19, wherein data packets comprise Transport Control Protocol/Internet Protocol (TCP/IP) packets.
- 21. A receiver according to claim 20, wherein the sub-blocks contain data transmitted in accordance with an Internet Small Computer System Interface (iSCSI) protocol.
- 22. A receiver according to claim 17, wherein the appended error detection code comprises a cyclic redundancy code (CRC) of the block of data, and wherein the error detection circuit is adapted to compare the total error detection code to the appended error detection code so as to verify that the total error detection code is equal to the CRC.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the benefit of U.S. Provisional Patent Application No. 60/283,896, filed Apr. 12, 2001, which is incorporated herein by reference.
Provisional Applications (1)
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Number |
Date |
Country |
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60283896 |
Apr 2001 |
US |