Claims
- 1. An output buffer circuit comprising:
- (a) first and second wells formed on a substrate of a first conductive type, both being of a second conductive type complementary to said first conductive type;
- (b) a first MOS transistor formed in said first well, having a drain and a source both of said first conductive type, a well electrode of said second conductive type for applying a potential to said first well, and a gate electrode;
- (c) a second MOS transistor formed in said second well, having a drain and source both of said first conductive type, a well electrode of said second conductive type for applying a potential to said second well, and a gate electrode;
- (d) an output terminal connected commonly to said source of said first MOS transistor, and said drain of said second MOS transistor;
- (e) a first potential point for applying a first potential to said drain of said first MOS transistor; and
- (f) a second potential point for applying a second potential different from said first potential, commonly to said source of said MOS transistor and said well electrode of said second MOS transistor,
- wherein said well electrode of said first MOS transistor is connected to said output terminal through a current limiting element for limiting a current flowing in itself and wherein said current limiting element includes a rectifying element.
- 2. An output buffer circuit of claim 1, wherein said current limiting element is a diode.
- 3. An output buffer circuit of claim 2, wherein said diode has a PN junction formed isolatedly from said substrate.
- 4. An output buffer circuit of claim 1, wherein said current limiting element is a constant voltage diode.
- 5. An output buffer circuit comprising:
- (a) first and second wells formed on a substrate of a first conductive type, both being of a second conductive type complementary to said first conductive type;
- (b) a first MOS transistor formed in said first well, having a drain and a source both of said first conductive type, a well electrode of said second conductive type for applying a potential to said first well, and a gate electrode;
- (c) a second MOS transistor formed in said second well, having a drain and source both of said first conductive type, a well electrode of said second conductive type for applying a potential to said second well, and a gate electrode;
- (d) an output terminal connected commonly to said source of said first MOS transistor, and said drain of said second MOS transistor;
- (e) a first potential point for applying a first potential to said drain of said first MOS transistor; and
- (f) a second potential point for applying a second potential different from said first potential, commonly to said source of said MOS transistor and said well electrode of said second MOS transistor,
- wherein said well electrode of said first MOS transistor is connected to said output terminal through a current limiting element for limiting a current flowing in itself and wherein said current limiting element has a rectifying property;
- wherein said current limiting element has a variable resistance value, presenting:
- a first resistance value when at least one of said first MOS transistor and second MOS transistor is turned on, and
- a second resistance value larger than said first resistance value when both said first MOS transistor and second MOS transistor are turned off.
Priority Claims (2)
Number |
Date |
Country |
Kind |
7-176084 |
Feb 1995 |
JPX |
|
7-337065 |
Dec 1995 |
JPX |
|
Parent Case Info
This application is a division of application Ser. No. 08/648,957, filed on May 16, 1996.
US Referenced Citations (12)
Foreign Referenced Citations (2)
Number |
Date |
Country |
1 43464 |
Sep 1989 |
JPX |
5 335504 |
Dec 1993 |
JPX |
Divisions (1)
|
Number |
Date |
Country |
Parent |
648957 |
May 1996 |
|